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2020-10-30gdb: introduce displaced_debug_printfSimon Marchi1-1/+1
Move all debug prints of the "displaced" category to use a new displaced_debug_printf macro, like what was done for infrun and others earlier. The debug output for one displaced step one amd64 looks like: [displaced] displaced_step_prepare_throw: stepping process 3367044 now [displaced] displaced_step_prepare_throw: saved 0x555555555042: 1e fa 31 ed 49 89 d1 5e 48 89 e2 48 83 e4 f0 50 [displaced] amd64_displaced_step_copy_insn: copy 0x555555555131->0x555555555042: b8 00 00 00 00 5d c3 0f 1f 84 00 00 00 00 00 f3 [displaced] displaced_step_prepare_throw: displaced pc to 0x555555555042 [displaced] resume_1: run 0x555555555042: b8 00 00 00 [displaced] displaced_step_restore: restored process 3367044 0x555555555042 [displaced] amd64_displaced_step_fixup: fixup (0x555555555131, 0x555555555042), insn = 0xb8 0x00 ... [displaced] amd64_displaced_step_fixup: relocated %rip from 0x555555555047 to 0x555555555136 On test case needed to be updated because it relied on the specific formatting of the message. gdb/ChangeLog: * infrun.h (displaced_debug_printf): New macro. Replace displaced debug prints throughout to use it. (displaced_debug_printf_1): New declaration. (displaced_step_dump_bytes): Return string, remove ui_file parameter, update all callers. * infrun.c (displaced_debug_printf_1): New function. (displaced_step_dump_bytes): Return string, remove ui_file parameter gdb/testsuite/ChangeLog: * gdb.arch/amd64-disp-step-avx.exp: Update displaced step debug expected output. Change-Id: Ie78837f56431f6f98378790ba1e6051337bf6533
2020-10-13gdb/testsuite/: Use "-qualified" in explicit "break main", etc.Pedro Alves3-6/+6
Similar to the previous patch, but this time add "-q" to tests that do "break main", "list main", etc. explicitly. gdb/testsuite/ChangeLog: * config/monitor.exp: Use "list -q". * gdb.arch/gdb1558.exp: Use "break -q". * gdb.arch/i386-permbkpt.exp: Use "break -q". * gdb.arch/i386-prologue-skip-cf-protection.exp: Use "break -q". * gdb.base/break.exp: Use "break -q", "list -q" and "tbreak -q". * gdb.base/commands.exp: Use "break -q". * gdb.base/condbreak.exp: Use "break -q". * gdb.base/ctf-ptype.exp: Use "list -q". * gdb.base/define.exp: Use "break -q". * gdb.base/del.exp: Use "break -q". * gdb.base/fullname.exp: Use "break -q". * gdb.base/hbreak-in-shr-unsupported.exp: Use "hbreak -q". * gdb.base/hbreak-unmapped.exp: Use "hbreak -q". * gdb.base/hbreak2.exp: Use "hbreak -q" and "list -q". * gdb.base/hw-sw-break-same-address.exp: Use "break -q" and "hbreak -q". * gdb.base/included.exp: Use "list -q". * gdb.base/label.exp: Use "break -q". * gdb.base/lineinc.exp: Use "break -q". * gdb.base/list.exp: Use "list -q". * gdb.base/macscp.exp: Use "list -q". * gdb.base/pending.exp: Use "break -q". * gdb.base/prologue-include.exp: Use "break -q". * gdb.base/ptype.exp: Use "list -q". * gdb.base/sepdebug.exp: Use "break -q", "list -q" and "tbreak -q". * gdb.base/server-del-break.exp: Use "break -q". * gdb.base/style.exp: Use "break -q". * gdb.base/symbol-without-target_section.exp: Use "list -q". * gdb.base/watchpoint-reuse-slot.exp: Use "hbreak -q". * gdb.cp/exception.exp: Use "tbreak -q". * gdb.dwarf2/dw2-error.exp: Use "break -q". * gdb.dwarf2/fission-mix.exp: Use "break -q". * gdb.dwarf2/fission-reread.exp: Use "break -q". * gdb.dwarf2/pr13961.exp: Use "break -q". * gdb.linespec/explicit.exp: Use "list -q". * gdb.linespec/linespec.exp: Use "break -q". * gdb.mi/mi-simplerun.exp: Use "--qualified". * gdb.python/py-mi-objfile-gdb.py: Use "list -q". * gdb.server/bkpt-other-inferior.exp: Use "break -q". * gdb.server/connect-without-multi-process.exp: Use "break -q". * gdb.trace/change-loc.exp: Use "break -q". * gdb.trace/pending.exp: Use "break -q". * gdb.tui/basic.exp: Use "list -q". * gdb.tui/list-before.exp: Use "list -q". * gdb.tui/list.exp: Use "list -q". * lib/gdb.exp (gdb_has_argv0): Use "break -q". Change-Id: Iab9408e90ed71cbb111cd737d2d81b5ba8adb108
2020-10-13'runto main' -> 'runto_main' throughoutPedro Alves1-1/+1
This commit does 's/runto main/runto_main/g' throughout. gdb/testsuite/ChangeLog: * gdb.ada/fun_in_declare.exp: Use "runto_main" instead of "runto main". * gdb.ada/small_reg_param.exp: Likewise. * gdb.arch/powerpc-d128-regs.exp: Likewise. * gdb.base/annota1.exp: Likewise. * gdb.base/anon.exp: Likewise. * gdb.base/breakpoint-in-ro-region.exp: Likewise. * gdb.base/dprintf-non-stop.exp: Likewise. * gdb.base/dprintf.exp: Likewise. * gdb.base/gdb11530.exp: Likewise. * gdb.base/gdb11531.exp: Likewise. * gdb.base/gnu_vector.exp: Likewise. * gdb.base/interrupt-noterm.exp: Likewise. * gdb.base/memattr.exp: Likewise. * gdb.base/step-over-syscall.exp: Likewise. * gdb.base/watch-cond-infcall.exp: Likewise. * gdb.base/watch-read.exp: Likewise. * gdb.base/watch-vfork.exp: Likewise. * gdb.base/watch_thread_num.exp: Likewise. * gdb.base/watchpoint-stops-at-right-insn.exp: Likewise. * gdb.guile/scm-frame-inline.exp: Likewise. * gdb.linespec/explicit.exp: Likewise. * gdb.opt/inline-break.exp: Likewise. * gdb.python/py-frame-inline.exp: Likewise. * gdb.reverse/break-precsave.exp: Likewise. * gdb.reverse/break-reverse.exp: Likewise. * gdb.reverse/consecutive-precsave.exp: Likewise. * gdb.reverse/consecutive-reverse.exp: Likewise. * gdb.reverse/finish-precsave.exp: Likewise. * gdb.reverse/finish-reverse.exp: Likewise. * gdb.reverse/fstatat-reverse.exp: Likewise. * gdb.reverse/getresuid-reverse.exp: Likewise. * gdb.reverse/i386-precsave.exp: Likewise. * gdb.reverse/i386-reverse.exp: Likewise. * gdb.reverse/i386-sse-reverse.exp: Likewise. * gdb.reverse/i387-env-reverse.exp: Likewise. * gdb.reverse/i387-stack-reverse.exp: Likewise. * gdb.reverse/insn-reverse.exp: Likewise. * gdb.reverse/machinestate-precsave.exp: Likewise. * gdb.reverse/machinestate.exp: Likewise. * gdb.reverse/pipe-reverse.exp: Likewise. * gdb.reverse/readv-reverse.exp: Likewise. * gdb.reverse/recvmsg-reverse.exp: Likewise. * gdb.reverse/rerun-prec.exp: Likewise. * gdb.reverse/s390-mvcle.exp: Likewise. * gdb.reverse/solib-precsave.exp: Likewise. * gdb.reverse/solib-reverse.exp: Likewise. * gdb.reverse/step-precsave.exp: Likewise. * gdb.reverse/step-reverse.exp: Likewise. * gdb.reverse/time-reverse.exp: Likewise. * gdb.reverse/until-precsave.exp: Likewise. * gdb.reverse/until-reverse.exp: Likewise. * gdb.reverse/waitpid-reverse.exp: Likewise. * gdb.reverse/watch-precsave.exp: Likewise. * gdb.reverse/watch-reverse.exp: Likewise. * gdb.threads/kill.exp: Likewise. * gdb.threads/tid-reuse.exp: Likewise. Change-Id: I70f457253836019880b4d7fb981936afa56724c2
2020-10-13PowerPC testsuite fails and duplicatesAlan Modra12-137/+6
binutils commit 5fbec329ec3 changed disassembly of mfvsrd and mtvsrd to be consistent with the mfvsrwz and mtvsrw/mtvsrwz, which favour output of the fp/vr extended mnemonic and regs over the vsx form. This patch fixes the following, and removes some duplicates. FAIL: gdb.arch/powerpc-power8.exp: found: mfvsrd r12,vs62 FAIL: gdb.arch/powerpc-power8.exp: found: mtvsrd vs48,r11 FAIL: gdb.arch/powerpc-vsx2.exp: found: mfvsrd r12,vs30 FAIL: gdb.arch/powerpc-vsx2.exp: found: mfvsrd r12,vs30 FAIL: gdb.arch/powerpc-vsx2.exp: found: mfvsrd r12,vs62 FAIL: gdb.arch/powerpc-vsx2.exp: found: mfvsrd r12,vs62 FAIL: gdb.arch/powerpc-vsx2.exp: found: mtvsrd vs11,r28 FAIL: gdb.arch/powerpc-vsx2.exp: found: mtvsrd vs11,r28 FAIL: gdb.arch/powerpc-vsx2.exp: found: mtvsrd vs43,r29 FAIL: gdb.arch/powerpc-vsx2.exp: found: mtvsrd vs43,r29 * gdb.arch/powerpc-altivec.s, * gdb.arch/powerpc-power7.s, * gdb.arch/powerpc-power8.s, * gdb.arch/powerpc-power9.s, * gdb.arch/powerpc-vsx.s, * gdb.arch/powerpc-vsx2.s: Remove duplicate instructions. * gdb.arch/powerpc-altivec.exp, * gdb.arch/powerpc-power7.exp, * gdb.arch/powerpc-power8.exp, * gdb.arch/powerpc-power9.exp, * gdb.arch/powerpc-vsx.exp, * gdb.arch/powerpc-vsx2.exp: Likewise, and update expected disassembly of mfvsrd/mtvsrd.
2020-10-13Re: gdb: Improve formatting of 'show architecture' messagesAlan Modra5-9/+9
Commit ccb9eba6a25 updated the testsuite for some targets without running the testsuite on those targets. This patch corrects the update, in most cases just adding the expected full-stop. On powerpc64le-linux, fixes these: FAIL: gdb.arch/powerpc-d128-regs.exp: checking for PPC arch FAIL: gdb.arch/powerpc-disassembler-options.exp: set architecture powerpc:common64 FAIL: gdb.arch/powerpc-disassembler-options.exp: set architecture rs6000:6000 FAIL: gdb.arch/ppc64-symtab-cordic.exp: show architecture I also verified that arm-linuxeabi and s390x-linux cross-builds now pass their disassembler-options.exp tests. * gdb.arch/arm-disassembler-options.exp: Adjust expected "target architecture" output. * gdb.arch/powerpc-d128-regs.exp: Likewise. * gdb.arch/powerpc-disassembler-options.exp: Likewise. * gdb.arch/ppc64-symtab-cordic.exp: Likewise. * gdb.arch/s390-disassembler-options.exp: Likewise.
2020-09-18gdb: Update i386_analyze_prologue to skip endbr32Victor Collod2-3/+3
With -m32 -fcf-protection, GCC generates an `endbr32` instruction at the function entry: [hjl@gnu-cfl-2 gdb]$ cat /tmp/x.c int main(void) { return 0; } [hjl@gnu-cfl-2 gdb]$ gcc -g -fcf-protection /tmp/x.c -m32 (gdb) b main Breakpoint 1 at 0x8049176: file /tmp/x.c, line 3. (gdb) r Breakpoint 1, main () at /tmp/x.c:3 3 { (gdb) disass Dump of assembler code for function main: => 0x08049176 <+0>: endbr32 0x0804917a <+4>: push %ebp 0x0804917b <+5>: mov %esp,%ebp 0x0804917d <+7>: mov $0x0,%eax 0x08049182 <+12>: pop %ebp 0x08049183 <+13>: ret End of assembler dump. (gdb) Update i386_analyze_prologue to skip `endbr32`: (gdb) b main Breakpoint 1 at 0x804917d: file /tmp/x.c, line 4. (gdb) r Breakpoint 1, main () at /tmp/x.c:4 4 return 0; (gdb) disass Dump of assembler code for function main: 0x08049176 <+0>: endbr32 0x0804917a <+4>: push %ebp 0x0804917b <+5>: mov %esp,%ebp => 0x0804917d <+7>: mov $0x0,%eax 0x08049182 <+12>: pop %ebp 0x08049183 <+13>: ret End of assembler dump. (gdb) Tested with $ make check RUNTESTFLAGS="--target_board='unix{-m32,}' i386-prologue-skip-cf-protection.exp" on Fedora 32/x86-64. 2020-0X-YY Victor Collod <vcollod@nvidia.com> gdb/ChangeLog: PR gdb/26635 * i386-tdep.c (i386_skip_endbr): Add a helper function to skip endbr. (i386_analyze_prologue): Call i386_skip_endbr. gdb/testsuite/ChangeLog: PR gdb/26635 * gdb.arch/amd64-prologue-skip-cf-protection.exp: Make the test compatible with i386, and move it to... * gdb.arch/i386-prologue-skip-cf-protection.exp: ... here. * gdb.arch/amd64-prologue-skip-cf-protection.c: Move to... * gdb.arch/i386-prologue-skip-cf-protection.c: ... here.
2020-09-11Add bfloat16 support for AVX512 register view.Felix Willgerodt2-0/+238
This adds support for the bfloat16 datatype, which can be seen as a short version of FP32, skipping the least significant 16 bits of the mantissa. Since the datatype is currently only supported by the AVX512 registers, the printing of bfloat16 values is only supported for xmm, ymm and zmm registers. gdb/ChangeLog: 2020-09-11 Moritz Riesterer <moritz.riesterer@intel.com> Felix Willgerodt <Felix.Willgerodt@intel.com> * gdbarch.sh: Added bfloat16 type. * gdbarch.c: Regenerated. * gdbarch.h: Regenerated. * gdbtypes.c (floatformats_bfloat16): New struct. (gdbtypes_post_init): Add builtin_bfloat16. * gdbtypes.h (struct builtin_type) <builtin_bfloat16>: New member. (floatformats_bfloat16): New struct. * i386-tdep.c (i386_zmm_type): Add field "v32_bfloat16" (i386_ymm_type): Add field "v16_bfloat16" (i386_gdbarch_init): Add set_gdbarch_bfloat16_format. * target-descriptions.c (make_gdb_type): Add case TDESC_TYPE_BFLOAT16. * gdbsupport/tdesc.cc (tdesc_predefined_types): New member bfloat16. * gdbsupport/tdesc.h (tdesc_type_kind): New member TDESC_TYPE_BFLOAT16. * features/i386/64bit-avx512.xml: Add bfloat16 type. * features/i386/64bit-avx512.c: Regenerated. * features/i386/64bit-sse.xml: Add bfloat16 type. * features/i386/64bit-sse.c: Regenerated. gdb/testsuite/ChangeLog: 2020-09-11 Moritz Riesterer <moritz.riesterer@intel.com> Felix Willgerodt <Felix.Willgerodt@intel.com> * x86-avx512bf16.c: New file. * x86-avx512bf16.exp: Likewise. * lib/gdb.exp (skip_avx512bf16_tests): New function.
2020-08-27gdb/testsuite: make test names unique in gdb.arch/*.expAndrew Burgess8-186/+188
Make the test names unique in gdb.arch/*.exp by either modifying the test names or using with_test_prefix. I have also fixed a typo 'forth' -> 'fourth' throughout gdb.arch/*. Finally, I replaced code like this: gdb_test "break [gdb_get_line_number "first breakpoint here"]" \ "Breakpoint .* at .*${srcfile}.*" \ "set first breakpoint in main" With this: gdb_breakpoint [gdb_get_line_number "first breakpoint here"] In those files that I was already modifying for the other reasons given above. gdb/testsuite/ChangeLog: * gdb.arch/amd64-byte.exp: Make test names unique, use gdb_breakpoint, and fix typo 'forth' -> 'fourth'. * gdb.arch/amd64-dword.exp: Likewise. * gdb.arch/amd64-pseudo.c: Fix typo 'forth' -> 'fourth'. * gdb.arch/amd64-stap-special-operands.exp: Make test names unique. * gdb.arch/amd64-tailcall-ret.exp: Likewise. * gdb.arch/amd64-word.exp: Make test names unique, use gdb_breakpoint, and fix typo 'forth' -> 'fourth'. * gdb.arch/i386-byte.exp: Make test names unique, use gdb_breakpoint. * gdb.arch/i386-word.exp: Likewise.
2020-08-25arc: Add ARCv2 XML target along with refactoringShahab Vahedi1-2/+2
A few changes have been made to make the register support simpler, more flexible and extendible. The trigger for most of these changes are the remarks [1] made earlier for v2 of this patch. The noticeable improvements are: - The arc XML target features are placed under gdb/features/arc - There are two cores (based on ISA) and one auxiliary feature: v1-core: ARC600, ARC601, ARC700 v2-core: ARC EM, ARC HS aux: common in both - The XML target features represent a minimalistic sane set of registers irrespective of application (baremetal or linux). - A concept of "feature" class has been introduced in the code. The "feature" object is constructed from BFD and GDBARCH data. It contains necessary information (ISA and register size) to determine which XML target feature to use. - A new structure (ARC_REGISTER_FEATURE) is added that allows providing index, names, and the necessity of registers. This simplifies the sanity checks and future extendibility. - Documnetation has been updated to reflect ARC features better. - Although the feature names has changed, there still exists backward compatibility with older names through find_obsolete_[core,aux]_names() functions. The last two points were inspired from RiscV port. [1] https://sourceware.org/pipermail/gdb-patches/2020-May/168511.html gdb/ChangeLog: * arch/arc.h (arc_gdbarch_features): New class to stir the selection of target XML. (arc_create_target_description): Use FEATURES to choose XML target. (arc_lookup_target_description): Use arc_create_target_description to create _new_ target descriptions or return the already created ones if the FEATURES is the same. * arch/arc.c: Implementation of prototypes described above. * gdb/arc-tdep.h (arc_regnum enum): Add more registers. (arc_gdbarch_features_init): Initialize the FEATURES struct. * arc-tdep.c (*_feature_name): Make feature names consistent. (arc_register_feature): A new struct to hold information about registers of a particular target/feature. (arc_check_tdesc_feature): Check if XML provides registers in compliance with ARC_REGISTER_FEATURE structs. (arc_update_acc_reg_names): Add aliases for r58 and r59. (determine_*_reg_feature_set): Which feature name to look for. (arc_gdbarch_features_init): Given MACH and ABFD, initialize FEATURES. (mach_type_to_arc_isa): Convert from a set of binutils machine types to expected ISA enums to be used in arc_gdbarch_features structs. * features/Makefile (FEATURE_XMLFILES): Add new files. * gdb/features/arc/v1-aux.c: New file. * gdb/features/arc/v1-aux.xml: Likewise. * gdb/features/arc/v1-core.c: Likewise. * gdb/features/arc/v1-core.xml: Likewise. * gdb/features/arc/v2-aux.c: Likewise. * gdb/features/arc/v2-aux.xml: Likewise. * gdb/features/arc/v2-core.c: Likewise. * gdb/features/arc/v2-core.xml: Likewise. * NEWS (Changes since GDB 9): Announce obsolence of old feature names. gdb/doc/ChangeLog: * gdb.texinfo (Synopsys ARC): Update the documentation for ARC Features. gdb/testsuite/ChangeLog: * gdb.arch/arc-tdesc-cpu.xml: Use new feature names.
2020-07-14gdb: Improve formatting of 'show architecture' messagesAndrew Burgess5-9/+9
This commit changes the output of 'show architecture'. Here is a session before this commit: (gdb) show architecture The target architecture is set automatically (currently i386) (gdb) set architecture mips The target architecture is assumed to be mips (gdb) show architecture The target architecture is assumed to be mips (gdb) After this commit the session now looks like this: (gdb) show architecture The target architecture is set to "auto" (currently "i386"). (gdb) set architecture mips The target architecture is set to "mips". (gdb) show architecture The target architecture is set to "mips". (gdb) The changes are: 1. The value is now enclosed in quotes, 2. Each line ends with '.', and 3. After setting the architecture GDB is now a little more assertive; 'architecture is set to' not 'is assumed to be', the user did just tell us after all! gdb/ChangeLog: * arch-utils.c (show_architecture): Update formatting of messages. gdb/testsuite/ChangeLog: * gdb.arch/amd64-osabi.exp: Update. * gdb.arch/arm-disassembler-options.exp: Update. * gdb.arch/powerpc-disassembler-options.exp: Update. * gdb.arch/ppc64-symtab-cordic.exp: Update. * gdb.arch/s390-disassembler-options.exp: Update. * gdb.base/all-architectures.exp.tcl: Update. * gdb.base/attach-pie-noexec.exp: Update. * gdb.base/catch-syscall.exp: Update. * gdb.xml/tdesc-arch.exp: Update.
2020-07-13Fix gdb.arch/i386-sse.exp with clangGary Benson1-1/+1
gdb.arch/i386-sse.exp fails to run with clang, because of: gdb compile failed, /gdbtest/src/gdb/testsuite/gdb.arch/i386-sse.c:56:40: warning: passing 'int *' to parameter of type 'unsigned int *' converts between pointers to integer types with different sign [-Wpointer-sign] if (!x86_cpuid (1, NULL, NULL, NULL, &edx)) ^~~~ /gdbtest/src/gdb/testsuite/../nat/x86-cpuid.h:35:41: note: passing argument to parameter '__edx' here unsigned int *__ecx, unsigned int *__edx) ^ 1 warning generated. Fix it by declaring edx unsigned. gdb/testsuite/ChangeLog: * gdb.arch/i386-sse.c (have_sse) <edx>: Make unsigned.
2020-06-25gdb/riscv: Loop over all registers for 'info all-registers'Andrew Burgess1-3/+7
Currently the 'info all-registers' command only loops over those registers that are known to GDB. Any registers that are unknown, that is, are mentioned in the target description, but are not something GDB otherwise knows, will not be displayed. This feels wrong, so this commit fixes this mistake. The output of 'info all-registers' now matches 'info registers all'. gdb/ChangeLog: * riscv-tdep.c (riscv_print_registers_info): Loop over all registers, not just the known core set of registers. gdb/testsuite/ChangeLog: * gdb.arch/riscv-tdesc-regs.exp: New test cases.
2020-06-25gdb/riscv: Record information about unknown tdesc registersAndrew Burgess1-2/+3
Making use of the previous commit, record information about unknown registers in the target description, and use this to resolve two issues. 1. Some targets (QEMU) are reporting three register fflags, frm, and fcsr, twice, once in the FPU feature, and once in the CSR feature. GDB does create two registers with identical names, but this is (sort of) fine, we only ever use the first one, and as both registers access the same target state things basically work OK. The only real problem is that the register names show up twice in 'info registers all' output. In this commit we spot the duplicates of these registers and then return NULL when asked for the name of these registers. This causes GDB to hide these registers from the user, fixing this problem. 2. Some targets (QEMU) advertise CSRs that GDB then can't read. The problem is these targets also say these CSRs are part of the save/restore register groups. This means that before an inferior call GDB tries to save all of these CSRs, and a failure to read one causes the inferior call to be abandoned. We already work around this issue to some degree, known CSRs are removed from the save/restore groups, despite what the target might say. However, any unknown CSRs are (currently) not removed in this way. After this commit we keep a log of the register numbers for all unknown CSRs, then when asked about the register groups, we override the group information for unknown CSRs, removing them from the save and restore groups. gdb/ChangeLog: * riscv-tdep.c (riscv_register_name): Return NULL for duplicate fflags, frm, and fcsr registers. (riscv_register_reggroup_p): Remove unknown CSRs from save and restore groups. (riscv_tdesc_unknown_reg): New function. (riscv_gdbarch_init): Pass riscv_tdesc_unknown_reg to tdesc_use_registers. * riscv-tdep.h (struct gdbarch_tdep): Add unknown_csrs_first_regnum, unknown_csrs_count, duplicate_fflags_regnum, duplicate_frm_regnum, and duplicate_fcsr_regnum fields. gdb/testsuite/ChangeLog: * gdb.arch/riscv-tdesc-regs.exp: Extend test case.
2020-06-25gdb/riscv: Improve support for matching against target descriptionsAndrew Burgess5-0/+359
For the RISC-V target it is desirable if the three floating pointer status CSRs fflags, frm, and fcsr can be placed into either the FPU feature or the CSR feature. This allows different targets to build the features in a way that better reflects their target. The change to support this within GDB is fairly simple, so this is done in this commit, and some tests added to check this new functionality. gdb/ChangeLog: * riscv-tdep.c (value_of_riscv_user_reg): Moved to here from later in the file. (class riscv_pending_register_alias): Likewise. (riscv_register_feature::register_info): Change 'required_p' field to 'required', and change its type. Add 'check' member function. (riscv_register_feature::register_info::check): Define new member function. (riscv_xreg_feature): Change initialisation of 'required' field. (riscv_freg_feature): Likewise. (riscv_virtual_feature): Likewise. (riscv_csr_feature): Likewise. (riscv_check_tdesc_feature): Take extra parameter, the csr tdesc_feature, rewrite the function to use the new riscv_register_feature::register_info::check function. (riscv_gdbarch_init): Pass the csr tdesc_feature where needed. gdb/testsuite/ChangeLog: * gdb.arch/riscv-tdesc-loading-01.xml: New file. * gdb.arch/riscv-tdesc-loading-02.xml: New file. * gdb.arch/riscv-tdesc-loading-03.xml: New file. * gdb.arch/riscv-tdesc-loading-04.xml: New file. * gdb.arch/riscv-tdesc-loading.exp: New file.
2020-06-25gdb/riscv: Take CSR names from target descriptionAndrew Burgess1-1/+38
First, consider the RISC-V register $x1. This register has an alias $ra. When GDB processes an incoming target description we allow the target to use either register name to describe the target. However, within GDB's UI we want to use the $ra alias in preference to the $x1 architecture name. To achieve this GDB overrides the tdesc_register_name callback with riscv_register_name. In riscv_register_name we ensure that we always return the preferred name, so in this case "ra". To ensure the user can still access the register as $x1 if they want to, when in riscv_check_tdesc_feature we spot that the target has supplied the register, we add aliases for every name except the preferred one, so in this case we add the alias "x1". This scheme seems to work quite well, the targets have the flexibility to be architecture focused if they wish (using x0 - x31) while GDB is still using the ABI names ra, sp, gp, etc. When this code was originally added there was an attempt made to include the CSRs in the same scheme. At the time the CSRs only had two names, one pulled from riscv-opc.h, and one generated in GDB that had the pattern csr%d. The idea was that if the remote targets description described the CSRs as csr%d then GDB would rename these back to the real CSR name. This code was only included because if followed the same pattern as the x-regs and f-regs, not because I was actually aware of any target that did this. However, recent changes to add additional CSR aliases has made me rethink the position here. Lets consider the CSR $dscratch0. This register has an alias 'csr1970' (1970 is 0x7b2, which is the offset of the CSR register into the CSR address space). However, this register was originally called just 'dscratch', and so, after recent commits, this register also has the alias 'dscratch'. As the riscv-opc.h file calls this register 'dscratch0' GDB's preferred name for this register is 'dscratch0'. So, if the remote target description includes the register 'dscratch0', then GDB will add the aliases 'dscratch', and 'csr1970'. In the UI GDB will describe the register as 'dscratch0', and all it good. The problem I see in this case is where the target describes the register as 'dscratch'. In this case GDB will still spot the register and add the aliases 'dscratch', and 'csr1970', GDB will then give the register the preferred name 'dscratch0'. I don't like this. For the CSRs I think that we should stick with the naming scheme offered by the remote target description. As the RISC-V specification evolves and CSR register names evolve, insisting on referring to registers by the most up to date name makes it harder for a target to provide a consistent target description for an older version of the RISC-V architecture spec. In this precise case the target offers 'dscratch', which is from an older version of the RISC-V specification, the newer version of the spec has two registers 'dscratch0' and 'dscratch1'. If we insist on using 'dscratch0' it is then a little "weird" (or seems so to me) when 'dscratch1' is missing. This patch makes a distinction between the x and f registers and the other register sets. For x and f we still make use of the renaming scheme, forcing GDB to prefer the ABI name. But after this patch the CSR register group, and also the virtual register group, will always prefer to use the name given in the target description, adding other names as aliases, but not making any other name the preferred name. gdb/ChangeLog: * riscv-tdep.c (struct riscv_register_feature::register_info): Fix whitespace error for declaration of names member variable. (struct riscv_register_feature): Add new prefer_first_name member variable, and fix whitespace error in declaration of registers. (riscv_xreg_feature): Initialize prefer_first_name field. (riscv_freg_feature): Likewise. (riscv_virtual_feature): Likewise. (riscv_csr_feature): Likewise. (riscv_register_name): Expand on comments. Remove register name modifications for CSR and virtual registers. gdb/testsuite/ChangeLog: * gdb.arch/riscv-tdesc-regs.exp: Extend test case.
2020-06-25gdb/riscv: Improved register alias name creationAndrew Burgess4-0/+285
This commit does two things: 1. Makes use of the DECLARE_CSR_ALIAS definitions in riscv-opc.h to add additional aliases for CSRs. 2. Only creates aliases for registers that are actually present on the target (as announced in the target XML description). This means that the 'csr%d' aliases that exist will only be created for those CSRs the target actually has, which is a nice improvement, as accessing one of the CSRs that didn't exist would cause GDB to crash with this error: valprint.c:1560: internal-error: bool maybe_negate_by_bytes(const gdb_byte*, unsigned int, bfd_endian, gdb::byte_vector*): Assertion `len > 0' failed. When we look at the DECLARE_CSR_ALIAS lines in riscv-opc.h, these can be split into three groups: DECLARE_CSR_ALIAS(misa, 0xf10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P9P1) The 'misa' register used to exist of offset 0xf10, but was moved to its current offset (0x301) in with privilege spec 1.9.1. We don't want GDB to create an alias called 'misa' as we will already have a 'misa' register created by the DECLARE_CSR(misa ....) call earlier in riscv-opc.h DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) These aliases are all CSRs that were removed in privilege spec 1.10, and whose addresses were reused by new CSRs. The names meaning of the old names is totally different to the new CSRs that have taken their place. I don't believe we should add these as aliases into GDB. If the new CSR exists in the target then that should be enough. DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P11) In privilege spec 1.11 the 'dscratch' register was renamed to 'dscratch0', however the meaning of the register didn't change. Adding the 'dscratch' alias makes sense I think. Looking then at the final PRIV_SPEC_CLASS_* field for each alias then we can see that currently we only want to take the alias from PRIV_SPEC_CLASS_1P11. For now then this is what I'm using to filter the aliases within GDB. In the future there's no telling how DECLARE_CSR_ALIAS will be used. I've heard it said that future RISC-V privilege specs will not reuse CSR offsets again. But it could happen. We just don't know. If / when it does we may need to revisit how aliases are created for GDB, but for now this seems to be OK. gdb/ChangeLog: * riscv-tdep.c (riscv_create_csr_aliases): Handle csr aliases from riscv-opc.h. (class riscv_pending_register_alias): New class. (riscv_check_tdesc_feature): Take vector of pending aliases and populate it as appropriate. (riscv_setup_register_aliases): Delete. (riscv_gdbarch_init): Create vector of pending aliases and pass it to riscv_check_tdesc_feature in all cases. Use the vector to create the register aliases. gdb/testsuite/ChangeLog: * gdb.arch/riscv-tdesc-regs-32.xml: New file. * gdb.arch/riscv-tdesc-regs-64.xml: New file. * gdb.arch/riscv-tdesc-regs.c: New file. * gdb.arch/riscv-tdesc-regs.exp: New file.
2020-06-24W/ Clang, compile/link C++ test programs with "-x c++"Pedro Alves1-1/+2
Some testcases want to compile .c files with a C++ compiler. So they pass the "c++" option to gdb_compile. That works fine with GCC, but with Clang, it results in: gdb compile failed, clang-5.0: warning: treating 'c' input as 'c++' when in C++ mode, this behavior is deprecated [-Wdeprecated] and the testcase is skipped with UNTESTED. A previous patch fixed a case like that in gdb.compile/compile-cplus.exp, by adding -Wno-deprecated to the build options. However, there are other testcases that use the same pattern, and all fail for the same reason. For example: gdb.base/info-types-c++.exp gdb.base/max-depth-c++.exp gdb.base/msym-lang.exp gdb.base/whatis-ptype-typedefs.exp gdb.btrace/rn-dl-bind.exp Fix this in a central place, within gdb_compile, by passing "-x c++" to the compiler driver when we're compiling/linking C++. This revealed that gdb.compile/compile-cplus.exp and gdb.arch/amd64-entry-value-paramref.exp tests are compiling an assembly file with the "c++" option, which would now fail to compile, with the C++ compiler not grokking the assembly, of course. We just need to not pass "c++" and all the other related C++ options when compiling an assembly file. gdb/testsuite/ChangeLog: 2020-06-24 Pedro Alves <palves@redhat.com> * gdb.arch/amd64-entry-value-paramref.exp: Use prepare_for_testing_full and don't pass "c++" for the .S file build spec. * gdb.compile/compile-cplus.exp: Don't compile $srcfile3 with $options, since it's an assembly file. Remove -Wno-deprecated. * lib/gdb.exp (gdb_compile): Pass "-x c++" explicitly when compiling C++ programs.
2020-05-29Fix file-not-found error with clang in gdb.arch/i386-{avx,sse}.cGary Benson2-2/+2
Clang fails to compile two testcases with the following error: fatal error: 'nat/x86-cpuid.h' file not found This prevents the following testcases from executing: gdb.arch/i386-avx.exp gdb.arch/i386-sse.exp Both testcases set additional_flags when building with GCC. This commit causes the additional_flags to also be used when building with clang. Note that, while fixing the build, this commit reveals several new failures when using clang to build the testsuite. gdb/testsuite/ChangeLog: * gdb.arch/i386-avx.exp (additional_flags): Also set when building with clang. * gdb.arch/i386-sse.exp (additional_flags): Likewise.
2020-05-27Fix some duplicate test namesLuis Machado5-56/+62
While doing a testsuite run on aarch64-linux, I noticed a bunch of duplicated test name results. It annoyed me a little, so I decided to go ahead and fix the worst offenders. The following patch brings the duplicate test names down from 461 to 137. The remaining ones are mostly scattered across the testsuite, with 1 to 3 duplicates per testcase. We can fix those as we go. gdb/testsuite/ChangeLog: 2020-05-27 Luis Machado <luis.machado@linaro.org> * gdb.arch/aarch64-sighandler-regs.exp: Fix duplicated test names. * gdb.arch/aarch64-tagged-pointer.exp: Likewise. * gdb.arch/arm-disassembler-options.exp: Likewise. * gdb.arch/arm-disp-step.exp: Likewise. * gdb.arch/thumb-prologue.exp: Likewise. * gdb.base/async.exp: Likewise. * gdb.base/auxv.exp: Likewise. * gdb.base/complex-parts.exp: Likewise. * gdb.base/ena-dis-br.exp: Likewise. * gdb.base/foll-exec.exp: Likewise. * gdb.base/permissions.exp: Likewise. * gdb.base/relocate.exp: Likewise. * gdb.base/return2.exp: Likewise. * gdb.base/sigbpt.exp: Likewise. * gdb.base/siginfo-obj.exp: Likewise. * gdb.cp/converts.exp: Likewise. * gdb.cp/exceptprint.exp: Likewise. * gdb.cp/inherit.exp: Likewise. * gdb.cp/nsnoimports.exp: Likewise. * gdb.cp/virtbase2.exp: Likewise. * gdb.mi/mi-var-cmd.exp: Likewise. * gdb.mi/var-cmd.c: Likewise.
2020-05-06gdb: handle endbr64 instruction in amd64_analyze_prologueSimon Marchi2-0/+86
v2: - test: build full executable instead of object - test: add and use supports_fcf_protection - test: use gdb_test_multiple's -wrap option - test: don't execute gdb_assert if failed to get breakpoint address Some GCCs now enable -fcf-protection by default. This is the case, for example, with GCC 9.3.0 on Ubuntu 20.04. Enabling it causes the `endbr64` instruction to be inserted at the beginning of all functions and that breaks GDB's prologue analysis. I noticed this because it gives many failures in gdb.base/break.exp. But let's take this dummy program and put a breakpoint on main: int main(void) { return 0; } Without -fcf-protection, the breakpoint is correctly put after the prologue: $ gcc test.c -g3 -O0 -fcf-protection=none $ ./gdb -q -nx --data-directory=data-directory a.out Reading symbols from a.out... (gdb) disassemble main Dump of assembler code for function main: 0x0000000000001129 <+0>: push %rbp 0x000000000000112a <+1>: mov %rsp,%rbp 0x000000000000112d <+4>: mov $0x0,%eax 0x0000000000001132 <+9>: pop %rbp 0x0000000000001133 <+10>: retq End of assembler dump. (gdb) b main Breakpoint 1 at 0x112d: file test.c, line 3. With -fcf-protection, the breakpoint is incorrectly put on the first byte of the function: $ gcc test.c -g3 -O0 -fcf-protection=full $ ./gdb -q -nx --data-directory=data-directory a.out Reading symbols from a.out... (gdb) disassemble main Dump of assembler code for function main: 0x0000000000001129 <+0>: endbr64 0x000000000000112d <+4>: push %rbp 0x000000000000112e <+5>: mov %rsp,%rbp 0x0000000000001131 <+8>: mov $0x0,%eax 0x0000000000001136 <+13>: pop %rbp 0x0000000000001137 <+14>: retq End of assembler dump. (gdb) b main Breakpoint 1 at 0x1129: file test.c, line 2. Stepping in amd64_skip_prologue, we can see that the prologue analysis, for GCC-compiled programs, is done in amd64_analyze_prologue by decoding the instructions and looking for typical patterns. This patch changes the analysis to check for a prologue starting with the `endbr64` instruction, and skip it if it's there. gdb/ChangeLog: * amd64-tdep.c (amd64_analyze_prologue): Check for `endbr64` instruction, skip it if it's there. gdb/testsuite/ChangeLog: * gdb.arch/amd64-prologue-skip-cf-protection.exp: New file. * gdb.arch/amd64-prologue-skip-cf-protection.c: New file.
2020-05-02[gdb/testsuite] Fix i386-mpx.exp compilation warningsTom de Vries5-0/+20
When running test-case gdb.arch/i386-mpx.exp with gcc-10, we get: ... Running src/gdb/testsuite/gdb.arch/i386-mpx.exp ... gdb compile failed, xgcc: warning: switch '-mmpx' is no longer supported xgcc: warning: switch '-fcheck-pointer-bounds' is no longer supported ... The test-case uses a combination of options, -mmpx and -fcheck-pointer-bounds. The -fcheck-pointer-bounds option requires the -mmpx option: ... $ gcc -fcheck-pointer-bounds ~/hello.c hello.c:1:0: warning: Pointer Checker requires MPX support on this target. \ Use -mmpx options to enable MPX. #include <stdio.h> cc1: error: ‘-fcheck-pointer-bounds’ is not supported for this target ... Both options is no longer supported in gcc-9. Fix the warnings by testing if the option combination is supported. Tested on x86_64-linux, with gcc-7.5.0 and gcc-10.0.1. gdb/testsuite/ChangeLog: 2020-05-02 Tom de Vries <tdevries@suse.de> * lib/gdb.exp (supports_mpx_check_pointer_bounds): New proc. * gdb.arch/i386-mpx-call.exp: Use supports_mpx_check_pointer_bounds. * gdb.arch/i386-mpx-map.exp: Same. * gdb.arch/i386-mpx-sigsegv.exp: Same. * gdb.arch/i386-mpx-simple_segv.exp: Same. * gdb.arch/i386-mpx.exp: Same.
2020-03-12gdb: make gdb.arch/amd64-disp-step-avx.exp actually test displaced steppingSimon Marchi2-1/+12
The test gdb.arch/amd64-disp-step-avx.exp is meant to test that doing a displaced step of an AVX instruction works correctly. However, I found (by pure coincidence) that the test instructions are not actually displaced stepped. Rather, they are inline-stepped, so the test is not actually testing what it's meant to test. This is what a portion of the test binary looks like: 0000000000400180 <_start>: 400180: 90 nop 0000000000400181 <main>: 400181: 90 nop 0000000000400182 <test_rip_vex2>: 400182: c5 fb 10 05 0e 00 00 vmovsd 0xe(%rip),%xmm0 # 400198 <ro_var> 400189: 00 000000000040018a <test_rip_vex2_end>: 40018a: 90 nop The instruction at 0x400182 is the one we want to test a displaced step for. A breakpoint is placed at 0x400182 and ran to. The execution is then resumed from there, forcing a step-over (which should normally be a displaced step) of the breakpoint. However, the displaced stepping buffer is at the _start label, and that means a breakpoint is present in the displaced stepping buffer. The breakpoint_in_range_p check in displaced_step_prepare_throw evaluates to true, which makes displaced_step_prepare_throw fail, forcing GDB to fall back on an in-line step. This can be easily observed by placing a `gdb_assert (false)` inside the breakpoint_in_range_p condition, in displaced_step_prepare_throw, and running gdb.arch/amd64-disp-step-avx.exp. The assertion will make the test fail. The proposed fix is to pad `_start` with a bunch of nops so that the test instruction is out of the displaced step buffer. I also think it would be good to enhance the test to make sure that we are testing displaced stepping as intended. I did that by enabling "set debug displaced on" while we step over the interesting instruction, and matching a message printed only when a displaced step is executed. gdb/testsuite/ChangeLog: * gdb.arch/amd64-disp-step-avx.S: Add nops after _start. * gdb.arch/amd64-disp-step-avx.exp: Enable "set debug displaced on" while stepping over the test instruction, match printed message.
2020-02-28Fix SVE-related failure in gdb.arch/aarch64-fp.expLuis Machado1-6/+6
The gdb.arch/aarch64-fp.exp test assumes it is dealing with a regular SIMD target that exposes the V registers as raw registers. SVE-enabled targets turn the V registers into pseudo-registers. That is all fine, but the testcase uses the "info registers" command, which prints pseudo-register's contents twice. One for the hex format and another for the natural format of the type. (gdb) info registers v0 v0 {d = {f = {0x0, 0x0}, u = {0x1716151413121110, 0x1f1e1d1c1b1a1918}, s = {0x1716151413121110, 0x1f1e1d1c1b1a1918}}, s = {f = {0x0, 0x0, 0x0, 0x0}, u = {0x13121110, 0x17161514, 0x1b1a1918, 0x1f1e1d1c}, s = {0x13121110, 0x17161514, 0x1b1a1918, 0x1f1e1d1c}}, h = {f = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u = {0x1110, 0x1312, 0x1514, 0x1716, 0x1918, 0x1b1a, 0x1d1c, 0x1f1e}, s = {0x1110, 0x1312, 0x1514, 0x1716, 0x1918, 0x1b1a, 0x1d1c, 0x1f1e}}, b = {u = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}, s = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}}, q = {u = {0x1f1e1d1c1b1a19181716151413121110}, s = {0x1f1e1d1c1b1a19181716151413121110}}} {d = {f = {1.846323925681849e-197, 8.5677456166123577e-159}, u = {1663540288323457296, 2242261671028070680}, s = {1663540288323457296, 2242261671028070680}}, s = {f = {1.84362032e-27, 4.84942184e-25, 1.27466897e-22, 3.34818801e-20}, u = {319951120, 387323156, 454695192, 522067228}, s = {319951120, 387323156, 454695192, 522067228}}, h = {f = {0.00061798, 0.00086308, 0.0012398, 0.00173, 0.0024872, 0.0034676, 0.0049896, 0.0069504}, u = {4368, 4882, 5396, 5910, 6424, 6938, 7452, 7966}, s = {4368, 4882, 5396, 5910, 6424, 6938, 7452, 7966}}, b = {u = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}, s = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}}, q = {u = {41362427191743139026751447860679676176}, s = {41362427191743139026751447860679676176}}} (gdb) p/x $v0 $1 = {d = {f = {0x0, 0x0}, u = {0x1716151413121110, 0x1f1e1d1c1b1a1918}, s = {0x1716151413121110, 0x1f1e1d1c1b1a1918}}, s = {f = {0x0, 0x0, 0x0, 0x0}, u = {0x13121110, 0x17161514, 0x1b1a1918, 0x1f1e1d1c}, s = {0x13121110, 0x17161514, 0x1b1a1918, 0x1f1e1d1c}}, h = {f = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, u = {0x1110, 0x1312, 0x1514, 0x1716, 0x1918, 0x1b1a, 0x1d1c, 0x1f1e}, s = {0x1110, 0x1312, 0x1514, 0x1716, 0x1918, 0x1b1a, 0x1d1c, 0x1f1e}}, b = {u = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}, s = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}}, q = {u = {0x1f1e1d1c1b1a19181716151413121110}, s = {0x1f1e1d1c1b1a19181716151413121110}}} Since the testcase is not expecting that, we run into a couple failures: FAIL: gdb.arch/aarch64-fp.exp: check register v0 value FAIL: gdb.arch/aarch64-fp.exp: check register v1 value The following patch switches to using "p/x" for printing register values, which prints the values once with the hex format, instead of twice. gdb/testsuite/ChangeLog 2020-02-28 Luis Machado <luis.machado@linaro.org> * gdb.arch/aarch64-fp.exp: Switch from "info registers" command to "p/x".
2020-02-28Fix gdb.arch/aarch64-dbreg-contents.exp build failuresLuis Machado1-0/+4
I ran into the following failures when running tests under QEMU: -- gdb compile failed, binutils-gdb/gdb/testsuite/gdb.arch/aarch64-dbreg-contents.c: In function 'set_watchpoint': binutils-gdb/gdb/testsuite/gdb.arch/aarch64-dbreg-contents.c:41:29: error: storage size of 'dreg_state' isn't known struct user_hwdebug_state dreg_state; ^~~~~~~~~~ In file included from /usr/include/aarch64-linux-gnu/bits/types/struct_iovec.h:23:0, from /usr/include/aarch64-linux-gnu/sys/uio.h:23, from binutils-gdb/gdb/testsuite/gdb.arch/aarch64-dbreg-contents.c:17: binutils-gdb/gdb/testsuite/gdb.arch/aarch64-dbreg-contents.c:69:18: error: invalid use of undefined type 'struct user_hwdebug_state' iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs) ^ binutils-gdb/gdb/testsuite/gdb.arch/aarch64-dbreg-contents.c:74:5: warning: implicit declaration of function 'error'; did you mean 'errno'? [-Wimplicit-function-declaration] error (1, errno, "PTRACE_SETREGSET: NT_ARM_HW_WATCH"); ^~~~~ errno binutils-gdb/gdb/testsuite/gdb.arch/aarch64-dbreg-contents.c: In function 'main': binutils-gdb/gdb/testsuite/gdb.arch/aarch64-dbreg-contents.c:87:3: warning: implicit declaration of function 'atexit'; did you mean '_Exit'? [-Wimplicit-function-declaration] atexit (cleanup); ^~~~~~ _Exit binutils-gdb/gdb/testsuite/gdb.arch/aarch64-dbreg-contents.c:89:11: warning: implicit declaration of function 'fork' [-Wimplicit-function-declaration] child = fork (); ^~~~ -- The following patch fixes those by adding the necessary include files. With that said, the test doesn't pass at present. I'll have to investigate it a bit more. gdb/testsuite/ChangeLog: 2020-02-28 Luis Machado <luis.machado@linaro.org> * gdb.arch/aarch64-dbreg-contents.c: Include stdlib.h, unistd, asm/ptrace.h and error.h.
2020-02-28Harden gdb.arch/aarch64-pauth.exp and fix a failureLuis Machado1-1/+6
When running this testcase against a QEMU with PAC support, i noticed we were failing to recognize the additional [PAC] that is emitted in the backtrace, resulting in this failure: FAIL: gdb.arch/aarch64-pauth.exp: backtrace I've made the test use multi_line to make the pattern more clear. Tested against aarch64-linux-gnu with and without PAC support. gdb/testsuite/ChangeLog: 2020-02-28 Luis Machado <luis.machado@linaro.org> * gdb.arch/aarch64-pauth.exp: Recognize optional PAC output.
2020-02-03gdb: fix powerpc disassembly testsRogerio Alves4-19/+15
This patch fixes test failures power8 and power9 caused by changes on opcodes: The dissasembler does not emit whitespace for instructions anymore (c2b1c2754526acff8aae2fe8f5a56c2dd11d0b7f) The dissasembler generates extended mnemonics for some instructions instead (aae9718e4d4e8d01dcee22684e82b000203d3e52) The ldmx instruction was removed. This instruction was never implemented (6fbc939cfdbdf02f205c20925583738b0f835e62) gdb/testsuite/ChangeLog: 2020-02-03 Rogerio A. Cardoso <rcardoso@linux.ibm.com> * gdb.arch/powerpc-power8.exp: Delete trailing whitespace of tbegin., tend. instructions. Replace bctar-, bctar+, bctarl-, bctarl+ extended mnemonics when avaliable by bgttar, bnstarl, blttar, bnetarl. * gdb.arch/powerpc-power8.s: Fix comments. Fix instructions binary for blttar, bnetarl. * gdb.arch/powerpc-power9.exp: Delete trailing whitespace of wait instruction. Delete ldmx test. * gdb.arch/powerpc-power9.s: Delete ldmx instruction.
2020-01-29Test handling of additional brk instruction patternsLuis Machado2-0/+100
New in v5: - Use gdb_test_name for gdb_test_multiple. - Use gdb_assert. - Verify count matches the expected sigtraps exactly. New in v4: - Fix formatting nit in gdb/testsuite/gdb.arch/aarch64-brk-patterns.c. New in v3: - Minor formatting and code cleanups. - Added count check to validate number of brk SIGTRAP's. - Moved count to SIGTRAP check conditional block. This test exercises the previous patch's code and makes sure GDB can properly get a SIGTRAP from various brk instruction patterns. GDB needs to be able to see the program exiting normally. If GDB doesn't support the additional brk instructions, we will see timeouts. We bail out with the first timeout since we won't be able to step through the program breakpoint anyway, so it is no use carrying on. gdb/testsuite/ChangeLog: 2020-01-29 Luis Machado <luis.machado@linaro.org> * gdb.arch/aarch64-brk-patterns.c: New source file. * gdb.arch/aarch64-brk-patterns.exp: New test.
2020-01-01Update copyright year range in all GDB files.Joel Brobecker279-279/+279
gdb/ChangeLog: Update copyright year range in all GDB files.
2019-11-21gdb/testsuite: skip gdb.arch/amd64-eval.exp when target is not x86_64Lukas Durfina1-0/+5
2019-11-01[ARM, thumb] Fix disassembling bug after reloading a symbol fileLuis Machado2-0/+84
The speed optimization from commit 5f6cac4085c95c5339b9549dc06d4f9184184fa6 made GDB skip reloading all symbols when the same symbol file is reloaded. As a result, ARM targets only read the mapping symbols the first time we load a symbol file. When reloaded, the speed optimization above will cause an early return and gdbarch_record_special_symbol won't be called to save mapping symbol data, which in turn affects disassembling of thumb instructions. First load and correct disassemble output: Dump of assembler code for function main: 0x0000821c <+0>: bx pc 0x0000821e <+2>: nop 0x00008220 <+4>: mov r0, #0 0x00008224 <+8>: bx lr Second load and incorrect disassemble output: Dump of assembler code for function main: 0x0000821c <+0>: bx pc 0x0000821e <+2>: nop 0x00008220 <+4>: movs r0, r0 0x00008222 <+6>: b.n 0x8966 0x00008224 <+8>: vrhadd.u16 d14, d14, d31 This happens because the mapping symbol data is stored in an objfile_key-based container, and that data isn't preserved across the two symbol loading operations. The following patch fixes this by storing the mapping symbol data in a bfd_key-based container, which doesn't change as long as the bfd is the same. I've also added a new test to verify the correct disassemble output. gdb/ChangeLog: 2019-11-01 Luis Machado <luis.machado@linaro.org> PR gdb/25124 * arm-tdep.c (arm_per_objfile): Rename to ... (arm_per_bfd): ... this. (arm_objfile_data_key): Rename to ... (arm_bfd_data_key): ... this. (arm_find_mapping_symbol): Adjust access to new bfd_key-based data. (arm_record_special_symbol): Likewise. gdb/testsuite/ChangeLog: 2019-11-01 Luis Machado <luis.machado@linaro.org> PR gdb/25124 * gdb.arch/pr25124.S: New file. * gdb.arch/pr25124.exp: New file. Change-Id: I22c3e6ebe9bfedad66d56fe9656994fa1761c485
2019-10-31[gdb/testsuite] Remove superfluous 3rd argument from gdb_test call (2)Tom de Vries2-32/+16
There's a pattern: ... gdb_test <command> <pattern> <command> ... that can be written shorter as: ... gdb_test <command> <pattern> ... Detect this pattern in proc gdb_test: ... global gdb_prompt upvar timeout timeout if [llength $args]>2 then { set message [lindex $args 2] + if { $message == [lindex $args 0] && [llength $args] == 3 } { + error "HERE" + } } else { set message [lindex $args 0] } ... and fix all occurrences in some gdb testsuite subdirs. Tested on x86_64-linux. gdb/testsuite/ChangeLog: 2019-10-31 Tom de Vries <tdevries@suse.de> * gdb.arch/amd64-disp-step-avx.exp: Drop superfluous 3rd argument to gdb_test. * gdb.arch/amd64-disp-step.exp: Same. * gdb.asm/asm-source.exp: Same. * gdb.btrace/buffer-size.exp: Same. * gdb.btrace/cpu.exp: Same. * gdb.btrace/enable.exp: Same. * gdb.dwarf2/count.exp: Same. * gdb.dwarf2/dw2-ranges-func.exp: Same. * gdb.dwarf2/dw2-ranges-psym.exp: Same. * gdb.fortran/vla-datatypes.exp: Same. * gdb.fortran/vla-history.exp: Same. * gdb.fortran/vla-ptype.exp: Same. * gdb.fortran/vla-value.exp: Same. * gdb.fortran/whatis_type.exp: Same. * gdb.guile/guile.exp: Same. * gdb.multi/tids.exp: Same. * gdb.python/py-finish-breakpoint.exp: Same. * gdb.python/py-framefilter.exp: Same. * gdb.python/py-pp-registration.exp: Same. * gdb.python/py-xmethods.exp: Same. * gdb.python/python.exp: Same. * gdb.server/connect-with-no-symbol-file.exp: Same. * gdb.server/no-thread-db.exp: Same. * gdb.server/run-without-local-binary.exp: Same. * gdb.stabs/weird.exp: Same. * gdb.threads/attach-many-short-lived-threads.exp: Same. * gdb.threads/thread-find.exp: Same. * gdb.threads/tls-shared.exp: Same. * gdb.threads/tls.exp: Same. * gdb.threads/wp-replication.exp: Same. * gdb.trace/ax.exp: Same. * lib/gdb.exp (gdb_test_exact, help_test_raw): Same. Change-Id: I2fa544c68f8c0099a77e03ff04ddc010eb2b6c7c
2019-09-24[gdb/tdep] Handle mxcsr kernel bug on Intel Skylake CPUsTom de Vries1-2/+17
On my openSUSE Leap 15.1 x86_64 Skylake system with the default (4.12) kernel, I run into: ... FAIL: gdb.base/gcore.exp: corefile restored all registers ... The problem is that there's a difference in the mxcsr register value before and after the gcore command: ... - mxcsr 0x0 [ ] + mxcsr 0x400440 [ DAZ OM ] ... This can be traced back to amd64_linux_nat_target::fetch_registers, where xstateregs is partially initialized by the ptrace call: ... char xstateregs[X86_XSTATE_MAX_SIZE]; struct iovec iov; amd64_collect_xsave (regcache, -1, xstateregs, 0); iov.iov_base = xstateregs; iov.iov_len = sizeof (xstateregs); if (ptrace (PTRACE_GETREGSET, tid, (unsigned int) NT_X86_XSTATE, (long) &iov) < 0) perror_with_name (_("Couldn't get extended state status")); amd64_supply_xsave (regcache, -1, xstateregs); ... after which amd64_supply_xsave is called. The amd64_supply_xsave call is supposed to only use initialized parts of xstateregs, but due to a kernel bug on intel skylake (fixed from 4.14 onwards by commit 0852b374173b "x86/fpu: Add FPU state copying quirk to handle XRSTOR failure on Intel Skylake CPUs") it can happen that the mxcsr part of xstateregs is not initialized, while amd64_supply_xsave expects it to be initialized, which explains the FAIL mentioned above. Fix the undetermined behaviour by initializing xstateregs before calling ptrace, which makes sure we get a 0x0 for mxcsr when this kernel bug occurs, and which also happens to fix the FAIL. Furthermore, add an xfail for this FAIL which triggers the same kernel bug: ... FAIL: gdb.arch/amd64-init-x87-values.exp: check_setting_mxcsr_before_enable: \ check new value of MXCSR is still in place ... Both FAILs pass when using a 5.3 kernel instead on the system mentioned above. Tested on x86_64-linux. gdb/ChangeLog: 2019-09-24 Tom de Vries <tdevries@suse.de> PR gdb/23815 * amd64-linux-nat.c (amd64_linux_nat_target::fetch_registers): Initialize xstateregs before ptrace PTRACE_GETREGSET call. gdb/testsuite/ChangeLog: 2019-09-24 Tom de Vries <tdevries@suse.de> PR gdb/24598 * gdb.arch/amd64-init-x87-values.exp: Add xfail.
2019-09-20Remove Cell Broadband Engine debugging supportUlrich Weigand4-554/+0
This patch implements removal of Cell/B.E. support, including - Support for the spu-*-* target - Support for native stand-alone SPU debugging - Support for integrated debugging of combined PPU/SPU applications - Remote debugging (gdbserver) support for all the above. The patch also removes the TARGET_OBJECT_SPU target object type, as this is available only on Cell/B.E. targets, including - Native Linux support - Core file support (including core file generation) - Remote target support, including removal of the qXfer:spu:read and qXfer:spu:write remote protocal packets and associated support in gdbserver. gdb/ChangeLog 2019-09-20 Ulrich Weigand <uweigand@de.ibm.com> * NEWS: Mention that Cell/B.E. debugging support was removed. * MAINTAINERS: Remove spu target. * config/djgpp/fnchange.lst: Remove entries for removed files. * Makefile.in (ALL_TARGET_OBS): Remove solib-spu.o, spu-multiarch.o, and spu-tdep.o. (HFILES_NO_SRCDIR): Remove solib-spu.h and spu-tdep.h. (ALLDEPFILES): Remove solib-spu.c, spu-linux-nat.c, spu-multiarch.c, and spu-tdep.c. * spu-linux-nat.c: Remove file. * spu-multiarch.c: Remove file. * spu-tdep.c: Remove file. * spu-tdep.h: Remove file. * solib-spu.c: Remove file. * solib-spu.h: Remove file. * configure.host (powerpc64*-*-linux*): Remove Cell/B.E. support. * configure.nat (spu-linux): Remove. * configure.tgt (powerpc*-*-linux*): Remove solib-spu.o and solib-multiarch.o from gdb_target_obs. (spu*-*-*): Remove. * arch/ppc-linux-common.h (struct ppc_linux_features): Remove "cell" feature flag. (ppc_linux_no_features): Update. * arch/ppc-linux-common.c (ppc_linux_match_description): Remove Cell/B.E. support. * arch/ppc-linux-tdesc.h (tdesc_powerpc_cell32l): Remove declaration. (tdesc_powerpc_cell64l): Likewise. * nat/ppc-linux.h (PPC_FEATURE_CELL): Remove. * ppc-linux-nat.c (ppc_linux_nat_target::read_description): Remove Cell/B.E. support. * ppc-linux-tdep.h: Do not include "solib-spu.h" or "spu-tdep.h". Do not include "features/rs6000/powerpc-cell32l.c" or "features/rs6000/powerpc-cell64l.c". (ppc_linux_spu_section): Remove. (ppc_linux_core_read_description): Remove Cell/B.E. support. (spe_context_objfile, spe_context_lm_addr, spe_context_offset, spe_context_cache_ptid, spe_context_cache_ptid): Remove. (ppc_linux_spe_context_lookup): Remove. (ppc_linux_spe_context_inferior_created): Remove. (ppc_linux_spe_context_solib_loaded): Remove. (ppc_linux_spe_context_solib_unloaded): Remove. (ppc_linux_spe_context): Remove. (struct ppu2spu_cache): Remove. (ppu2spu_prev_arch, ppu2spu_this_id, ppu2spu_prev_register): Remove. (struct ppu2spu_data): Remove. (ppu2spu_unwind_register, ppu2spu_sniffer, ppu2spu_dealloc_cache, ppu2spu_unwind): Remove. (ppc_linux_init_abi): Remove Cell/B.E. support. * rs6000-tdep.h (rs6000_gdbarch_init): Remove Cell/B.E. support. * features/Makefile (rs6000/powerpc-cell32l-expedite): Remove. (rs6000/powerpc-cell64l-expedite): Likewise (WHICH): Remove rs6000/powerpc-cell32l and rs6000/powerpc-cell64l. (XMLTOC): Remove rs6000/powerpc-cell32l.xml and rs6000/powerpc-cell64l.xml. * features/rs6000/powerpc-cell32l.xml: Remove. * features/rs6000/powerpc-cell64l.xml: Likewise. * features/rs6000/powerpc-cell32l.c: Remove generated file. * features/rs6000/powerpc-cell64l.c: Likewise. * regformats/rs6000/powerpc-cell32l.dat: Remove generated file. * regformats/rs6000/powerpc-cell64l.dat: Likewise. * regformats/reg-spu.dat: Remove. * target.h (enum target_object): Remove TARGET_OBJECT_SPU. * corelow.c (struct spuid_list): Remove. (add_to_spuid_list): Remove. (core_target::xfer_partial): Remove support for TARGET_OBJECT_SPU. * remote.c (PACKET_qXfer_spu_read, PACKET_qXfer_spu_write): Remove. (remote_protocol_features): Remove associated entries. (_initialize_remote): No longer initialize them. (remote_target::xfer_partial): Remove support for TARGET_OBJECT_SPU. * linux-nat.c (SPUFS_MAGIC): Remove. (linux_proc_xfer_spu): Remove. (spu_enumerate_spu_ids): Remove. (linux_nat_target::xfer_partial): Remove support for TARGET_OBJECT_SPU. * linux-tdep.c (-linux_spu_make_corefile_notes): Remove. (linux_make_corefile_notes): No longer call it. * regcache.c (cooked_read_test): Remove bfd_arch_spu special case. (cooked_write_test): Likewise. gdb/doc/ChangeLog 2019-09-20 Ulrich Weigand <uweigand@de.ibm.com> * doc/gdb.texinfo (Remote Configuration): Remove documentation for qXfer:spu:read and qXfer:spu:write. (General Query Packets): Likewise. (Cell Broadband Engine SPU architecture): Remove subsection. gdb/gdbserver/ChangeLog 2019-09-20 Ulrich Weigand <uweigand@de.ibm.com> * configure.srv (ipa_ppc_linux_regobj): Remove powerpc-cell32l-ipa.o and powerpc-cell64l-ipa.o. (powerpc*-*-linux*): Remove powerpc-cell32l.o and powerpc-cell64l.o from srv_regobj. Remove rs6000/powerpc-cell32l.xml and rs6000/powerpc-cell64l.xml from srv_xmlfiles. (spu*-*-*): Remove. * spu-low.c: Remove file. * linux-ppc-low.c (INSTR_SC, NR_spu_run): Remove. (parse_spufs_run): Remove. (ppc_get_pc): Remove Cell/B.E. support. (ppc_set_pc): Likewise. (ppc_breakpoint_at): Likewise. (ppc_arch_setup): Likewise. (ppc_get_ipa_tdesc_idx): Do not handle tdesc_powerpc_cell64l or tdesc_powerpc_cell32l. (initialize_low_arch): Do not call init_registers_powerpc_cell64l or init_registers_powerpc_cell32l. * linux-ppc-ipa.c (get_ipa_tdesc): Do not handle PPC_TDESC_CELL. (initialize_low_tracepoint): Do not call init_registers_powerpc_cell64l or init_registers_powerpc_cell32l. * linux-ppc-tdesc-init.h (PPC_TDESC_CELL): Mark as unused. (init_registers_powerpc_cell32l): Remove prototype. (init_registers_powerpc_cell64l): Likewise. * target.h (struct target_ops): Remove qxfer_spu member. * server.c (handle_qxfer_spu): Remove. (qxfer_packets): Remove entry for "spu". (handle_query): No longer support qXfer:spu:read or qXfer:spu:write. * linux-low.c (SPUFS_MAGIC): Remove. (spu_enumerate_spu_ids): Remove. (linux_qxfer_spu): Remove. (linux_target_ops): Remove qxfer_spu member. * lynx-low.c (lynx_target_ops): Remove qxfer_spu member. * nto-low.c (nto_target_ops): Remove qxfer_spu member. * win32-low.c (win32_target_ops): Remove qxfer_spu member. gdb/testsuite/ChangeLog 2019-09-20 Ulrich Weigand <uweigand@de.ibm.com> * gdb.arch/spu-info.exp: Remove file. * gdb.arch/spu-info.c: Remove file. * gdb.arch/spu-ls.exp: Remove file. * gdb.arch/spu-ls.c: Remove file. * gdb.asm/asm-source.exp: Remove support for spu*-*-*. * gdb.asm/spu.inc: Remove file. * gdb.base/dump.exp: Remove support for spu*-*-*. * gdb.base/stack-checking.exp: Likewise. * gdb.base/overlays.exp: Likewise. * gdb.base/ovlymgr.c: Likewise. * gdb.base/spu.ld: Remove file. * gdb.cp/bs15503.exp: Remove support for spu*-*-*. * gdb.cp/cpexprs.exp: Likewise. * gdb.cp/exception.exp: Likewise. * gdb.cp/gdb2495.exp: Likewise. * gdb.cp/mb-templates.exp: Likewise. * gdb.cp/pr9167.exp: Likewise. * gdb.cp/userdef.exp: Likewise. * gdb.xml/tdesc-regs.exp: Remove support for spu*-*-*. * gdb.cell: Remove directory. * lib/cell.exp: Remove file.
2019-08-14AArch64: Allow additional sizes in prologueAlan Hayward2-0/+119
When saving registers to the stack at the start of a function, not all state needs to be saved. For example, only the first 64bits of float registers need saving. However, a program may choose to store extra state if it wishes, there is nothing preventing it doing so. The aarch64_analyze_prologue will error if it detects extra state being stored. Relex this restriction. Tested via aarch64-prologue test. gdb/ChangeLog: * aarch64-tdep.c (aarch64_analyze_prologue): Allow any valid register sizes. gdb/testsuite/ChangeLog: * gdb.arch/aarch64-prologue.c: New test. * gdb.arch/aarch64-prologue.exp: New file.
2019-07-26[gdb/testsuite] Fix unterminated string in i386-pkru.expTom de Vries1-1/+1
I ran into this error: ... ERROR: tcl error sourcing gdb/testsuite/gdb.arch/i386-pkru.exp. ERROR: missing " while executing "untested "" invoked from within "if { [prepare_for_testing "failed to prepare" ${testfile} ${srcfile} \ [list debug additional_flags=${comp_flags}]] } { untested "failed to c..." (file "gdb/testsuite/gdb.arch/i386-pkru.exp" line 25) invoked from within ... caused by: ... untested "failed to compile x86 PKEYS test. ... Fix the unterminated string. Tested on x86_64-linux. gdb/testsuite/ChangeLog: 2019-07-26 Tom de Vries <tdevries@suse.de> * gdb.arch/i386-pkru.exp: Fix unterminated string.
2019-07-23[gdb][Arm]: gdb cannot step across CMSE secure entry function code.Srinath Parvathaneni2-0/+100
GDB is not able to execute "step" command on function calls of Armv8-M cmse secure entry functions. Everytime GNU linker come across definition of any cmse secure entry function in object file(s), it creates two new instructions secure gateway (sg) and original branch destination (b.w), place those two instructions in ".gnu.sgstubs" section of executable. Any function calls to these cmse secure entry functions is re-directed through secure gateway (sg) present in ".gnu.sgstubs" section. Example: Following is a function call to cmse secure entry function "foo": ... bl xxxx <foo> --->(a) ... <foo> xxxx: push {r7, lr} GNU linker on finding out "foo" is a cmse secure entry function, created sg and b.w instructions and place them in ".gnu.sgstubs" section (marked by c). The "bl" instruction (marked by a) which is a call to cmse secure entry function is modified by GNU linker (as marked by b) and call flow is re-directly through secure gateway (sg) in ".gnu.sgstubs" section. ... bl yyyy <foo> ---> (b) ... section .gnu.sgstubs: ---> (c) yyyy <foo> yyyy: sg // secure gateway b.w xxxx <__acle_se_foo> // original_branch_dest ... 0000xxxx <__acle_se_foo> xxxx: push {r7, lr} ---> (d) On invoking GDB, when the control is at "b" and we pass "step" command, the pc returns "yyyy" (sg address) which is a trampoline and which does not exist in source code. So GDB jumps to next line without jumping to "__acle_se_foo" (marked by d). The above details are published on the Arm website [1], please refer to section 5.4 (Entry functions) and section 3.4.4 (C level development flow of secure code). [1] https://developer.arm.com/architectures/cpu-architecture/m-profile/docs/ecm0359818/latest/armv8-m-security-extensions-requirements-on-development-tools-engineering-specification This patch fixes above problem by returning target pc "xxxx" to GDB on executing "step" command at "b", so that the control jumps to "__acle_se_foo" (marked by d). gdb/ChangeLog: * arm-tdep.c (arm_skip_cmse_entry): New function. (arm_is_sgstubs_section): New function. (arm_skip_stub): Add call to arm_skip_cmse_entry function. gdb/testsuite/ChangeLog: * gdb.arch/arm-cmse-sgstubs.c: New test. * gdb.arch/arm-cmse-sgstubs.exp: New file.
2019-07-19gdb/riscv: Write 4-byte nop to dummy code region before inferior callsAndrew Burgess2-0/+85
When making inferior function calls GDB sets up a dummy code region on the stack, and places a breakpoint within that region. If the random stack contents appear to be a compressed instruction then GDB will place a compressed breakpoint, which can cause problems if the target doesn't support compressed instructions. This commit prevents this issue by writing a 4-byte nop instruction to the dummy region at the time the region is allocated. With this nop instruction in place, when we come to insert the breakpoint then an uncompressed breakpoint will be used. This is similar to other targets, for example mips. gdb/ChangeLog: * riscv-tdep.c (riscv_push_dummy_code): Write a 4-byte nop instruction to the dummy code region. gdb/testsuite/ChangeLog: * gdb.arch/riscv-bp-infcall.c: New file. * gdb.arch/riscv-bp-infcall.exp: New file.
2019-07-09gdb: Don't skip prologue for explicit line breakpoints in assemblerAndrew Burgess2-0/+70
It was observed that in some cases, placing a breakpoint in an assembler file using filename:line-number syntax would result in the breakpoint being placed at a different line within the file. For example, consider this x86-64 assembler: test: push %rbp /* Break here. */ mov %rsp, %rbp nop /* Stops here. */ The user places the breakpoint using file:line notation targeting the line marked 'Break here', GDB actually stops at the line marked 'Stops here'. The reason is that the label 'test' is identified as the likely start of a function, and the call to symtab.c:skip_prologue_sal causes GDB to skip forward over the instructions that GDB believes to be part of the prologue. I believe however, that when debugging assembler code, where the user has instruction-by-instruction visibility, if they ask for a specific line, GDB should (as far as possible) stop on that line, and not perform any prologue skipping. I don't believe that the behaviour of higher level languages should change, in these cases skipping the prologue seems like the correct thing to do. In order to implement this change I needed to extend our current tracking of when the user has requested an explicit line number. We already tracked this in some cases, but not in others (see the changes in linespec.c). However, once I did this I started to see some additional failures (in tests gdb.base/break-include.exp gdb.base/ending-run.exp gdb.mi/mi-break.exp gdb.mi/mi-reverse.exp gdb.mi/mi-simplerun.exp) where we currently expected a breakpoint placed at one file and line number to be updated to reference a different line number, this was fixed by removing some code in symtab.c:skip_prologue_sal. My concern here is that removing this check didn't cause anything else to fail. I have a new test that covers my original case, this is written for x86-64 as most folk have access to such a target, however, any architecture that has a prologue scanner can be impacted by this change. gdb/ChangeLog: * linespec.c (decode_digits_list_mode): Set explicit_line to a bool value. (decode_digits_ordinary): Set explicit_line field in sal. * symtab.c (skip_prologue_sal): Don't skip prologue for a symtab_and_line that was set on an explicit line number in assembler code. Do always update the recorded symtab and line if we do skip the prologue. gdb/testsuite/ChangeLog: * gdb.arch/amd64-break-on-asm-line.S: New file. * gdb.arch/amd64-break-on-asm-line.exp: New file.
2019-06-05gdb/testsuite: Improve comments in recently added testAndrew Burgess2-2/+2
Remove the use of 'I' within some comments in a recently added test. gdb/testsuite/ChangeLog: * gdb.arch/riscv-unwind-long-insn-6.s: Remove use of 'I' in comment. * gdb.arch/riscv-unwind-long-insn-8.s: Likewise.
2019-06-05gdb/riscv: Don't error when decoding a 6 or 8 byte instructionAndrew Burgess4-0/+176
If the RISC-V prologue scanner finds a 6 or 8 byte instruction we currently throw an internal error, which is not great for the user. A mechanism already exists in the prologue scanner to leave instructions marked as unknown so that we can stop the prologue scan without raising an error, this is used for all 2 and 4 byte instructions that are not part of the small set the prologue scanner actually understands. This commit changes GDB so that all 6 and 8 byte instructions are marked as unknown, rather than causing an error. gdb/ChangeLog: * riscv-tdep.c (riscv_insn::decode): Gracefully ignore instructions of lengths 6 or 8 bytes. gdb/testsuite/ChangeLog: * gdb.arch/riscv-unwind-long-insn-6.s: New file. * gdb.arch/riscv-unwind-long-insn-8.s: New file. * gdb.arch/riscv-unwind-long-insn.c: New file. * gdb.arch/riscv-unwind-long-insn.exp: New file.
2019-05-22AArch64: Treat pauth ops as nops on non-pauth systemsAlan Hayward2-0/+79
Running an address signed binary through GDB on a non pauth system gives the following error: Call Frame Instruction op 45 in vendor extension space is not handled on this architecture. Instead GDB should ignore the op, treating it as a nop. Add test case for pauth binaries, regardless of whether the target supports it. gdb/ChangeLog: * aarch64-tdep.c (aarch64_execute_dwarf_cfa_vendor_op): Treat DW_CFA_AARCH64_negate_ra_state as nop on non pauth targets. gdb/testsuite/ChangeLog: * gdb.arch/aarch64-pauth.c: New test. * gdb.arch/aarch64-pauth.exp: New file.
2019-05-21[gdb/testsuite] Require c++11 where necessaryTom de Vries1-1/+1
When building gdb on ubuntu 16.04 with gcc 5.4.0, and running the gdb testsuite we run into failures due test-cases requiring at least c++1. Fix this by adding -std=c++11 to those test-cases. Tested on x86_64-linux. gdb/testsuite/ChangeLog: 2019-05-21 Tom de Vries <tdevries@suse.de> * gdb.arch/amd64-eval.exp: Require c++11. * gdb.base/max-depth.exp: Same. * gdb.compile/compile-cplus-array-decay.exp: Same. * gdb.cp/meth-typedefs.exp: Same. * gdb.cp/subtypes.exp: Same. * gdb.cp/temargs.exp: Same.
2019-05-09[gdb/testsuite] Fix gdb.arch/amd64-tailcall-self.STom de Vries1-12/+12
The test-case gdb.arch/amd64-tailcall-self.exp fails here: ... if ![runto b] { return -1 } ... like: ... (gdb) file build/gdb/testsuite/outputs/gdb.arch/amd64-tailcall-self/\ amd64-tailcall-self Reading symbols from build/gdb/testsuite/outputs/gdb.arch/\ amd64-tailcall-self/amd64-tailcall-self... Dwarf Error: Cannot find DIE at 0x1f5 referenced from DIE at 0x107 [in \ module build/gdb/testsuite/outputs/gdb.arch/amd64-tailcall-self/\ amd64-tailcall-self] ... The problem is that in amd64-tailcall-self.S, CU-relative references are assigned .debug_info section relative values. [ This is similar to the problem fixed by "Fix gdb.arch/amd64-entry-value-paramref.S". ] Fix this by assigning CU-relative references instead. Tested on x86_64-linux. gdb/testsuite/ChangeLog: 2019-05-09 Tom de Vries <tdevries@suse.de> * gdb.arch/amd64-tailcall-self.S: Make DW_FORM_ref4 references CU-relative.
2019-05-09[gdb/testsuite] Fix gdb.arch/amd64-entry-value-paramref.STom de Vries1-13/+13
The file gdb.arch/amd64-entry-value-paramref.S contains a DIE for function bar: ... DIE29: .uleb128 0x2 # (DIE (0x29) DW_TAG_subprogram) .ascii "bar\0" # DW_AT_name .byte 0x1 # DW_AT_decl_file (gdb.arch/amd64-entry-value-paramref.cc) .byte 0x15 # DW_AT_decl_line .long DIE45 # DW_AT_type .byte 0x1 # DW_AT_inline ... which refers to DIE45: ... DIE45: .uleb128 0x4 # (DIE (0x45) DW_TAG_base_type) .byte 0x4 # DW_AT_byte_size .byte 0x5 # DW_AT_encoding .ascii "int\0" # DW_AT_name ... using a form DW_FORM_ref4: ... .uleb128 0x2 # (abbrev code) .uleb128 0x2e # (TAG: DW_TAG_subprogram) .byte 0x1 # DW_children_yes ... .uleb128 0x49 # (DW_AT_type) .uleb128 0x13 # (DW_FORM_ref4) ... However, the DW_FORM_ref4 is a CU-relative reference, while using a label for the value will result in a section-relative value. So, if linked in object files contain dwarf info and are placed in the .debug_info section before the compilation units generated from amd64-entry-value-paramref.S, then the referenced type is at 0x108: ... <1><108>: Abbrev Number: 4 (DW_TAG_base_type) <109> DW_AT_byte_size : 4 <10a> DW_AT_encoding : 5 (signed) <10b> DW_AT_name : int ... but the reference will point to a non-existing DIE at 0x1cf: ... <1><f0>: Abbrev Number: 2 (DW_TAG_subprogram) <f1> DW_AT_name : bar <f5> DW_AT_decl_file : 1 <f6> DW_AT_decl_line : 21 <f7> DW_AT_type : <0x1cf> <fb> DW_AT_inline : 1 (inlined) ... which happens to cause a GDB internal error described in PR23270 - "GDB internal error: dwarf2read.c:18656: internal-error: could not find partial DIE 0x1b7 in cache". Fix the invalid DWARF by making the reference value CU-relative: ... - .long DIE45 # DW_AT_type + .long DIE45 - .Ldebug_info0 # DW_AT_type ... Tested on x86_64-linux. gdb/testsuite/ChangeLog: 2019-05-09 Tom de Vries <tdevries@suse.de> * gdb.arch/amd64-entry-value-paramref.S: Make DW_FORM_ref4 references CU-relative.
2019-04-24Fix passing of struct with bitfields on x86-64Tom Tromey2-0/+20
Commit 4aa866af ("Fix AMD64 return value ABI in expression evaluation") introduced a regression when calling a function with a structure that contains bitfields. Because the caller of amd64_has_unaligned_fields handles bitfields already, it seemed to me that the simplest fix was to ignore bitfields here. gdb/ChangeLog 2019-04-24 Tom Tromey <tromey@adacore.com> * amd64-tdep.c (amd64_has_unaligned_fields): Ignore bitfields. gdb/testsuite/ChangeLog 2019-04-24 Tom Tromey <tromey@adacore.com> * gdb.arch/amd64-eval.exp: Test bitfield return. * gdb.arch/amd64-eval.cc (struct Bitfields): New. (class Foo) <return_bitfields>: New method. (main): Call it.
2019-04-15Fix AMD64 return value ABI in expression evaluationLeszek Swirski2-0/+163
The AMD64 System V ABI specifies that when a function has a return type classified as MEMORY, the caller provides space for the value and passes the address to this space as the first argument to the function (before even the "this" pointer). The classification of MEMORY is applied to struct that are sufficiently large, or ones with unaligned fields. The expression evaluator uses call_function_by_hand to call functions, and the hand-built frame has to push arguments in a way that matches the ABI of the called function. call_function_by_hand supports ABI-based struct returns, based on the value of gdbarch_return_value, however on AMD64 the implementation of the classifier incorrectly assumed that all non-POD types (implemented as "all types with a base class") should be classified as MEMORY and use the struct return. This ABI mismatch resulted in issues when calling a function that returns a class of size <16 bytes which has a base class, including issues such as the "this" pointer being incorrect (as it was passed as the second argument rather than the first). This is now fixed by checking for field alignment rather than POD-ness, and a testsuite is added to test expression evaluation for AMD64. gdb/ChangeLog: * amd64-tdep.c (amd64_classify_aggregate): Use cp_pass_by_reference rather than a hand-rolled POD check when checking for forced MEMORY classification. gdb/testsuite/ChangeLog: * gdb.arch/amd64-eval.cc: New file. * gdb.arch/amd64-eval.exp: New file.
2019-02-14Updating test caseWeimin Pan2-13/+9
gdb.arch/aarch64-dbreg-contents.exp: * Replaced "run" with "runto_main + continue". * Replaced "gdb_compile + clean_restart" with "prepare_for_testing". * Added comment for case "exited with code 01". gdb.arch/aarch64-dbreg-contents.c: * Removed SET_WATCHPOINT marco. * Removed redundent cleanup (). * Cleaned up comment.
2019-02-13Adding a test caseWeimin Pan2-0/+179
gdb/testsuite/ChangeLog 2019-02-12 Weimin Pan <weimin.pan@oracle.com> PR breakpoints/21870 * gdb.arch/aarch64-dbreg-contents.exp: New file. * gdb.arch/aarch64-dbreg-contents.c: New file.
2019-01-14[PowerPC] Aliases for vector registersPedro Franco de Carvalho4-2/+128
This patch defines pseudo-registers "v0" through "v31" as aliases that map to the corresponding raw "vr0" through "vr31" vector registers for Power. The motivation behind this is that although GDB defines these registers as "vrX", the disassembler prints them as "vX", e.g. as the operands in instructions such as "vaddubm v2,v1,v1". This can be confusing to users trying to print out the values of the operands while inspecting the disassembled code. The new aliases are made not to belong to any register group, to avoid duplicated values in "info register vector" and "info register all". The arch-specific rs6000_pseudo_register_reggroup_p function had previously been removed since the other pseudo-registers could have their groups inferred by their type. It restored with this patch to handle the aliases. Membership for the other pseudo-registers is still determined using the default function. A new tests checks that GDB prints the expected values of vector registers after they are filled by the inferior, by using both the raw names and the aliases. Two other existing tests are modified to also test the aliases. gdb/ChangeLog: 2019-01-14 Pedro Franco de Carvalho <pedromfc@linux.ibm.com> * ppc-tdep.h (struct gdbarch_tdep) <ppc_v0_alias_regnum>: New field. * rs6000-tdep.c: Include reggroups.h. (IS_V_ALIAS_PSEUDOREG): Define. (rs6000_register_name): Return names for the "vX" aliases. (rs6000_pseudo_register_type): Return type for the "vX" aliases. (rs6000_pseudo_register_reggroup_p): Restore. Handle "vX" aliases. Call default_register_reggroup_p for all other pseudo-registers. (v_alias_pseudo_register_read, v_alias_pseudo_register_write): New functions. (rs6000_pseudo_register_read, rs6000_pseudo_register_write): Handle "vX" aliases. (v_alias_pseudo_register_collect): New function. (rs6000_ax_pseudo_register_collect): Handle "vX" aliases. (rs6000_gdbarch_init): Initialize "vX" aliases as pseudo-registers. Restore registration of rs6000_pseudo_register_reggroup_p with set_tdesc_pseudo_register_reggroup_p. gdb/testsuite/ChangeLog: 2019-01-14 Pedro Franco de Carvalho <pedromfc@linux.ibm.com> * gdb.arch/vsx-regs.exp: Add tests that use the vector register aliases. * gdb.arch/altivec-regs.exp: Likewise. Fix indentation of two tests. * gdb.arch/powerpc-vector-regs.c: New file. * gdb.arch/powerpc-vector-regs.exp: New file. gdb/doc/ChangeLog: 2019-01-14 Pedro Franco de Carvalho <pedromfc@linux.ibm.com> * gdb.texinfo (PowerPC Features): Document the alias pseudo-registers for the org.gnu.gdb.power.altivec feature.
2019-01-14[PowerPC] Fix "info vector" test in gdb.arch/altivec-regs.expPedro Franco de Carvalho1-38/+5
This patch fixes one of the tests in gdb.arch/altivec-regs.exp that was passing an incorrect list to gdb_expect_list, which always matched. gdb/testsuite/ChangeLog: 2019-01-14 Pedro Franco de Carvalho <pedromfc@linux.ibm.com> * gdb.arch/altivec-regs.exp: Fix the list passed to gdb_expect_list when testing "info vector".
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