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2021-05-20Fix overflow detection in the Z80 assembler.Sergey Belyashov5-200/+227
* config/tc-z80.c (emit_data_val): Warn on constant overflow. (signed_overflow): New function. (unsigned_overflow): New function. (is_overflow): Use new functions. (md_apply_fix): Use signed_overflow. * testsuite/gas/z80/ez80_adl_suf.d: Fix test. * testsuite/gas/z80/ez80_isuf.s: Likewise. * testsuite/gas/z80/ez80_z80_suf.d: Likewise.
2021-05-20PR27888, fix link of gas with zlib by libtool 2.4.6Nicolas Boulenguez3-2/+11
PR 27888 * Makefile.am (ZLIB): Define. (as_new_LDADD): Add it. * Makefile.in: Regenerate.
2021-05-19Fix offset for ia64 PCREL60B relocation on HP-UXJohn David Anglin1-1/+10
gas/ChangeLog: 2021-05-19 John Buddery <jvb@cyberscience.com> PR 25599 * config/tc-ia64.c (emit_one_bundle): Increment fixup offset by one for PCREL60B relocation on HP-UX.
2021-05-17arm: Fix bugs with MVE vmov from two GPRs to vector lanesAlex Coplan5-3/+340
The initial problem I wanted to fix here is that GAS was rejecting MVE instructions such as: vmov q3[2], q3[0], r2, r2 with: Error: General purpose registers may not be the same -- `vmov q3[2],q3[0],r2,r2' which is incorrect; such instructions are valid. Note that for moves in the other direction, e.g.: vmov r2, r2, q3[2], q3[0] GAS is correct in rejecting this as it does not make sense to move both lanes into the same register (the Arm ARM says this is CONSTRAINED UNPREDICTABLE). After fixing this issue, I added assembly/disassembly tests for these vmovs. This revealed several disassembly issues, including incorrectly marking the moves into vector lanes as UNPREDICTABLE, and disassembling many of the vmovs as vector loads. These are now fixed. gas/ChangeLog: * config/tc-arm.c (do_mve_mov): Only reject vmov if we're moving into the same GPR twice. * testsuite/gas/arm/mve-vmov-bad-2.l: Tweak error message. * testsuite/gas/arm/mve-vmov-3.d: New test. * testsuite/gas/arm/mve-vmov-3.s: New test. opcodes/ChangeLog: * arm-dis.c (mve_opcodes): Fix disassembly of MVE_VMOV2_GP_TO_VEC_LANE when idx == 1. (is_mve_encoding_conflict): MVE vector loads should not match when P = W = 0. (is_mve_unpredictable): It's not unpredictable to use the same source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
2021-05-12SAFE_BYTE_GET64Alan Modra3-3/+8
Functions dealing with lack of a 64-bit integer type can disappear now that we require C99. Printing using dwarf_vmatoa is better too. binutils/ * dwarf.c (dwarf_vmatoa64, SAFE_BYTE_GET64, add64): Delete. (skip_attr_bytes): Replace use of SAFE_BYTE_GET64 with SAFE_BYTE_GET_AND_INC. (read_and_display_attr_value): Likewise. Print using dwarf_vmatoa. (process_debug_info, process_cu_tu_index): Likewise. * elfcomm.c (byte_put, byte_put_little_endian, byte_put_big_endian), (byte_get, byte_get_little_endian, byte_get_big_endian), (byte_get_signed): Make size param unsigned. Remove code dealing with 4-byte elf_vma. (byte_get_64): Delete. * elfcomm.h (byte_put, byte_put_little_endian, byte_put_big_endian), (byte_get, byte_get_little_endian, byte_get_big_endian), (byte_get_signed): Update prototypes. (byte_get_64): Delete. gas/ * testsuite/gas/elf/dwarf-5-file0.d: Update. * testsuite/gas/i386/dwarf5-line-1.d: Update.
2021-05-11Report illegal Z80 load instructions.Sergey Belyashov5-0/+95
PR 27823 * config/tc-z80.c (emit_ld_r_m): Report an illegal load instruction. * testsuite/gas/z80/ill_ops.s: New test source file. * testsuite/gas/z80/ill_ops.d: New test driver. * testsuite/gas/z80/ill_ops.l: New test error output.
2021-05-10Add support for 8-bit and 24-bit shifts in the z80 assembler.Sergey Belyashov4-2/+35
PR 27415 * config/tc-z80.c (emit_data_val): Add support for 8-bit and 24-bit shifts. * testsuite/gas/z80/z80_reloc.a: Update tests. * testsuite/gas/z80/z80_reloc.d: Update expected disassembly.
2021-05-08support generating multi-html pages in parallelMike Frysinger3-2/+17
Use the pattern from other projects where we generate the html pages in a dir named the same as the project. So now we have: gas/doc/gas.html - single html page gas/doc/gas/ - multiple html pages This works for projects that have a doc/ subdir already, but gprof & ld require a little tweaking since they generate their docs in their respective toplevels.
2021-05-08generate single html manual page by defaultMike Frysinger3-2/+9
This better matches other GNU projects like autoconf/automake where the html manual is the single page form. We'll support the multi-page form in a follow up change.
2021-05-07Add a generic .bss directive for ELF based targets.Nick Clifton4-14/+65
PR 3136 * config/obj-elf.c (elf_pseudo_table): Add entry for .bss. (obj_elf_bss): New function. Change to the .bss section. Support an optional subsection number. (obj_elf_change_section): Call obj_elf_section_change_hook. (obj_elf_section): Likewise. (obj_elf_data): Likewise. (obj_elf_text): Likewise. (obj_elf_struct): Likewise. (obj_elf_subsection): Likewise. (obj_elf_previous): Likewise. * config/obj-elf.h (obj_elf_bss): Prototype. * doc/as.texi (Bss): New node.
2021-05-07Fix .dwsect generation for XCOFF. Handle .function generated with DWARF on ↵Cl?ment Chigot11-5/+217
XCOFF. gas * config/tc-ppc.c (ppc_function): Update comment for fifth argument. (ppc_frob_symbol): Remove ppc_last_function check. Make sure coff_last_function is reset. Correctly set fsize when not provided in .function. * testsuite/gas/ppc/aix.exp: New tests. * testsuite/gas/ppc/xcoff-function-1-32.d: New test. * testsuite/gas/ppc/xcoff-function-1-64.d: New test. * testsuite/gas/ppc/xcoff-function-1.s: New test. bfd * coff-rs6000.c (xcoff_dwsect_names): Add new DWARF sections. * coffgen.c (coff_pointerize_aux): Handle C_DWARF. (coff_print_symbol): Likewise. * libxcoff.h (XCOFF_DWSECT_NBR_NAMES): Update. gas * config/obj-coff.c (coff_frob_symbol): Don't skip C_DWARF. (coff_adjust_section_syms): Use corrext auxent for C_DWARF. (coff_frob_section): Likewise. * config/obj-coff.h (SA_GET_SECT_SCNLEN, SA_GET_SECT_NRELOC, SA_SET_SECT_SCNLEN, SA_SET_SECT_NRELOC) New defines. (SET_SECTION_RELOCS): Adjust for C_DWARF. * config/tc-ppc.c (ppc_frob_symbol): Don't skip C_DWARF. (ppc_adjust_symtab): Reorder C_DWARF symbols. * testsuite/gas/ppc/aix.exp: New tests. * testsuite/gas/ppc/xcoff-dwsect-2-32.d: New test. * testsuite/gas/ppc/xcoff-dwsect-2-64.d: New test. * testsuite/gas/ppc/xcoff-dwsect-2.s: New test. include * coff/internal.h (C_DWARF): New define. * coff/xcoff.h (SSUBTYP_DWLOC, SSUBTYP_DWFRAME, SSUBTYP_DWMAC): New defines.
2021-05-07x86-64/ELF: clear src_mask for all reloc typesJan Beulich4-0/+33
x86-64 uses rela relocations. The comment next to the field's declaration says "Non-zero values for ELF USE_RELA targets should be viewed with suspicion ..." And indeed the fields being non-zero causes section contents to be accumulated into the final relocated values in addition to the relocations' addends, which is contrary to the ELF spec.
2021-05-07x86: don't mix disp and imm processingJan Beulich2-1/+6
Surely disp processing should access the disp operand, not an imm one. This is not an active issue only because imms and disps are, at the moment, overlapping fields of the same union.
2021-05-07x86: move register check in immediate operand parsingJan Beulich2-7/+13
i386_finalize_immediate() is used for both AT&T and Intel immediate operand handling. Move an AT&T-only check to i386_immediate(), which at the same time allows it to cover other cases as well, giving an overall better / more consistent diagnostic.
2021-05-07x86: minor improvements to optimize_imm()Jan Beulich2-8/+11
- Drop a pointless & where just before it was checked that the respective bits are clear already anyway. - Avoid a not really necessary operand_type_set() and a redundant operand_type_or() / operand_type_and() pair.
2021-05-06or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha()Stafford Horne3-1/+14
The gotha() relocation mnemonic will be outputted by OpenRISC GCC when using the -mcmodel=large option. This relocation is used along with got() to generate 32-bit GOT offsets. This increases the previous GOT offset limit from the previous 16-bit (64K) limit. This is needed on large binaries where the GOT grows larger than 64k. bfd/ChangeLog: PR 21464 * bfd-in2.h: Add BFD_RELOC_OR1K_GOT_AHI16 relocation. * elf32-or1k.c (or1k_elf_howto_table, or1k_reloc_map): Likewise. (or1k_final_link_relocate, or1k_elf_relocate_section, or1k_elf_check_relocs): Likewise. * libbfd.h (bfd_reloc_code_real_names): Likewise. * reloc.c: Likewise. cpu/ChangeLog: PR 21464 * or1k.opc (or1k_imm16_relocs, parse_reloc): Define parse logic for gotha() relocation. include/ChangeLog: PR 21464 * elf/or1k.h (elf_or1k_reloc_type): Define R_OR1K_GOT_AHI16 number. opcodes/ChangeLog: PR 21464 * or1k-asm.c: Regenerate. gas/ChangeLog: PR 21464 * testsuite/gas/or1k/reloc-1.s: Add test for new relocation. * testsuite/gas/or1k/reloc-1.d: Add test result for new relocation. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> fixup reloc, add tests
2021-05-03RISC-V: PR27764, Add tests for A extensionJim Wilson1-0/+8
ChangeLog entry for last patch.
2021-05-03RISC-V: PR27764, Add tests for A extensionChristoph Muellner4-0/+550
gas/ PR 27764 * testsuite/gas/riscv/a-ext-64.d: New testcase. * testsuite/gas/riscv/a-ext-64.s: Likewise. * testsuite/gas/riscv/a-ext.d: Likewise. * testsuite/gas/riscv/a-ext.s: Likewise. Signed-off-by: Christoph Muellner <cmuellner@gcc.gnu.org>
2021-05-03x86: allow @secrel32 also in data definitionsJan Beulich4-7/+22
Now that lex_got() is uniform for all targets using it, permit COFF targets to also use @secrel32 with, in particular, .long. This is more natural than the custom .secrel32 directive, and also allows more flexibility (the "+six" form of the two added test lines doesn't work with a .secrel32 equivalent, in that it silently produces an unintended relocation type). As an extra benefit this also makes sure that data definitions in Intel syntax mode would get treated like they do for e.g. ELF targets.
2021-05-03x86: use UNIX EOL in secrel testcaseJan Beulich3-125/+130
For some reason these were using Windows EOL.
2021-05-03x86: fold both instances of lex_got()Jan Beulich2-106/+14
I see no reason at all for us to carry two copies of almost identical code. The differences, apart from the table entries, are benign. And the #ifdef-ary doesn't really get any worse.
2021-05-03testsuite: Don't start directives in first columnAlan Modra3-14/+20
Fixes fails on hppa64-hp-hpux11.23 * testsuite/gas/elf/section25.s: Don't start directives in first column. * testsuite/gas/elf/section26.s: Likewise.
2021-04-29x86-64: adjust recently added testsJan Beulich6-15/+26
Five of them fail for Cygwin and MingW. Adjust four and move one to the ELF-only section.
2021-04-29x86: relax when/how @size can be usedJan Beulich7-9/+138
Allow a few more expression forms when the entire expression can be resolved at assembly time. For this, i386_validate_fix() needs to arrange for all processing of the relocation to be deferred to tc_gen_reloc().
2021-04-29x86: allow @size to also (sensibly) apply to sectionsJan Beulich5-7/+36
So far this (counter-intuitively) produced the size as recorded in the (section) symbol. Obtain the section's size instead for section symbols. (I wonder whether STT_SECTION symbols couldn't properly hold the section's size in their st_size field, which in turn would likely mean the internal symbol would also have its size properly updated.) Note that this is not the same as the .sizeof.() pseudo-operator: @size yields the local file's contribution to a section, while .sizeof.() gets resolved by the linker to produce the final full section's size. As to the 3rd each of the expected output lines in the changed testcase: I can't find justification for zzz to come after yyy despite them being defined in the opposite order in source. Therefore I think it's better to permit both possible outcomes.
2021-04-28x86: honor signedness of PC-relative relocationsJan Beulich11-18/+211
PR gas/27763 While the comment in output_jump() was basically correct prior to the introduction of 64-bit mode, both that and the not-JMP-like behavior of XBEGIN require adjustments: Branches with 32-bit displacement do not wrap at 4G in 64-bit mode, and XBEGIN with 16-bit operand size doesn't wrap at 64k. Similarly %rip-relative addressing doesn't wrap at 4G. The new testcase points out that for PE/COFF object_64bit didn't get set so far, preventing in particular the check at the end of md_convert_frag() to take effect. For Mach-O the new testcase fails (bogusly), in that only the first two of the expected errors get raised. Since for Mach-O many testcases already fail, and since an x86_64-darwin target can't even be configured for, I didn't think I need to bother. Note that there are further issues in this area, in particular for branches with operand size overrides. Such branches, which truncate %rip / %eip, can't be correctly expressed with ordinary PC-relative relocations. It's not really clear what to do with them - perhaps the best we can do is to carry through all associated relocations, leaving it to the linker (or even loader) to decide (once the final address layout is known). Same perhaps goes for relocations associated with 32-bit addressing in 64-bit mode.
2021-04-27x86: Add () to silence GCC 5H.J. Lu2-1/+7
Add () to !i.prefix[ADDR_PREFIX] to silence GCC 5: gas/config/tc-i386.c:4152:31: error: logical not is only applied to the left hand side of comparison [-Werror=logical-not-parentheses] && !i.prefix[ADDR_PREFIX] != (flag_code == CODE_32BIT)) ^ * config/tc-i386.c (optimize_encoding): Add () to silence GCC 5.
2021-04-26x86: add IS_ELF to check whether to resolve @size relocJan Beulich2-1/+7
This may not be strictly needed, as BFD_RELOC_SIZE* shouldn't appear from elsewhere for non-ELF, but let's be on the safe side.
2021-04-26x86: limit 32-bit @size overflow checks to 64-bit objectsJan Beulich2-0/+6
For 32-bit objects the behavior should not be dependent upon the build being a BFD64 one.
2021-04-26x86: optimize LEAJan Beulich13-8/+569
Over the years I've seen a number of instances where people used lea (%reg1), %reg2 or lea symbol, %reg despite the same thing being expressable via MOV. Since additionally LEA often has restrictions towards the ports it can be issued to, while MOV typically gets dealt with simply by register renaming, transform to MOV when possible (without growing opcode size and without altering involved relocation types). Note that for Mach-O the new 64-bit testcases would fail (for BFD_RELOC_X86_64_32S not having a representation), and hence get skipped there.
2021-04-26x86-64: have value properly checked when resolving fixupJan Beulich5-1/+65
Constants not known at the time an individual insn gets assembled and going into a sign-extended field still shouldn't be silently truncated at the time the respective fixup gets resolved.
2021-04-23Fix type of .persistent.bss sectionEric Botcazou4-2/+17
The change implementing the .persistent family of sections broke the existing support for the .persistent.bss section in the compiler: int a __attribute__ ((section (".persistent.bss"))); t.s: Assembler messages: t.s:4: Warning: setting incorrect section type for .persistent.bss The compiler encodes it as @nobits but the assembler expects @progbits. The assembler is incorrect and should treat the section like the compiler. bfd/ * elf.c (special_sections_p): Add .persistent.bss. gas/ * testsuite/gas/elf/section25.d: Run it everywhere. * testsuite/gas/elf/section26.d: Likewise. * testsuite/gas/elf/section26.s: Add test for .persistent.bss.
2021-04-23Allow .seh_pushframe to take an optional [code] parameterJ?r?me Gardou2-1/+25
* config/obj-coff-seh.c (obj_coff_seh_pushframe): Allow an optional "code" argument.
2021-04-23x86-64: special case LEA when determining signedness of displacementJan Beulich2-8/+24
LEA behavior without a 64-bit destination is independent of address size - in particular LEA with 32-bit addressing and 64-bit destination is the same as LEA with 64-bit addressing and 32-bit destination. IOW checking merely i.prefix[ADDR_PREFIX] is insufficient. This also means wrong relocation types (R_X86_64_32S when R_X86_64_32 is needed) were used so far in such cases. Note that in one case in build_modrm_byte() the 64-bit check came too early altogether, and hence gets dropped in favor of the one included in the new helper. This is benign to non-64-bit code from all I can tell, but the failure to clear disp16 could have been a latent problem.
2021-04-23x86-64: defer 32-bit signed displacement checkJan Beulich2-19/+34
In preparation for extending the conditions here defer this check until operands have been parsed, as certain further attributes will need to be known for determinig applicability of this check to be correct to LEA.
2021-04-23x86: re-order optimize_disp()Jan Beulich2-16/+23
While I can't point out any specific case where things break, it looks wrong to have the consumer of a flag before its producer. Set .disp32 first, then do the possible conversion to signed 32-bit, and finally check whether the value fits in a signed long.
2021-04-23x86: don't truncate values in diagnostics and alikeJan Beulich2-4/+9
Truncating an expression's X_add_number to just "long" can result in confusing output (e.g. an apparently in-range number claimed to be out of range). Use the abstraction that bfd provides for this. Take the opportunity and also insert a missing "of".
2021-04-21Adjust readelf's output so that section symbols without a name as shown with ↵Nick Clifton34-133/+170
their section name. binutils* readelf.c (print_dynamic_symbol): Print the section name for section symbols without a name of their own. * testsuite/binutils-all/mips/global-local-symtab-sort-n64t.d: Adjust expected output to allow for named section symbols. * testsuite/binutils-all/mips/global-local-symtab-sort-o32t.d: Likewise. * testsuite/binutils-all/readelf.s-64: Likewise. * testsuite/binutils-all/readelf.ss-64-unused: Likewise. * testsuite/binutils-all/readelf.ss-tmips: Likewise. * testsuite/binutils-all/readelf.ss-unused: Likewise. ld * testsuite/ld-aarch64/variant_pcs-now.d: Adjust expected output to allow for named section symbols. * testsuite/ld-aarch64/variant_pcs-r.d: Likewise. * testsuite/ld-aarch64/variant_pcs-shared.d: Likewise. * testsuite/ld-alpha/tlsbin.rd: Likewise. * testsuite/ld-alpha/tlsbinr.rd: Likewise. * testsuite/ld-alpha/tlspic.rd: Likewise. * testsuite/ld-arm/rodata-merge-map.sym: Likewise. * testsuite/ld-arm/script-type.sym: Likewise. * testsuite/ld-cris/libdso-2.d: Likewise. * testsuite/ld-cris/pr16044.d: Likewise. * testsuite/ld-elf/sec64k.exp: Likewise. * testsuite/ld-ia64/tlsbin.rd: Likewise. * testsuite/ld-ia64/tlspic.rd: Likewise. * testsuite/ld-mips-elf/global-local-symtab-sort-n64t.d: Likewise. * testsuite/ld-mips-elf/global-local-symtab-sort-o32t.d: Likewise. * testsuite/ld-mmix/bspec1.d: Likewise. * testsuite/ld-mmix/bspec2.d: Likewise. * testsuite/ld-mmix/local1.d: Likewise. * testsuite/ld-mmix/local3.d: Likewise. * testsuite/ld-mmix/local5.d: Likewise. * testsuite/ld-mmix/local7.d: Likewise. * testsuite/ld-mmix/undef-3.d: Likewise. * testsuite/ld-powerpc/tlsso.r: Likewise. * testsuite/ld-powerpc/tlsso32.r: Likewise. * testsuite/ld-powerpc/tlstocso.r: Likewise. * testsuite/ld-s390/tlsbin.rd: Likewise. * testsuite/ld-s390/tlsbin_64.rd: Likewise. * testsuite/ld-s390/tlspic.rd: Likewise. * testsuite/ld-s390/tlspic_64.rd: Likewise. * testsuite/ld-sparc/gotop32.rd: Likewise. * testsuite/ld-sparc/gotop64.rd: Likewise. * testsuite/ld-sparc/tlssunbin32.rd: Likewise. * testsuite/ld-sparc/tlssunbin64.rd: Likewise. * testsuite/ld-sparc/tlssunnopic32.rd: Likewise. * testsuite/ld-sparc/tlssunnopic64.rd: Likewise. * testsuite/ld-sparc/tlssunpic32.rd: Likewise. * testsuite/ld-sparc/tlssunpic64.rd: Likewise. * testsuite/ld-tic6x/common.d: Likewise. * testsuite/ld-tic6x/shlib-1.rd: Likewise. * testsuite/ld-tic6x/shlib-1b.rd: Likewise. * testsuite/ld-tic6x/shlib-1r.rd: Likewise. * testsuite/ld-tic6x/shlib-1rb.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1b.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1r.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1rb.rd: Likewise. * testsuite/ld-tic6x/shlib-noindex.rd: Likewise. * testsuite/ld-tic6x/static-app-1.rd: Likewise. * testsuite/ld-tic6x/static-app-1b.rd: Likewise. * testsuite/ld-tic6x/static-app-1r.rd: Likewise. * testsuite/ld-tic6x/static-app-1rb.rd: Likewise. gas * testsuite/gas/aarch64/dwarf.d: Adjust expected output to allow for named section symbols. * testsuite/gas/arm/thumbver.d: Likewise. * testsuite/gas/bfin/loop_temps.d: Likewise. * testsuite/gas/elf/section2.e-arc: Likewise. * testsuite/gas/elf/section2.e-arm: Likewise. * testsuite/gas/elf/section2.e-csky: Likewise. * testsuite/gas/elf/section2.e-m32r: Likewise. * testsuite/gas/elf/section2.e-mips: Likewise. * testsuite/gas/elf/section2.e-msp430: Likewise. * testsuite/gas/elf/section2.e-riscv: Likewise. * testsuite/gas/elf/section2.e-rl78: Likewise. * testsuite/gas/elf/section2.e-rx: Likewise. * testsuite/gas/elf/section2.e-score: Likewise. * testsuite/gas/elf/section2.e-tic6x: Likewise. * testsuite/gas/elf/section2.e-unused: Likewise. * testsuite/gas/elf/section2.e-v850: Likewise. * testsuite/gas/elf/section2.e-xtensa: Likewise. * testsuite/gas/ia64/alias-ilp32.d: Likewise. * testsuite/gas/ia64/alias.d: Likewise. * testsuite/gas/ia64/global.d: Likewise. * testsuite/gas/microblaze/relax_size.elf: Likewise. * testsuite/gas/microblaze/relax_size2.elf: Likewise. * testsuite/gas/mips/global-local-symtab-sort-n64t.d: Likewise. * testsuite/gas/mips/global-local-symtab-sort-o32t.d: Likewise. * testsuite/gas/mmix/bspec-1.d: Likewise. * testsuite/gas/mmix/byte-1.d: Likewise. * testsuite/gas/mmix/comment-1.d: Likewise. * testsuite/gas/mmix/loc-1.d: Likewise. * testsuite/gas/mmix/loc-2.d: Likewise. * testsuite/gas/mmix/loc-3.d: Likewise. * testsuite/gas/mmix/loc-4.d: Likewise. * testsuite/gas/mmix/loc-5.d: Likewise. * testsuite/gas/tic6x/scomm-directive-4.d: Likewise.
2021-04-20Rework the R_NEG support on both gas and ld for the PowerPC AIX targets, in ↵Cl?ment Chigot3-28/+107
order to manage C++ exceptions built with GCC. bfd PR binutils/21700 * reloc.c (BFD_RELOC_PPC_NEG): New relocation. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * coff-rs6000.c (_bfd_xcoff_reloc_type_lookup): Add BFD_RELOC_PPC_NEG handler. (xcoff_reloc_type_neg): Correctly substract addend. * coff64-rs6000.c (xcoff64_howto_table): Add R_NEG_32 howto. (xcoff64_rtype2howto): Add handler for R_NEG_32. (xcoff64_reloc_type_lookup): Add BFD_RELOC_PPC_NEG handler. * xcofflink.c (xcoff_need_ldrel_p): Check output section for R_POS-like relocations. New argument added. (xcoff_mark): Adapt to new xcoff_need_ldrel_p argument. (xcoff_link_input_bfd): Likewise. gas * config/tc-ppc.c (ppc_get_csect_to_adjust): New function. (ppc_fix_adjustable): Manage fx_subsy part. (tc_gen_reloc): Create second relocation when both fx_addsy and fx_subsy are provided. * config/tc-ppc.h (RELOC_EXPANSION_POSSIBLE): New define. (MAX_RELOC_EXPANSION): Likewise. (TC_FORCE_RELOCATION_SUB_SAME): Likewise (UNDEFINED_DIFFERENCE_OK): Likewise * testsuite/gas/all/gas.exp: Skip difference between two undefined symbols test. ld * testsuite/ld-powerpc/aix52.exp: Add new test. * testsuite/ld-powerpc/aix-neg-reloc-32.d: New test. * testsuite/ld-powerpc/aix-neg-reloc-64.d: New test. * testsuite/ld-powerpc/aix-neg-reloc.ex: New test. * testsuite/ld-powerpc/aix-neg-reloc.s: New test.
2021-04-19Fix an assembler testuite failure when checking a toolchain configured with ↵Nick Clifton2-0/+7
--target=rs6000-aix3.3. * testsuite/gas/all/gas.exp: Add rs6000*-*-aix* to the list of targets which should skip the undefined symbols test.
2021-04-19aarch64: New instructions for maintenance of GPT entries cached in a TLBPrzemyslaw Wirkus4-0/+18
This patch adds support to four new system registers (RPAOS, RPALOS, PAALLOS, PAALL) in conjunction with TLBI instruction. This change is part of RME (Realm Management Extension). gas/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Update news. * testsuite/gas/aarch64/rme.d: Update test. * testsuite/gas/aarch64/rme.s: Update test. opcodes/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support for TLBI instruction.
2021-04-19aarch64: Add new data cache maintenance operationsPrzemyslaw Wirkus3-0/+11
This patch adds support to two new system registers (CIPAPA, CIGDPAPA) in conjunction with DC instruction. This change is part of RME (Realm Management Extension). gas/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * testsuite/gas/aarch64/rme.d: Update test. * testsuite/gas/aarch64/rme.s: Update test. opcodes/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for DC instruction.
2021-04-19gas: drop sprint_value()Jan Beulich7-30/+19
Its (documented) behavior is unhelpful in particular in 64-bit build environments: While printing large 32-bit numbers in decimal already isn't very meaningful to most people, this even more so goes for yet larger 64-bit numbers. bfd_sprintf_vma() still tries to limit the number of digits printed (without depending on a build system property), but uniformly produces hex output.
2021-04-16aarch64: Define RME system registersPrzemyslaw Wirkus6-0/+41
This patch introduces RME (Realm Management Extension) system registers. gas/ChangeLog: 2021-03-01 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * testsuite/gas/aarch64/rme-invalid.d: New test. * testsuite/gas/aarch64/rme-invalid.l: New test. * testsuite/gas/aarch64/rme-invalid.s: New test. * testsuite/gas/aarch64/rme.d: New test. * testsuite/gas/aarch64/rme.s: New test. opcodes/ChangeLog: 2021-03-01 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add RME system registers.
2021-04-16RISC-V: PR27436, make operand C> work the same as >.Nelson Chu8-3/+116
gas/ PR 27436 * config/tc-riscv.c (riscv_ip): make operand C> work the same as >. * testsuite/gas/riscv/shamt-32.d: New testcase. * testsuite/gas/riscv/shamt-32.l: Likewise. * testsuite/gas/riscv/shamt-32.s: Likewise. * testsuite/gas/riscv/shamt-64.d: Likewise. * testsuite/gas/riscv/shamt-64.l: Likewise. * testsuite/gas/riscv/shamt-64.s: Likewise.
2021-04-16Update the ChangeLog, and add the missing entries.Nelson Chu1-2/+6
2021-04-16RISC-V: compress "addi d,CV,z" to "c.mv d,CV"Lifang Xia2-9/+9
PR 27732 gas/ * testsuite/gas/riscv/c-zero-imm.d: Compress addi a4,a4,0 to c.mv a4,a4. * testsuite/gas/riscv/c-zero-imm.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress "addi d,CV,z" to "c.mv d,CV".
2021-04-14Re: PR27723, Internal error in select_cie_for_fdeAlan Modra2-68/+67
Let's make sure what we allow in the CIE initial instructions and what select_cie_for_fde compares for a match is always in sync. Also correct the previous patch that allowed DW_CFA_GNU_window_save to be part of the CIE initial instructions, which was likely a mistake. PR 27723 * dw2gencfi.c (initial_cie_insn): New function, extracted from.. (select_cie_for_fde): ..here. Simplify.
2021-04-14PR27723, Internal error in select_cie_for_fdeAlan Modra2-0/+10
PR 27723 * dw2gencfi.c (select_cie_for_fde): Handle DW_CFA_val_offset, DW_CFA_GNU_window_save and DW_CFA_restore_state.
2021-04-13m68hc11 gas testsuite wartAlan Modra2-13/+15
Writing to a potentially read-only source directory is not good. * testsuite/gas/m68hc11/m68hc11.exp (gas_m68hc11_message): Don't write to $srcdir. Use gas_host_run and read output file rather than gas_start/gas_finish.
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