| Age | Commit message (Collapse) | Author | Files | Lines |
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Adjust the testsuite expected disassemblies to take this into account.
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* elf32-arm.c (PLT_THUMB_STUB_SIZE): Define.
(elf32_arm_plt_thumb_stub): New.
(struct elf32_arm_link_hash_entry): Add plt_thumb_refcount
and plt_got_offset.
(elf32_arm_link_hash_traverse): Fix typo.
(elf32_arm_link_hash_table): Add obfd.
(elf32_arm_link_hash_newfunc): Initialize new fields.
(elf32_arm_copy_indirect_symbol): Copy plt_thumb_refcount.
(elf32_arm_link_hash_table_create): Initialize obfd.
(record_arm_to_thumb_glue): Mark the glue as a local ARM function.
(record_thumb_to_arm_glue): Mark the glue as a local Thumb function.
(bfd_elf32_arm_get_bfd_for_interworking): Verify that the
interworking BFD is not dynamic.
(bfd_elf32_arm_process_before_allocation): Handle R_ARM_PLT32. Do
not emit glue for PLT references.
(elf32_arm_final_link_relocate): Handle Thumb functions. Do not
emit glue for PLT references. Support the Thumb PLT prefix.
(elf32_arm_gc_sweep_hook): Handle R_ARM_THM_PC22 and
plt_thumb_refcount.
(elf32_arm_check_relocs): Likewise.
(elf32_arm_adjust_dynamic_symbol): Handle Thumb functions and
plt_thumb_refcount.
(allocate_dynrelocs): Handle Thumb PLT references.
(elf32_arm_finish_dynamic_symbol): Likewise.
(elf32_arm_symbol_processing): New function.
(elf_backend_symbol_processing): Define.
opcodes/
* arm-dis.c (WORD_ADDRESS): Define.
(print_insn): Use it. Correct big-endian end-of-section handling.
gas/testsuite/
* gas/arm/mapping.d: Expect F markers for Thumb code.
* gas/arm/unwind.d: Update big-endian pattern.
ld/
* emultempl/armelf.em (arm_elf_set_bfd_for_interworking): Don't use
a dynamic object for stubs.
ld/testsuite/
* ld-arm/mixed-app.d, ld-arm/mixed-app.r, ld-arm/mixed-app.s,
ld-arm/mixed-app.sym, ld-arm/mixed-lib.d, ld-arm/mixed-lib.r,
ld-arm/mixed-lib.s, ld-arm/mixed-lib.sym, ld-arm/arm-dyn.ld,
ld-arm/arm-lib.ld: New files.
* ld-arm/arm-app-abs32.d, ld-arm/arm-app-abs32.r, ld-arm/arm-app.d,
ld-arm/arm-app.r, ld-arm/arm-lib-plt32.d, ld-arm/arm-lib-plt32.r,
ld-arm/arm-lib.d, ld-arm/arm-lib.r, ld-arm/arm-static-app.d,
ld-arm/arm-static-app.r: Update for big-endian.
* ld-arm/arm-elf.exp: Run the new tests.
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include/ChangeLog
* xtensa-isa-internal.h (xtensa_interface_internal): Add class_id.
* xtensa-isa.h (xtensa_interface_class_id): New prototype.
bfd/ChangeLog
* xtensa-isa.c (xtensa_interface_class_id): New.
gas/ChangeLog
* config/tc-xtensa.c (finish_vinsn): Clear pending instruction if
there is a conflict.
(check_t1_t2_reads_and_writes): Check for both reads and writes to
interfaces that are related as determined by xtensa_interface_class_id.
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Add a test of this fix.
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* config/tc-xtensa.c (MAX_IMMED6): Change value to 65.
gas/testsuite/
* gas/xtensa/short_branch_offset.s: New.
* gas/xtensa/short_branch_offset.d: New.
* gas/xtensa/all.exp: Run new test.
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relaxing at the end of a loop. Don't mark frags as UNREACHABLE or
MAYBE_UNREACHABLE.
(relax_frag_immed): Update call to update_next_frag_state.
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* gas/i386/intelok.s: Likewise.
* gas/i386/opcode.d: Update.
* gas/i386/intelok.d: Update.
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* read.h (s_app_file_string): Likewise.
* read.c (s_app_file_string): Likewise.
(s_app_file): Adjust s_app_file_string call.
* config/tc-mips.c (s_mips_file): Likewise.
* config/obj-coff.h (obj_app_file): Add app param.
* config/obj-ecoff.h (obj_app_file): Likewise.
* config/obj-multi.h (obj_app_file): Likewise.
* config/obj-elf.h (elf_file_symbol): Likewise.
* config/obj-elf.c (elf_file_symbol): Only emit one file symbol
if called for # preprocessor lines.
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PR 528
* symbols.c (resolve_symbol_value): Convert weak symbols only
for Windows PECOFF.
(symbol_equated_reloc_p): Don't equate weaks when relocating
only for Windows PECOFF.
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* config/tc-crx.c (print_insn): Check and set insn_addr.
* config/tc-crx.h (md_frag_check): Define.
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* gas/i386/general.s: Add movzb.
* gas/i386/general.l: Updated.
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(md_estimate_size_before_relax): Use it.
(find_address_of_next_align_frag): Likewise.
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* config/tc-crx.c: Rename argument types.
(processing_arg_number): Rename to 'cur_arg_num'.
(get_number_of_bits): Rename to 'set_operand_size'.
(get_operandtype): Rename to 'parse_operand', totally rewrite.
(set_cons_rparams): Rename to 'set_operand', totally rewrite.
(set_indexmode_parameters): Remove function, integrate its code into
'set_operand'.
(set_operand_size): Get rid of 'Operand Number' function parameter -
use global variable 'cur_arg_num' instead.
Use a local 'argument' pointer to reference the current argument.
(parse_operand): Likewise.
(set_operand): Likewise.
(process_label_constant): Likewise.
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* config/tc-crx.c: Rename argument types.
(processing_arg_number): Rename to 'cur_arg_num'.
(get_number_of_bits): Rename to 'set_operand_size'.
(get_operandtype): Rename to 'parse_operand', totally rewrite.
(set_cons_rparams): Rename to 'set_operand', totally rewrite.
(set_indexmode_parameters): Remove function, integrate its code into 'set_operand'.
(set_operand_size): Get rid of 'Operand Number' function parameter - use global variable 'cur_arg_num' instead.
Use a local 'argument' pointer to reference the current argument.
(parse_operand): Likewise.
(set_operand): Likewise.
(process_label_constant): Likewise.
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(add_section_rename): Delete. Inlined into...
(build_section_rename): ...here. Use xstrdup instead of strdup.
(xtensa_section_rename): Drop "const" from argument and return types.
(md_show_usage): Indent to match show_usage().
* config/tc-xtensa.h: Remove XTENSA_SECTION_RENAME ifdefs.
(tc_canonicalize_section_name): Define.
(md_elf_section_rename): Remove unused macro.
* doc/as.texinfo (Overview): Document Xtensa --rename-section option.
* doc/c-xtensa.texi (Xtensa Options): Likewise.
(Frame Directive): Delete.
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* configure.in (arm-*-oabi*, thumb-*-oabi*): Remove.
* configure: Regenerated.
bfd/
* Makefile.am (BFD32_BACKENDS, BFD32_BACKENDS_CFILES): Replace
elfarm-nabi with elf32-arm. Remove elfarm-oabi.
(elf32-arm.lo): Replace elfarm-nabi.lo rule. Remove elf32-arm.h
dependency.
* config.bfd: Move arm-*-oabi* and thumb-*-oabi* from obsolete list
to a new removed list. Remove normal configuration stanzas.
* configure.in: (bfd_elf32_bigarm_vec, bfd_elf32_bigarm_symbian_vec)
(bfd_elf32_littlearm_symbian_vec, bfd_elf32_littlearm_vec): Replace
elfarm-nabi.lo with elf32-arm.lo.
(bfd_elf32_bigarm_oabi_vec, bfd_elf32_littlearm_oabi_vec): Remove.
* elf32-arm.c: Renamed from elfarm-nabi.c. Inline elf32-arm.h.
* elf32-arm.h: Remove.
* elfarm-oabi.c: Remove.
* targets.c (_bfd_target_vector): Remove bfd_elf32_bigarm_oabi_vec
and bfd_elf32_littlearm_oabi_vec.
* aclocal.m4, Makefile.in, configure, doc/Makefile.in: Regenerated.
gas/
* configure.in: Remove arm-*-oabi and thumb-*-oabi.
* config/tc-arm.c (target_oabi): Delete.
(md_apply_fix3, elf32_arm_target_format): Remove target_oabi checks.
(arm_opts): Remove moabi.
* doc/as.texinfo (Overview): Remove documentation of -moabi.
* doc/c-arm.texi (ARM Options): Likewise.
* configure: Regenerated.
ld/
* Makefile.am (ALL_EMULATIONS): Remove earmelf_oabi.o.
(earmelf_oabi.c): Remove rule.
* configure.tgt: Remove arm-*-oabi and thumb-*-oabi.
* emulparams/armelf_oabi.sh, emultempl/armelf_oabi.em: Delete files.
* Makefile.in: Regenerated.
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* gas/cris/operand-err-1.s (test.m constant): Remove xfail marker
and update rationale. Mark "ba [external_symbol]" and "ba [r3]"
as invalid.
* gas/ieee-fp/x930509a.exp: setup_xfail for crisv32-*-*.
* gas/macros/macros.exp: setup_xfail strings for crisv32-*-*.
* gas/cris/abs32-1.s, gas/cris/arch-err-1.s,
gas/cris/arch-err-2.s, gas/cris/arch-err-3.s,
gas/cris/arch-err-4.s, gas/cris/arch-err-5.s,
gas/cris/bound-err-1.s, gas/cris/brokw-3b.s,
gas/cris/march-err-1.s, gas/cris/march-err-2.s,
gas/cris/push-err-1.s, gas/cris/push-err-2.s,
gas/cris/pushpopv32.s, gas/cris/rd-abs32-1.d,
gas/cris/rd-abs32-2.d, gas/cris/rd-arch-1.d, gas/cris/rd-arch-2.d,
gas/cris/rd-arch-3.d, gas/cris/rd-bkw1b.d, gas/cris/rd-bkw2b.d,
gas/cris/rd-bkw3b.d, gas/cris/rd-bound1.d, gas/cris/rd-bound1.s,
gas/cris/rd-bound2.d, gas/cris/rd-bound3.d, gas/cris/rd-bound4.d,
gas/cris/rd-break32.d, gas/cris/rd-ppv1032.d, gas/cris/rd-ppv32.d,
gas/cris/rd-spr-1.d, gas/cris/rd-spr-1.s, gas/cris/rd-usp-1.d,
gas/cris/rd-usp-1b.d, gas/cris/rd-v10_32o-1.d,
gas/cris/rd-v10_32o-2.d, gas/cris/rd-v10_32o-2.s,
gas/cris/rd-v32-b1.d, gas/cris/rd-v32-b1.s, gas/cris/rd-v32-b2.d,
gas/cris/rd-v32-b2.s, gas/cris/rd-v32-b3.d, gas/cris/rd-v32-b3.s,
gas/cris/rd-v32-f1.d, gas/cris/rd-v32-f1.s, gas/cris/rd-v32-i1.d,
gas/cris/rd-v32-i1.s, gas/cris/rd-v32-l1.d, gas/cris/rd-v32-l1.s,
gas/cris/rd-v32-l3.d, gas/cris/rd-v32-l3.s, gas/cris/rd-v32-l4.d,
gas/cris/rd-v32-l4.s, gas/cris/rd-v32o-1.d, gas/cris/rd-v32s-1.d,
gas/cris/rd-v32s-2.d, gas/cris/rd-v32s-2.s, gas/cris/rd-v32s-3.d,
gas/cris/rd-v32s-3.s, gas/cris/rd-v32s-4.d, gas/cris/rd-v32s-4.s,
gas/cris/rd-vao-1.d, gas/cris/v32-err-1.s, gas/cris/v32-err-10.s,
gas/cris/v32-err-11.s, gas/cris/v32-err-2.s, gas/cris/v32-err-3.s,
gas/cris/v32-err-4.s, gas/cris/v32-err-5.s, gas/cris/v32-err-6.s,
gas/cris/v32-err-7.s, gas/cris/v32-err-8.s, gas/cris/v32-err-9.s:
New tests.
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DEFAULT_CRIS_ARCH. Handle crisv32-*-linux-gnu* like
cris-*-linux-gnu* and crisv32-*-* like cris-*-*.
* configure: Regenerate.
* config/tc-cris.c (enum cris_archs): New.
(cris_mach, cris_arch_from_string, s_cris_arch, get_sup_reg)
(cris_insn_ver_valid_for_arch): New functions.
(DEFAULT_CRIS_ARCH): New macro, default to cris_any_v0_v10.
(cris_arch): New variable.
(md_pseudo_table): New pseudo .arch.
(err_for_dangerous_mul_placement): Initialize according to
DEFAULT_CRIS_ARCH.
(STATE_COND_BRANCH): Renamed from STATE_CONDITIONAL_BRANCH.
All users changed.
(STATE_COND_BRANCH_V32, STATE_COND_BRANCH_COMMON)
(STATE_ABS_BRANCH_V32, STATE_LAPC, BRANCH_BF_V32, BRANCH_BB_V32)
(BRANCH_WF_V32, BRANCH_WB_V32): New.
(BRANCH_BF, BRANCH_BB, BRANCH_WF, BRANCH_WB): Don't undef after
use in md_cris_relax_table.
(md_cris_relax_table): Add entries for STATE_COND_BRANCH_V32,
STATE_COND_BRANCH_COMMON, STATE_ABS_BRANCH_V32, STATE_LAPC.
Update and improve head comment.
(OPTION_PIC): Define in terms of previous option, OPTION_US.
(OPTION_MULBUG_ABORT_ON, OPTION_MULBUG_ABORT_OFF): Similar.
(OPTION_ARCH): New.
(md_longopts): New option --march=...
(cris_any_v0_v10_long_jump_size, crisv32_long_jump_size): New
macros.
(md_long_jump_size): Initialize in terms of DEFAULT_CRIS_ARCH.
(HANDLE_RELAXABLE): New macro.
(md_estimate_size_before_relax): Use HANDLE_RELAXABLE for common
cases. Check for weak symbols and assume not relaxable. Handle
STATE_COND_BRANCH_V32, STATE_COND_BRANCH_COMMON,
STATE_ABS_BRANCH_V32, STATE_LAPC. Use new variable symbolP, not
fragP->fr_symbol.
(md_convert_frag): Handle STATE_COND_BRANCH_V32,
STATE_COND_BRANCH_COMMON, STATE_ABS_BRANCH_V32, STATE_LAPC.
(cris_create_short_jump): Adjust for CRISv32.
(md_create_long_jump): Ditto. Emit error for common_v10_v32.
(md_begin): Define symbols "..asm.arch.cris.v32",
"..asm.arch.cris.v10", "..asm.arch.cris.common_v10_v32" and
"..asm.arch.cris.any_v0_v10". Use cris_insn_ver_valid_for_arch
when entering opcode table entry points.
(md_assemble): Adjust branch handling for CRISv32. Handle LAPC
relaxation. In fix_new_exp call for main insn, pass 1 for pcrel
parameter for 8, 16 and 32-bit pc-relative insns and LAPC.
(cris_process_instruction): Initialize out_insnp->insn_type to
CRIS_INSN_NONE, not CRIS_INSN_NORMAL.
<case ']', '[', 'A', 'd', 'Q', 'N', 'n', 'Y', 'U', 'u', 'T'>: New
cases.
<case 'm'>: Check that modified_char == '.'.
<invalid operands>: Consume the rest of the line.
When operands don't match, skip over subsequent insns with
non-matching version specifier but same mnemonic.
<immediate constant, case SIZE_SPEC_REG>: Immediate operands for
special registers in CRISv32 are always 32 bit long.
<immediate constant, case SIZE_FIELD_SIGNED, SIZE_FIELD_UNSIGNED>:
New cases.
(get_gen_reg): Only recognize "PC" when followed by "+]" for v32
and compatible. Recognize "ACR" for v32, unless followed by "+".
(get_spec_reg): Consider cris_arch when looking up register.
(get_autoinc_prefix_or_indir_op): Don't recognize assignment for
v32 or compatible.
(get_3op_or_dip_prefix_op): Check for ']' after seeing '[rN+'.
(cris_get_expression): Restore input_line_pointer if failing "early".
(get_flags): Consider cris_arch and recognize flags accordingly.
(branch_disp): Adjust for CRISv32.
(gen_cond_branch_32): Similar. Emit error for common_v10_v32.
(cris_number_to_imm): Use as_bad_where, not as_bad. Remove
related FIXME. Don't insist on BFD_RELOC_32_PCREL fixup to be
resolved. Don't enter zeros in object file for
BFD_RELOC_32_PCREL.
<case BFD_RELOC_CRIS_LAPCQ_OFFSET, BFD_RELOC_CRIS_SIGNED_16>
<case BFD_RELOC_CRIS_SIGNED_8>: New case.
(md_parse_option): Break out "return 1".
<OPTION_ARCH> New case.
(tc_gen_reloc): <case BFD_RELOC_CRIS_LAPCQ_OFFSET>
<case BFD_RELOC_CRIS_SIGNED_16, BFD_RELOC_CRIS_SIGNED_8>
<case BFD_RELOC_CRIS_UNSIGNED_8, BFD_RELOC_CRIS_UNSIGNED_16>
<case BFD_RELOC_32_PCREL>: New cases.
Addends for non-zero fx_pcrel are too in fx_offset.
(md_show_usage): Show --march=<arch>.
(md_apply_fix3): Adjust val for BFD_RELOC_CRIS_LAPCQ_OFFSET.
(md_pcrel_from): BFD_RELOC_CRIS_LAPCQ_OFFSET is PC-relative too.
(s_syntax) <struct syntaxes>: Properly constify member operand.
* config/tc-cris.h (TARGET_MACH): Define.
(cris_mach): Declare.
* doc/as.texinfo (Overview) <CRIS>: Add --march=...
* doc/c-cris.texi (CRIS-Symbols): New node for built-in symbols.
(CRIS-Opts): Document --march=...
(CRIS-Pseudos): Document .arch.
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2004-11-04 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (set_intel_syntax): Allow % in symbol names when
intel syntax and no register prefix, allow $ in symbol names when
intel syntax.
(set_16bit_gcc_code_flag): Replace literal 'l' by LONG_MNEM_SUFFIX.
(intel_float_operand): Add fourth return value indicating math control
operations. Make classification more precise.
(md_assemble): Complain if memory operand of mov[sz]x has no size
specified.
(parse_insn): Translate word operands to floating point instructions
operating on integers as well as control instructions to short ones
as expected by AT&T syntax. Translate 'd' suffix to short one only for
floating point instructions operating on non-integer operands.
(match_template): Remove fldcw special case. Adjust q-suffix handling
to permit it on fild/fistp/fisttp in AT&T mode.
(process_suffix): Don't guess DefaultSize insns' suffix from
stackop_size for certain floating point control instructions. Guess
suffix for branch and [ls][gi]dt based on flag_code. Split error
messages for Intel and AT&T syntax, and make the condition more strict
for the former. Adjust suppressing of generation of operand size
overrides.
(intel parser): Allow the full set of MASM operators. Add FWORD, TBYTE,
OWORD, and XMMWORD operand size specifiers (TBYTE replaces XWORD). Add
more error checking.
* config/tc-i386.h (BYTE_PTR WORD_PTR DWORD_PTR QWORD_PTR XWORD_PTR
SHORT OFFSET_FLAT FLAT NONE_FOUND): Remove unused defines.
gas/testsuite/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* gas/i386/i386.exp: Execute new tests intelbad and intelok.
* gas/i386/intelbad.[sl]: New test to check for various things not
permitted in Intel mode.
* gas/i386/intel.d, gas/i386/opcode.d, gas/i386/x86-64-opcode.d:
Adjust for change to segment register store.
* gas/i386/intelok.[sd]: New test to check various Intel mode specific
things get handled correctly.
* gas/i386/x86_64.[sd]: Remove unsupported constructs referring to
'high' and 'low' parts of an operand, which the parser previously
accepted while neither telling that it's not supported nor that it
ignored the remainder of the line following these supposed keywords.
include/opcode/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386.h (sldx_Suf): Remove.
(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
(q_FP): Define, implying no REX64.
(x_FP, sl_FP): Imply FloatMF.
(i386_optab): Split reg and mem forms of moving from segment registers
so that the memory forms can ignore the 16-/32-bit operand size
distinction. Adjust a few others for Intel mode. Remove *FP uses from
all non-floating-point instructions. Unite 32- and 64-bit forms of
movsx, movzx, and movd. Adjust floating point operations for the above
changes to the *FP macros. Add DefaultSize to floating point control
insns operating on larger memory ranges. Remove left over comments
hinting at certain insns being Intel-syntax ones where the ones
actually meant are already gone.
opcodes/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
(indirEb): Remove.
(Mp): Use f_mode rather than none at all.
(t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
replaces what previously was x_mode; x_mode now means 128-bit SSE
operands.
(dis386): Make far jumps and calls have an 'l' prefix only in AT&T
mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
pinsrw's second operand is Edqw.
(grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
mode when an operand size override is present or always suffixing.
More instructions will need to be added to this group.
(putop): Handle new macro chars 'C' (short/long suffix selector),
'I' (Intel mode override for following macro char), and 'J' (for
adding the 'l' prefix to far branches in AT&T mode). When an
alternative was specified in the template, honor macro character when
specified for Intel mode.
(OP_E): Handle new *_mode values. Correct pointer specifications for
memory operands. Consolidate output of index register.
(OP_G): Handle new *_mode values.
(OP_I): Handle const_1_mode.
(OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
respective opcode prefix bits have been consumed.
(OP_EM, OP_EX): Provide some default handling for generating pointer
specifications.
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md_short_jump_size, md_long_jump_size.
* write.c [!WORKING_DOT_WORD]: Ditto.
* tc.h [!WORKING_DOT_WORD]: Declare them here. Drop const
qualifier.
* config/tc-cris.h (md_short_jump_size, md_long_jump_size): Don't
declare.
* config/tc-cris.c (md_short_jump_size, md_long_jump_size): Drop
const qualifier in these definitions.
* config/tc-i370.c, config/tc-m68k.c, config/tc-pdp11.c,
config/tc-s390.c, config/tc-tahoe.c, config/tc-vax.c: Ditto.
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produce a .debug_line section to match up with a user provided .debug_info
section.
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* gas/crx/cop_insn.d: Regenerate (after a bug fix in Assembler).
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* config/tc-crx.c (getreg_image): Bug fix, a return value was mistakenly ommited from CRX_C_REGTYPE and CRX_CS_REGTYPE cases.
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* gas/crx/cop_insn.s: Test new Co-Processor instruction 'cpi'.
* gas/crx/list_insn.s: Add hi/lo/u<N> registers tests, fix test bugs.
* gas/crx/cop_insn.d: Regenerate.
* gas/crx/list_insn.d: Likewise.
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* config/tc-crx.c: Remove global variable 'post_inc_mode'.
(get_flags): New function.
(get_number_of_bits): Edit comments, update numeric values to supported sizes.
(process_label_constant): Don't support the colon format (SYMBOL:[s|m|l]).
(set_cons_rparams): Support argument type 'arg_rbase'.
(get_operandtype): Bug fix in 'rbase' operand type parsing.
(handle_LoadStor): Bug fix, first handle post-increment mode.
(getreg_image): Remove redundant code, update according to latest CRX spec.
(print_constant): Bug fix relate to 3-word instructions.
(assemble_insn): Bug fix, when matching instructions, verify also instruction type (not only mnemonic).
Add various error checking.
(preprocess_reglist): Support HI/LO and user registers.
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(get_flags): New function.
(get_number_of_bits): Edit comments, update numeric values to supported sizes.
(process_label_constant): Don't support the colon format (SYMBOL:[s|m|l]).
(set_cons_rparams): Support argument type 'arg_rbase'.
(get_operandtype): Bug fix in 'rbase' operand type parsing.
(handle_LoadStor): Bug fix, first handle post-increment mode.
(getreg_image): Remove redundant code, update according to latest CRX spec.
(print_constant): Bug fix relate to 3-word instructions.
(assemble_insn): Bug fix, when matching instructions, verify also instruction type (not only mnemonic).
Add various error checking.
(preprocess_reglist): Support HI/LO and user registers.
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* config/tc-ia64.c (fixup_unw_records): Don't let the "t" value
in an epilogue directive go negative.
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PR 474
* config/tc-ia64.c (emit_one_bundle): Decrement md.num_slots_in_use
after reporting template error during manual bundling. Reported
by Michael Dupont, michaelx.dupont@intel.com.
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be unsigned immediate.
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(tc_pe_dwarf2_emit_offset): New function.
* config/tc-i386.h (O_secrel): Define as O_md1.
(TC_DWARF2_EMIT_OFFSET): Define.
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* Makefile.in: Regenerate.
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Remove comments about placement of literal pools.
(Literal Directive): Update description of literal placement.
(Literal Prefix Directive): Remove statement that this does not apply
to absolute-mode literals. Describe new section naming scheme.
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* elf32-xtensa.c (elf_xtensa_get_private_bfd_flags): Delete.
(narrow_instruction, widen_instruction): Remove unnecessary calls to
xtensa_format_encode.
(ebb_propose_action): Inline call to ebb_add_proposed_action.
(ebb_add_proposed_action): Delete.
gas ChangeLog
* config/tc-xtensa.c (xtensa_frequency_pseudo): Use set_subseg_freq.
(is_entry_opcode, is_movi_opcode, is_the_loop_opcode, is_jx_opcode,
is_windowed_return_opcode): Delete.
(xtensa_frob_label): Use get_subseg_target_freq.
(md_assemble): Inline call to is_entry_opcode.
(xtensa_handle_align): Inline call to get_frag_is_literal.
(relaxation_requirements): Inline call to is_jx_opcode.
(emit_single_op): Inline call to is_movi_opcode.
(xg_assemble_vliw_tokens): Inline calls to get_frag_is_insn,
get_frag_is_no_transform, is_entry_opcode, and
set_frag_is_specific_opcode. Use get_subseg_total_freq.
(xtensa_fix_a0_b_retw_frags, xtensa_fix_b_j_loop_end_frags,
xtensa_fix_close_loop_end_frags, relax_frag_immed, convert_frag_immed):
Inline calls to get_frag_is_no_transform.
(next_instrs_are_b_retw): Inline call to is_windowed_return_opcode.
(xtensa_fix_short_loop_frags): Inline calls to is_the_loop_opcode and
get_frag_is_no_transform.
(convert_frag_immed_finish_loop): Inline calls to get_expression_value
and set_frag_is_no_transform.
(get_expression_value): Delete.
(subseg_map struct): Rename cur_total_freq to total_freq. Rename
cur_target_freq to target_freq.
(get_subseg_info): Split out code to create a new map entry into ...
(add_subseg_info): ... this new function.
(get_last_insn_flags): Check if get_subseg_info succeeded.
(set_last_insn_flags): Call add_subseg_info if needed.
(get_subseg_total_freq, get_subseg_target_freq, set_subseg_freq): New.
(xtensa_reorder_segments): Compute last_sec while counting sections.
Remove call to get_last_sec.
(get_last_sec): Delete.
(cache_literal_section): Inline call to retrieve_literal_seg and its
callees, seg_present and add_seg_list.
(retrieve_literal_seg, seg_present, add_seg_list): Delete.
(get_frag_is_insn, get_frag_is_no_transform,
set_frag_is_specific_opcode, set_frag_is_no_transform): Delete.
* config/tc-xtensa.h (MAX_SLOTS): Reduce from 31 to 15.
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* elf32-xtensa.c: Use ISO C90 formatting.
gas ChangeLog
* config/tc-xtensa.c: Use ISO C90 formatting.
* config/tc-xtensa.h: Likewise.
* config/xtensa-istack.h: Likewise.
* config/xtensa-relax.c: Likewise.
* config/xtensa-relax.h: Likewise.
ld ChangeLog
* emultempl/xtensaelf.em: Use ISO C90 formatting.
opcodes ChangeLog
* xtensa-dis.c: Use ISO C90 formatting.
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