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2023-04-13arc: Update GAS testClaudiu Zissulescu3-8/+5
2023-04-12Fail of x86_64 AMX-COMPLEX insns (Intel disassembly)Alan Modra1-0/+1
2023-04-12Comment typo fixAlan Modra1-1/+1
2023-04-10x86: Add inval tests for AMX instructionsHaochen Jiang7-8/+60
2023-04-07Support Intel AMX-COMPLEXHaochen Jiang11-1/+104
2023-04-06gas/write.c use better typesAlan Modra1-3/+3
2023-04-03opcodes/arm: adjust whitespace in cpsie instructionAndrew Burgess2-4/+4
2023-04-03ubsan: aarch64 parse_vector_reg_listAlan Modra1-4/+4
2023-03-31RISC-V: Allocate "various" operand typeTsukasa OI1-17/+47
2023-03-31x86: convert testcases to use .insnJan Beulich39-523/+346
2023-03-31x86: document .insnJan Beulich2-0/+133
2023-03-31x86: handle immediate operands for .insnJan Beulich6-4/+182
2023-03-31x86: allow for multiple immediates in output_disp()Jan Beulich1-5/+5
2023-03-31x86: handle EVEX Disp8 for .insnJan Beulich5-1/+149
2023-03-31x86: process instruction operands for .insnJan Beulich6-21/+432
2023-03-31x86: parse special opcode modifiers for .insnJan Beulich1-1/+38
2023-03-31x86: parse VEX and alike specifiers for .insnJan Beulich5-6/+250
2023-03-31x86: introduce .insn directiveJan Beulich6-10/+213
2023-03-30aarch64: Add the RPRFM instructionRichard Sandiford7-1/+186
2023-03-30aarch64: Add the SVE FCLAMP instructionRichard Sandiford8-1/+102
2023-03-30aarch64: Add new SVE shift instructionsRichard Sandiford7-0/+97
2023-03-30aarch64: Add new SVE saturating conversion instructionsRichard Sandiford7-0/+93
2023-03-30aarch64: Add new SVE dot-product instructionsRichard Sandiford9-12/+186
2023-03-30aarch64: Add the SVE BFMLSL instructionsRichard Sandiford7-0/+143
2023-03-30aarch64: Add the SME2 UZP and ZIP instructionsRichard Sandiford7-0/+352
2023-03-30aarch64: Add the SME2 UNPK instructionsRichard Sandiford7-0/+188
2023-03-30aarch64: Add the SME2 shift instructionsRichard Sandiford15-3/+384
2023-03-30aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford14-0/+328
2023-03-30aarch64: Add the SME2 FP<->FP conversion instructionsRichard Sandiford7-0/+102
2023-03-30aarch64: Add the SME2 FP<->int conversion instructionsRichard Sandiford7-0/+245
2023-03-30aarch64: Add the SME2 CLAMP instructionsRichard Sandiford7-0/+407
2023-03-30aarch64: Add the SME2 MOPA and MOPS instructionsRichard Sandiford7-0/+177
2023-03-30aarch64: Add the SME2 vertical dot-product instructionsRichard Sandiford28-0/+556
2023-03-30aarch64: Add the SME2 dot-product instructionsRichard Sandiford28-0/+2355
2023-03-30aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford22-0/+2317
2023-03-30aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford8-0/+2084
2023-03-30aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford15-0/+1129
2023-03-30aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford8-6/+2218
2023-03-30aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford22-1/+1424
2023-03-30aarch64: Add the SME2 ZT0 instructionsRichard Sandiford11-12/+746
2023-03-30aarch64: Add the SME2 predicate-related instructionsRichard Sandiford26-24/+2680
2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford29-0/+6804
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford10-2/+1598
2023-03-30aarch64: Add support for predicate-as-counter registersRichard Sandiford15-3/+331
2023-03-30aarch64; Add support for vector offset rangesRichard Sandiford11-0/+84
2023-03-30aarch64: Add support for vgx2 and vgx4Richard Sandiford13-1/+119
2023-03-30aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford1-1/+1
2023-03-30aarch64: Add +sme2Richard Sandiford3-0/+6
2023-03-30aarch64: Prefer register ranges & support wrappingRichard Sandiford11-982/+1038
2023-03-30aarch64: Add support for strided register listsRichard Sandiford4-27/+53
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