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2017-09-05Missing relocation R_PPC_VLE_ADDR20 and add VLE flag to details in readelfAlexander Fedotov-B556134-2/+33
include/ * elf/ppc.h (R_PPC_VLE_ADDR20): New relocation. bfd/ * elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_VLE_ADDR20. (ppc_elf_check_relocs): Handle it. (ppc_elf_vle_split20): New function. (ppc_elf_relocate_section): Handle R_PPC_VLE_ADDR20. binutils/ * readelf.c (get_elf_section_flags): Add VLE. (process_section_headers): Add VLE key to details. gas/ * config/tc-ppc.c (md_parse_option): Handle "mno-vle" flag. (ppc_elf_section_letter): New function. * config/tc-ppc.h (md_elf_section_letter): New. * testsuite/gas/elf/section10.d: Adjust for VLE.
2017-09-01Enable support for the AArch64 dot-prod instruction in the Cortex A55 and ↵Tamar Christina2-2/+7
A75 cpus. * config/tc-aarch64.c (aarch64_cpus): Enable DOTPROD for cortex-a55 and cortx-a75.
2017-08-30MIPS/BFD: Correct microMIPS cross-mode BAL to JALX relaxationMaciej W. Rozycki6-0/+114
Fix a bug in commit a6ebf6169a1b ("MIPS: Convert cross-mode BAL to JALX") and in BFD linker relaxation correct the microMIPS interpretation of the branch offset, which is supposed to be shifted by 1 bit, rather than 2 as in the regular MIPS case. bfd/ * elfxx-mips.c (mips_elf_perform_relocation): Correct microMIPS branch offset interpretation. gas/ * testsuite/gas/mips/branch-addend-micromips.d: New test. * testsuite/gas/mips/branch-addend-micromips-n32.d: New test. * testsuite/gas/mips/branch-addend-micromips-n64.d: New test. * testsuite/gas/mips/branch-addend-micromips.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/bal-jalx-addend-micromips.d: New test. * testsuite/ld-mips-elf/bal-jalx-addend-micromips-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-addend-micromips-n64.d: New test. * testsuite/ld-mips-elf/bal-jalx-local-micromips.d: New test. * testsuite/ld-mips-elf/bal-jalx-local-micromips-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-local-micromips-n64.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-micromips.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips-n64.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2017-08-30MIPS/GAS: Also respect `-mignore-branch-isa' with MIPS16 codeMaciej W. Rozycki23-1/+411
Fix a bug in commit 8b10b0b3e100 ("MIPS: Add options to control branch ISA checks") and with the `-mignore-branch-isa' command-line option also lift a GAS check for invalid MIPS16 branches between ISA modes, which is made separately from regular MIPS and microMIPS checks. gas/ * config/tc-mips.c (md_convert_frag): Respect `mips_ignore_branch_isa'. * testsuite/gas/mips/branch-local-5.d: New test. * testsuite/gas/mips/branch-local-n32-5.d: New test. * testsuite/gas/mips/branch-local-n64-5.d: New test. * testsuite/gas/mips/branch-local-6.d: New test. * testsuite/gas/mips/branch-local-n32-6.d: New test. * testsuite/gas/mips/branch-local-n64-6.d: New test. * testsuite/gas/mips/branch-local-7.d: New test. * testsuite/gas/mips/branch-local-n32-7.d: New test. * testsuite/gas/mips/branch-local-n64-7.d: New test. * testsuite/gas/mips/branch-local-ignore-5.d: New test. * testsuite/gas/mips/branch-local-ignore-n32-5.d: New test. * testsuite/gas/mips/branch-local-ignore-n64-5.d: New test. * testsuite/gas/mips/branch-local-ignore-6.d: New test. * testsuite/gas/mips/branch-local-ignore-n32-6.d: New test. * testsuite/gas/mips/branch-local-ignore-n64-6.d: New test. * testsuite/gas/mips/branch-local-5.l: New stderr output. * testsuite/gas/mips/branch-local-6.l: New stderr output. * testsuite/gas/mips/branch-local-5.s: New test source. * testsuite/gas/mips/branch-local-6.s: New test source. * testsuite/gas/mips/branch-local-7.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2017-08-30MIPS/GAS/testsuite: Deduplicate error lists of branch local testsMaciej W. Rozycki9-20/+17
Complement commit 7795a8f8bdde ("MIPS/GAS/testsuite: Convert branch local list tests to dump tests") and share identical error lists among branch local tests, removing duplicate copies. gas/ * testsuite/gas/mips/branch-local-n32-2.d: Use `branch-local-2.l' for `error-output'. * testsuite/gas/mips/branch-local-n64-2.d: Likewise. * testsuite/gas/mips/branch-local-n32-3.d: Use `branch-local-3.l' for `error-output'. * testsuite/gas/mips/branch-local-n64-3.d: Likewise. * testsuite/gas/mips/branch-local-n32-2.l: Remove file. * testsuite/gas/mips/branch-local-n64-2.l: Remove file. * testsuite/gas/mips/branch-local-n32-3.l: Remove file. * testsuite/gas/mips/branch-local-n64-3.l: Remove file.
2017-08-29Improve MSP430 section placement.Jozef Lawrynowicz6-3/+70
ld * emultempl/msp430.em (change_output_section): New function. (move_prefixed_section): New function. (add_region_prefix): New function. (msp430_elf_after_open): New function. (gld${EMULATION_NAME}_add_options): Implement. (gld${EMULATION_NAME}_list_options): Implement. (gld${EMULATION_NAME}_handle_option): Implement. * ld.texinfo: Document new options. * testsuite/ld-msp430-elf/main-bss-lower.d: New. * testsuite/ld-msp430-elf/main-bss-upper.d: New. * testsuite/ld-msp430-elf/main-const-lower.d: New. * testsuite/ld-msp430-elf/main-const-upper.d: New. * testsuite/ld-msp430-elf/main-text-lower.d: New. * testsuite/ld-msp430-elf/main-text-upper.d: New. * testsuite/ld-msp430-elf/main-var-lower.d: New. * testsuite/ld-msp430-elf/main-var-upper.d: New. * testsuite/ld-msp430-elf/main-with-data-bss-unique-sec.s: New. * testsuite/ld-msp430-elf/main-with-data-bss.s: New. * testsuite/ld-msp430-elf/main-with-text-rodata-unique-sec.s: New. * testsuite/ld-msp430-elf/main-with-text-rodata.s: New. * testsuite/ld-msp430-elf/msp430-elf.exp: New. * testsuite/ld-msp430-elf/msp430-no-lower.ld: New. * testsuite/ld-msp430-elf/msp430.ld: New. * emultempl/msp430.em (data_statement_size): New. (eval_upper_either_sections): New. (eval_lower_either_sections): New. (intermediate_relax_sections): New. (msp430_elf_after_allocation): New. * emultempl/msp430.em (gld${EMULATION_NAME}_place_orphan): Always place sections in the lower region. gas * config/tc-msp430.c (md_parse_option): Define high data and high bss symbols if -mdata-region is passed. Define -mdata-region open. * doc/c-msp430.texi: Document -mdata-region. * testsuite/gas/msp430/high-data-bss-sym.d: New test. * testsuite/gas/msp430/high-data-bss-sym.s: New. * testsuite/gas/msp430/msp430.exp: Add -mdata-region tests.
2017-08-24[PowerPC VLE] Add SPE2 and EFS2 instructions supportAlexander Fedotov18-1/+2581
include/ * opcode/ppc.h: (spe2_opcodes, spe2_num_opcodes): New. (PPC_OPCODE_SPE2): New define. (PPC_OPCODE_EFS2): Likewise. (SPE2_XOP): Likewise. (SPE2_XOP_TO_SEG): Likewise. opcodes/ * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "e200z4" entry. New entries efs2 and spe2. Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry. (SPE2_OPCD_SEGS): New macro. (spe2_opcd_indices): New. (disassemble_init_powerpc): Handle SPE2 opcodes. (lookup_spe2): New function. (print_insn_powerpc): call lookup_spe2. * ppc-opc.c (insert_evuimm1_ex0): New function. (extract_evuimm1_ex0): Likewise. (insert_evuimm_lt8): Likewise. (extract_evuimm_lt8): Likewise. (insert_off_spe2): Likewise. (extract_off_spe2): Likewise. (insert_Ddd): Likewise. (extract_Ddd): Likewise. (DD): New operand. (EVUIMM_LT8): Likewise. (EVUIMM_LT16): Adjust. (MMMM): New operand. (EVUIMM_1): Likewise. (EVUIMM_1_EX0): Likewise. (EVUIMM_2): Adjust. (NNN): New operand. (VX_OFF_SPE2): Likewise. (BBB): Likewise. (DDD): Likewise. (VX_MASK_DDD): New mask. (HH): New operand. (VX_RA_CONST): New macro. (VX_RA_CONST_MASK): Likewise. (VX_RB_CONST): Likewise. (VX_RB_CONST_MASK): Likewise. (VX_OFF_SPE2_MASK): Likewise. (VX_SPE_CRFD): Likewise. (VX_SPE_CRFD_MASK VX): Likewise. (VX_SPE2_CLR): Likewise. (VX_SPE2_CLR_MASK): Likewise. (VX_SPE2_SPLATB): Likewise. (VX_SPE2_SPLATB_MASK): Likewise. (VX_SPE2_OCTET): Likewise. (VX_SPE2_OCTET_MASK): Likewise. (VX_SPE2_DDHH): Likewise. (VX_SPE2_DDHH_MASK): Likewise. (VX_SPE2_HH): Likewise. (VX_SPE2_HH_MASK): Likewise. (VX_SPE2_EVMAR): Likewise. (VX_SPE2_EVMAR_MASK): Likewise. (PPCSPE2): Likewise. (PPCEFS2): Likewise. (vle_opcodes): Add EFS2 and some missing SPE opcodes. (powerpc_macros): Map old SPE instructions have new names with the same opcodes. Add SPE2 instructions which just are mapped to SPE2. (spe2_opcodes): Add SPE2 opcodes. gas/ * config/tc-ppc.c: (md_parse_option): Add mspe2 switch. (md_show_usage): Document -mspe2. (ppc_setup_opcodes): Handle spe2_opcodes. * doc/as.texinfo: Document -mspe2. * doc/c-ppc.texi: Likewise. * testsuite/gas/ppc/efs.d: New file. * testsuite/gas/ppc/efs.s: Likewise. * testsuite/gas/ppc/efs2.d: Likewise. * testsuite/gas/ppc/efs2.s: Likewise. * testsuite/gas/ppc/ppc.exp: Run new tests. * testsuite/gas/ppc/spe.d: New file. * testsuite/gas/ppc/spe.s: Likewise. * testsuite/gas/ppc/spe2-checks.d: Likewise. * testsuite/gas/ppc/spe2-checks.l: Likewise. * testsuite/gas/ppc/spe2-checks.s: Likewise. * testsuite/gas/ppc/spe2.d: Likewise. * testsuite/gas/ppc/spe2.s: Likewise. * testsuite/gas/ppc/spe_ambiguous.d: Likewise. * testsuite/gas/ppc/spe_ambiguous.s: Likewise.
2017-08-23gas: enable PC-relative diff relocations on sparc64James Clarke3-1/+56
gas/ * config/tc-sparc.c (tc_gen_reloc): Convert BFD_RELOC_8/16/32/64 into the corresponding BFD_RELOC_8/16/32/64_PCREL relocation when requested. * config/tc-sparc.h (DIFF_EXPR_OK): Define to enable PC-relative diff relocations. (TC_FORCE_RELOCATION_SUB_LOCAL): Define to ensure only supported relocations are made PC-relative. (CFI_DIFF_EXPR_OK): Define to 0 to force BFD_RELOC_32_PCREL to be used directly, since otherwise BFD_RELOC_SPARC_UA32 will be used for .eh_frame which cannot in general be converted to a BFD_RELOC_32_PCREL due to alignment requirements.
2017-08-23Assemble powerpc vle lsp tests with -a32Alan Modra3-2/+7
-mvle isn't a valid 64-bit option. * testsuite/gas/ppc/lsp-checks.d: Assemble with -a32. * testsuite/gas/ppc/lsp.d: Likewise.
2017-08-21[PowerPC VLE] Add LSP (Lightweight Signal Processing) instruction supportAlexander Fedotov7-0/+1603
include/ * opcode/ppc.h (PPC_OPCODE_LSP): New define. opcodes/ * ppc-opc.c (insert_evuimm2_ex0): New function. (extract_evuimm2_ex0): Likewise. (insert_evuimm4_ex0): Likewise. (extract_evuimm4_ex0): Likewise. (insert_evuimm8_ex0): Likewise. (extract_evuimm8_ex0): Likewise. (insert_evuimm_lt16): Likewise. (extract_evuimm_lt16): Likewise. (insert_rD_rS_even): Likewise. (extract_rD_rS_even): Likewise. (insert_off_lsp): Likewise. (extract_off_lsp): Likewise. (RD_EVEN): New operand. (RS_EVEN): Likewise. (RSQ): Adjust. (EVUIMM_LT16): New operand. (HTM_SI): Adjust. (EVUIMM_2_EX0): New operand. (EVUIMM_4): Adjust. (EVUIMM_4_EX0): New operand. (EVUIMM_8): Adjust. (EVUIMM_8_EX0): New operand. (WS): Adjust. (VX_OFF): New operand. (VX_LSP): New macro. (VX_LSP_MASK): Likewise. (VX_LSP_OFF_MASK): Likewise. (PPC_OPCODE_LSP): Likewise. (vle_opcodes): Add LSP opcodes. * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry. gas/ * testsuite/gas/ppc/lsp-checks.d, * testsuite/gas/ppc/lsp-checks.l, * testsuite/gas/ppc/lsp-checks.s: New test. * testsuite/gas/ppc/lsp.d, * testsuite/gas/ppc/lsp.s: New test. * testsuite/gas/ppc/ppc.exp: Run new tests.
2017-08-15[Patch AArch64] Turn lr, fp, ip0 and ip1 into proper aliasesRamana Radhakrishnan7-5/+47
We got a report from the linux-arm-kernel folks about getting spurious warnings when building the kernel with binutils 2.29. See https://www.spinics.net/lists/arm-kernel/msg599929.html which boils down to this testcase. $> cat /tmp/tst.s lr .req x30 /tmp/tst.s: Assembler messages: /tmp/tst.s:1: Warning: ignoring attempt to redefine built-in register 'lr' Instead let's treat this as a proper alias at startup time thus avoiding the problem and treating these as proper aliases rather than new registers. This means that attempts to redefine the alias with the same "name" will provoke no warning and attempts to redefine the alias to something else will provoke the above mentioned warning. Tested make check-gas and no regressions. Ok to apply to trunk (and backport to 2.29 branch)? Regards Ramana
2017-08-11Also disallow global alias of common symbolH.J. Lu14-4/+61
We can't create alias of common symbol. Local alias of common symbol has been disallowed. But global alias of common symbol is disallowed when the common symbol is seen first and silently dropped otherwise. This patch disallows alias of common symbol in all cases. gas/ PR gas/21667 * read.c (pseudo_set): Update error message for alias of common symbol. * write.c (write_object_file): Disallow both local and global aliases of common symbol. * testsuite/gas/elf/common5a.d: New file. * testsuite/gas/elf/common5a.l: Likewise. * testsuite/gas/elf/common5a.s: Likewise. * testsuite/gas/elf/common5b.d: Likewise. * testsuite/gas/elf/common5b.l: Likewise. * testsuite/gas/elf/common5b.s: Likewise. * testsuite/gas/elf/common5c.d: Likewise. * testsuite/gas/elf/common5c.s: Likewise. * testsuite/gas/elf/common5d.d: Likewise. * testsuite/gas/elf/common5d.s: Likewise. * testsuite/gas/elf/elf.exp: Run common5a, common5b, common5c and common5d.
2017-08-10Fix memory corruption when assembling an i386 darwin source file.Nick Clifton2-5/+24
PR gas/21939 * config/obj-macho.c (obj_mach_o_set_indirect_symbols): Increase size of indirect_syms array so that it is large enough to hold every symbol if necessary.
2017-08-09[ARM] Don't warn on REG_SP when used in CRC32 instructionsJiong Wang9-16/+63
According to ARMv8-A architecture manual, REG_SP is allowed in CRC32 instructions in Thumb mode. It is REG_PC that will cause unpredictable behaviours on both ARM and Thumb. This patch removes the incorrect warning on Thumb mode. Meanwhile the disassembler is updated to use format "<bitfield>R" instead of "<bitfield>S". "<bitfield>S" is not used elsewhere. so I have deleted related code from the disassembler. gas/ * config/tc-arm.c (do_crc32_1): Remove warning on REG_SP for thumb_mode. * testsuite/gas/arm/crc32-armv8-a-bad.d: Update exepcted result. * testsuite/gas/arm/crc32-armv8-r-bad.d: Likewise. * testsuite/gas/arm/crc32-armv8-a.d: Likewise. * testsuite/gas/arm/crc32-armv8-r.d: Likewise. * testsuite/gas/arm/crc32-armv8-ar-bad.s: Update test case. * testsuite/gas/arm/crc32-armv8-ar.s: Likewise. * testsuite/gas/arm/crc32-bad.l: Update expected error message. opcode/ * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for register operands in CRC instructions. (print_insn_thumb32): Remove "<bitfield>S" support. Updated the comments.
2017-08-02Fix gas and binutils testsuite failures for am33_2.0-linux target.Nick Clifton14-23/+44
gas * testsuite/gas/all/gas.exp: Add am33 to the skip lists of tests passed over by the mn10300 target. * testsuite/gas/elf/elf.exp: Likewise. * testsuite/gas/elf/dwarf2-11.d: Correct skip of am33 target. * testsuite/gas/elf/dwarf2-12.d: Likewise. * testsuite/gas/elf/dwarf2-13.d: Likewise. * testsuite/gas/elf/dwarf2-14.d: Likewise. * testsuite/gas/elf/dwarf2-15.d: Likewise. * testsuite/gas/elf/dwarf2-16.d: Likewise. * testsuite/gas/elf/dwarf2-17.d: Likewise. * testsuite/gas/elf/dwarf2-18.d: Likewise. * testsuite/gas/elf/dwarf2-5.d: Likewise. * testsuite/gas/elf/dwarf2-6.d: Likewise. * testsuite/gas/elf/dwarf2-7.d: Likewise. binutils * testsuite/binutils-all/objdump.exp (cpus_expected): Add am33-2.
2017-08-01x86: Update segment register check in Intel syntaxH.J. Lu7-18/+57
https://sourceware.org/ml/binutils/2009-04/msg00223.html introduced a new Intel syntax parser which accepts mov eax, fs:gs:[eax] It ignores anything between ':'s after fs and treats mov eax, DWORD PTR fs:foobar:16 mov eax, DWORD PTR fs:foobar:barfoo:16 mov eax, DWORD PTR fs:ds:16 mov eax, DWORD PTR fs:ds:cs:16 as mov eax, DWORD PTR fs:16 This patch updates segment register check and only allows a single ':'. PR gas/21874 * config/tc-i386-intel.c (i386_intel_operand): Update segment register check. * testsuite/gas/i386/intelok.s: Replace "fs:gs:[eax]" with "fs:[eax]". * testsuite/gas/i386/inval-seg.s: Add tests for invalid segment register. * testsuite/gas/i386/x86-64-inval-seg.s: Likewise. * testsuite/gas/i386/inval-seg.l: Updated. * testsuite/gas/i386/x86-64-inval-seg.l: Likewise.
2017-07-31Fix bb instructions with double-word condition on hppa.John David Anglin2-3/+6
2017-07-28Fix problems parsing RISCV architecture extenstions in the assembler.Andrew Waterman2-11/+13
* config/tc-riscv.c (riscv_set_arch): Handle the Q subset like all other subsets. Obviate use-after-free.
2017-07-25Fix typos in error and option messages in OPCODES library.Nick Clifton2-1/+6
PR 21739 opcodes * arc-opc.c (insert_rhv2): Use lower case first letter in error message. (insert_r0): Likewise. (insert_r1): Likewise. (insert_r2): Likewise. (insert_r3): Likewise. (insert_sp): Likewise. (insert_gp): Likewise. (insert_pcl): Likewise. (insert_blink): Likewise. (insert_ilink1): Likewise. (insert_ilink2): Likewise. (insert_ras): Likewise. (insert_rbs): Likewise. (insert_rcs): Likewise. (insert_simm3s): Likewise. (insert_rrange): Likewise. (insert_r13el): Likewise. (insert_fpel): Likewise. (insert_blinkel): Likewise. (insert_pclel): Likewise. (insert_nps_bitop_size_2b): Likewise. (insert_nps_imm_offset): Likewise. (insert_nps_imm_entry): Likewise. (insert_nps_size_16bit): Likewise. (insert_nps_##NAME##_pos): Likewise. (insert_nps_##NAME): Likewise. (insert_nps_bitop_ins_ext): Likewise. (insert_nps_##NAME): Likewise. (insert_nps_min_hofs): Likewise. (insert_nps_##NAME): Likewise. (insert_nps_rbdouble_64): Likewise. (insert_nps_misc_imm_offset): Likewise. * riscv-dis.c (print_riscv_disassembler_options): Fix typo in option description. gas * testsuite/gas/arc/add_s-err.s: Update expected error message.
2017-07-24Stop the generation of mapping symbols in the debug sections of ARM and ↵Nick Clifton3-1/+18
AArch64 binaries. PR 21809 * config/tc-aarch64.c (aarch64_init_frag): Do not set a mapping state for frags in debug sections. * config/tc-arm.c (arm_init_frag): Likewise.
2017-07-24* dwarf2dbg.c (dwarf2dbg_final_check): Rename local variable exp from expr.Hans-Peter Nilsson2-5/+10
Trying to build (for mmix-knuth-mmixware but I don't think that matters) yields the following (repeatable on e.g. CompileFarm gcc20 sporting gcc-4.7.2 as default): gcc -DHAVE_CONFIG_H -I. -I/home/hp/binutils/src/gas -I. -I/home/hp/binutils/src/gas -I../bfd -I/home/hp/binutils/src/gas/config -I/home/hp/binutils/src/gas/../include -I/home/hp/binutils/src/gas/.. -I/home/hp/binutils/src/gas/../bfd -DLOCALEDIR="\"/usr/local/share/locale\"" -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow -Werror -Wwrite-strings -I/home/hp/binutils/src/gas/../zlib -g -O2 -MT dwarf2dbg.o -MD -MP -MF .deps/dwarf2dbg.Tpo -c -o dwarf2dbg.o /home/hp/binutils/src/gas/dwarf2dbg.c cc1: warnings being treated as errors /home/hp/binutils/src/gas/dwarf2dbg.c: In function 'dwarf2dbg_final_check': /home/hp/binutils/src/gas/dwarf2dbg.c:2246: error: declaration of 'expr' shadows a global declaration /home/hp/binutils/src/gas/expr.h:180: error: shadowed declaration is here make[4]: *** [dwarf2dbg.o] Error 1 IIRC this is a false namespace clash and the warning is not observable with a new-enough gcc. Committed as obvious. brgds, H-P PS. Idea: -Wcompiler; warn about constructs problematic with e.g. old gcc. 1/2 ;-)
2017-07-21This patch introduces support for specifing views in .loc directives, so ↵Alexandre Oliva60-55/+1369
that the compiler can use the assembler to generate line number information and have the assembler determine view numbers to multiple views at the same program counter. binutils* dwarf.c (struct State_Machine_Registers): Add view field. (reset_state_machine): Reset view. (process_extended_line_op): Reset view when appropriate. (display_debug_lines_raw): Increment or reset view when appropriate. Print nonzero views. Support print view resets, disabled by default. (display_debug_lines_decoded): Likewise. Disambiguate op_code tests, enabling printing of end_sequence. * testsuite/binutils-all/dw2-1.W: Add nonzero views. * testsuite/binutils-all/dw2-3.W: Likewise. * testsuite/binutils-all/dw2-3gabi.W: Likewise. * testsuite/binutils-all/dw5.W: Add end sequence lines. * testsuite/binutils-all/i386/compressed-1a.d: Add nonzero views. * testsuite/binutils-all/libdw2-compressedgabi.out: Likewise. * testsuite/binutils-all/objdump.W: Likewise. * testsuite/binutils-all/objdump.WL: Add end sequence lines. * testsuite/binutils-all/x86-64/compressed-1a.d: Add nonzero views. gas * doc/as.texinfo (.loc): Document view support. * dwarf2dbg.c (unused): Check offset of next in struct line_entry. (current): Initialize view. (force_reset_view, view_assert_failed): New variables. (reverse_line_entry_list): New function. (set_or_check_view): Likewise. (dwarf2_gen_line_info_1): Call it. (dwarf2_where): Set view to NULL. (dwarf2_emit_insn): Return early when called before first file. (dwarf2_directive_loc): Add view support. Emit insn immediately when view option is given. (process_entries): Avoid set_address to reset view when a known address change already implies the view reset. (dwarf2dbg_final_check): New function. * dwarf2dbg.h (struct dwarf2_line_info): Add view. (dwarf2dbg_final_check): Declare. * read.c (s_leb128): Parse expression as deferred. * testsuite/gas/all/gas.exp: Run sleb128-9. * testsuite/gas/all/sleb128-9.d: New. * testsuite/gas/all/sleb128-9.l: New. * testsuite/gas/all/sleb128-9.s: New. * testsuite/gas/elf/dwarf2-1.d: Add nonzero views. * testsuite/gas/elf/dwarf2-2.d: Likewise. * testsuite/gas/elf/dwarf2-5.d: New. * testsuite/gas/elf/dwarf2-5.s: New. * testsuite/gas/elf/dwarf2-6.d: New. * testsuite/gas/elf/dwarf2-6.s: New. * testsuite/gas/elf/dwarf2-7.d: New. * testsuite/gas/elf/dwarf2-7.s: New. * testsuite/gas/elf/dwarf2-8.d: New. * testsuite/gas/elf/dwarf2-8.l: New. * testsuite/gas/elf/dwarf2-8.s: New. * testsuite/gas/elf/dwarf2-9.d: New. * testsuite/gas/elf/dwarf2-9.l: New. * testsuite/gas/elf/dwarf2-9.s: New. * testsuite/gas/elf/dwarf2-10.d: New. * testsuite/gas/elf/dwarf2-10.l: New. * testsuite/gas/elf/dwarf2-10.s: New. * testsuite/gas/elf/dwarf2-11.d: New. * testsuite/gas/elf/dwarf2-11.s: New. * testsuite/gas/elf/dwarf2-12.d: New. * testsuite/gas/elf/dwarf2-12.s: New. * testsuite/gas/elf/dwarf2-13.d: New. * testsuite/gas/elf/dwarf2-13.s: New. * testsuite/gas/elf/dwarf2-14.d: New. * testsuite/gas/elf/dwarf2-14.s: New. * testsuite/gas/elf/dwarf2-15.d: New. * testsuite/gas/elf/dwarf2-15.s: New. * testsuite/gas/elf/dwarf2-16.d: New. * testsuite/gas/elf/dwarf2-16.s: New. * testsuite/gas/elf/dwarf2-17.d: New. * testsuite/gas/elf/dwarf2-17.s: New. * testsuite/gas/elf/dwarf2-18.d: New. * testsuite/gas/elf/dwarf2-18.s: New. * testsuite/gas/elf/elf.exp: Run dwarf2-5..18 tests. * testsuite/gas/i386/dw2-compress-1.d: Add nonzero views. * testsuite/gas/i386/dw2-compressed-1.d: Likewise. * testsuite/gas/i386/ilp32/lns/lns-duplicate.d: Likewise. * testsuite/gas/lns/lns-big-delta.d: Likewise. * testsuite/gas/lns/lns-duplicate.d: Likewise. * testsuite/gas/mips/loc-swap-2.d: Likewise. * testsuite/gas/mips/loc-swap-3.d: Likewise. * testsuite/gas/mips/loc-swap.d: Likewise. * testsuite/gas/mips/micromips@loc-swap-2.d: Likewise. * testsuite/gas/mips/micromips@loc-swap.d: Likewise. * testsuite/gas/mips/mips16@loc-swap-2.d: Likewise. * testsuite/gas/mips/mips16@loc-swap.d: Likewise. * testsuite/gas/mips/mips16e@loc-swap.d: Likewise. * write.c (write_object_file): Check pending view asserts. (cvt_frag_to_fill): Complain about undefined leb128 operand.
2017-07-21S/390: Support z14 as CPU name.Andreas Krebbel4-3/+10
With IBM z14 officially announced I can add z14 as CPU name. No regressions with that patch on s390x. gas/ChangeLog: 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): Add z14 as alternate CPU name. * doc/as.texinfo: Add z14 to CPU string list. * doc/c-s390.texi: Likewise. opcodes/ChangeLog: 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Enable z14 as CPU string in the opcode table.
2017-07-19[ARC] Add JLI support.John Eric Martin4-0/+43
The following relocation types were added to GCC/binutils: ARC_JLI_SECTOFF is a relocation type in Metaware that is now used by GCC as well to adjust the index of function calls to functions with attribute jli_call_always. bfd/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> John Eric Martin <John.Martin@emmicro-us.com> * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf32-arc.c (JLI): Define. * reloc.c: Add JLI relocations. gas/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/jli-1.d: New file. * testsuite/gas/arc/jli-1.s: Likewise. * testsuite/gas/arc/taux.d: Update for jli_base. include/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> John Eric Martin <John.Martin@emmicro-us.com> * elf/arc-reloc.def: Add JLI relocs howto. * opcode/arc-func.h (replace_jli): New function. ld/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> John Eric Martin <John.Martin@emmicro-us.com> * emulparams/arcelf.sh (JLI_START_TABLE): Define. * scripttempl/elfarc.sc: Handle jlitab section. * scripttempl/elfarcv2.sc: Likewise. * testsuite/ld-arc/arc.exp: Add JLI test. * testsuite/ld-arc/jli-script.ld: New file. * testsuite/ld-arc/jli-simple.dd: Likewise. * testsuite/ld-arc/jli-simple.rd: Likewise. * testsuite/ld-arc/jli-simple.s: Likewise. * testsuite/ld/testsuite/ld-arc/jli-overflow.s: Likewise. * testsuite/ld/testsuite/ld-arc/jli-overflow.d: Likewise. * testsuite/ld/testsuite/ld-arc/jli-overflow.err: Likewise. opcode/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> John Eric Martin <John.Martin@emmicro-us.com> * arc-opc.c (UIMM10_6_S_JLIOFF): Define. (UIMM3_23): Adjust accordingly. * arc-regs.h: Add/correct jli_base register. * arc-tbl.h (jli_s): Likewise.
2017-07-19Remove datasize measurements based on sbrk()Tristan Gingold2-19/+6
binutils/ * nm.c (show_stats): Remove variable. (long_options): Remove --stats option. (main): Remove handling of --stats. ld/ * ldmain.c (main): Remove display of data size. gas/ * as.c (start_sbrk): Remove. (main): Remove assignment. (dump_statistics): Remove display of data size.
2017-07-19Fix gas crash on missing seh_endproc.Tristan Gingold5-4/+22
gas/ * testsuite/gas/pe/seh-x64-err-2.s: New test. * testsuite/gas/pe/seh-x64-err-2.l: New stderr output. * testsuite/gas/pe/pe.exp: Add test. * config/obj-coff-seh.c (obj_coff_seh_do_final): Don't try to end seh part.
2017-07-18Fix spelling typos.Yuri Chornovian11-59/+73
2017-07-18Import updated Ukranian and Swedish translations.Nick Clifton2-245/+140
gas * po/uk.po: Updated Ukranian translation. binutils* po/sv.po: Updated Swedish translation.
2017-07-17Update assembler documentation on some AVR cores.Georg-Johann Lay3-4/+30
PR 21472 * config/tc-avr.c (mcu_types): Add entries for: attiny212, attiny214, attiny412, attiny414, attiny814, attiny1614, attiny1616, attiny1617, attiny3214, attiny3216, attiny3217. (md_show_usage): Adjust doc for "avrxmega3". * doc/c-avr.texi (AVR options) [-mmcu=]: Adjust doc for avrxmega3. Add MCUs: attiny212, attiny214, attiny412, attiny414, attiny416, attiny417, attiny814, attiny816, attiny817, attiny1614, attiny1616, attiny1617, attiny3214, attiny3216, attiny3217.
2017-07-13Add RDMA support for falkot/qdf24xx.Jim Wilson2-2/+9
gas/ * config/tc-arch64.c (aarch64_cpus): Add AARCH64_FEATURE_RDMA to falkor and qdf24xx entries.
2017-07-12Update PO filesAlan Modra11-20540/+22098
bfd/ * po/es.po: Update from translationproject.org/latest/bfd/. * po/fi.po: Likewise. * po/fr.po: Likewise. * po/id.po: Likewise. * po/ja.po: Likewise. * po/ro.po: Likewise. * po/ru.po: Likewise. * po/sr.po: Likewise. * po/sv.po: Likewise. * po/tr.po: Likewise. * po/uk.po: Likewise. * po/vi.po: Likewise. * po/zh_CN.po: Likewise. * po/hr.po: New file from translationproject.org. * configure.ac (ALL_LINGUAS): Add hr. Sort. * configure: Regenerate. binutils/ * po/bg.po: Update from translationproject.org/latest/binutils/. * po/ca.po: Likewise. * po/da.po: Likewise. * po/es.po: Likewise. * po/fi.po: Likewise. * po/fr.po: Likewise. * po/hr.po: Likewise. * po/id.po: Likewise. * po/it.po: Likewise. * po/ja.po: Likewise. * po/ro.po: Likewise. * po/ru.po: Likewise. * po/sk.po: Likewise. * po/sr.po: Likewise. * po/sv.po: Likewise. * po/tr.po: Likewise. * po/uk.po: Likewise. * po/vi.po: Likewise. * po/zh_CN.po: Likewise. * po/zh_TW.po: Likewise. gas/ * po/es.po: Update from translationproject.org/latest/gas/. * po/fi.po: Likewise. * po/fr.po: Likewise. * po/id.po: Likewise. * po/ja.po: Likewise. * po/ru.po: Likewise. * po/sv.po: Likewise. * po/tr.po: Likewise. * po/uk.po: Likewise. * po/zh_CN.po: Likewise. gold/ * po/es.po: Update from translationproject.org/latest/gold/. * po/fi.po: Likewise. * po/fr.po: Likewise. * po/id.po: Likewise. * po/it.po: Likewise. * po/vi.po: Likewise. * po/zh_CN.po: Likewise. * po/ja.po: New file from translationproject.org. * po/sv.po: Likewise. * po/uk.po: Likewise. gprof/ * po/bg.po: Update from translationproject.org/latest/gprof/. * po/da.po: Likewise. * po/de.po: Likewise. * po/eo.po: Likewise. * po/es.po: Likewise. * po/fi.po: Likewise. * po/fr.po: Likewise. * po/ga.po: Likewise. * po/hu.po: Likewise. * po/id.po: Likewise. * po/it.po: Likewise. * po/ja.po: Likewise. * po/ms.po: Likewise. * po/nl.po: Likewise. * po/pt_BR.po: Likewise. * po/ro.po: Likewise. * po/ru.po: Likewise. * po/sr.po: Likewise. * po/sv.po: Likewise. * po/tr.po: Likewise. * po/uk.po: Likewise. * po/vi.po: Likewise. ld/ * po/bg.po: Update from translationproject.org/latest/ld/. * po/da.po: Likewise. * po/es.po: Likewise. * po/fi.po: Likewise. * po/fr.po: Likewise. * po/id.po: Likewise. * po/it.po: Likewise. * po/ja.po: Likewise. * po/tr.po: Likewise. * po/uk.po: Likewise. * po/vi.po: Likewise. * po/zh_CN.po: Likewise. * po/zh_TW.po: Likewise. * po/de.po: New file from translationproject.org. * po/ru.po: Likewise. * configure.ac (ALL_LINGUAS): Add de, ru. Sort. * configure: Regenerate. opcodes/ * po/da.po: Update from translationproject.org/latest/opcodes/. * po/de.po: Likewise. * po/es.po: Likewise. * po/fi.po: Likewise. * po/fr.po: Likewise. * po/id.po: Likewise. * po/it.po: Likewise. * po/nl.po: Likewise. * po/pt_BR.po: Likewise. * po/ro.po: Likewise. * po/sv.po: Likewise. * po/tr.po: Likewise. * po/uk.po: Likewise. * po/vi.po: Likewise. * po/zh_CN.po: Likewise.
2017-07-12Fix compile time warnings building the binutils with gcc 7.1.1.Nick Clifton3-4/+13
bfd * elf32-xtensa.c (elf_xtensa_get_plt_section): Increase length of plt_name buffer. (elf_xtensa_get_gotplt_section): Increase length of got_name buffer. * mach-o-arm.c (bfd_mach_o_arm_canonicalize_one_reloc): Add a default return of FALSE. * mach-o-i386.c (bfd_mach_o_i386_canonicalize_one_reloc): Add a default return of FALSE. binutils * dwarf.c (dwarf_vmatoa_1): Do not pass a NULL string pointer to sprintf. * srconv.c (walk_tree_type): Initialise the spare field of the IT_dty structure. gas * config/tc-pru.c (md_assemble): Add continue statement after handling 'E' operand character. * config/tc-v850.c (md_assemble): Initialise the 'insn' variable.
2017-07-05[ARM] Add support for Cortex-A55 and Cortex-A75.James Greenhalgh3-0/+13
This patch adds support for the ARM Cortex-A55 and Cortex-A75 processors. The ARM Cortex-A55 and Cortex-A75 procsessors implement the ARMv8-A architecture, with support for the ARMv8.1-A and ARMv8.2-A extensions, including support for the 16-bit floating point extensions. The 16-bit floating-point extensions are optional, and we haven't defined an option mapping straight to them thus far, so this patch first needs to add one of those in include/opcode/arm.h, then we can simply add the CPU names as usual in config/tc-arm.c . Tested on arm-none-eabi. 2017-07-05 James Greenhalgh <james.greenhalgh@arm.com> * config/tc-arm.c (arm_cpus): Add Cortex-A55 and Cortex-A75. * doc/c-arm.texi (-mcpu): Document Cortex-A55 and Cortex-A75.
2017-07-05X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctlyBorislav Petkov5-0/+37
The instructions are not documented in the Intel SDM but are documented in the AMD APM as an alias to the group 2, ModRM.reg == 4 variant. Both AMD and Intel CPUs execute the C[0-1] and D[0-3] instructions as expected, i.e., like the /4 aliases: #include <stdio.h> int main(void) { int a = 2; printf ("a before: %d\n", a); asm volatile(".byte 0xd0,0xf0" /* SHL %al */ : "+a" (a)); printf("a after : %d\n", a); return 0; } $ ./a.out a before: 2 a after : 4
2017-07-05Fixup changelog entries for previous commitRamana Radhakrishnan1-0/+11
40c7d50720e04c3d1ef1695a8097f735bafbe54f
2017-07-04[Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-ARamana Radhakrishnan6-0/+28
This patch adds support mvfr2 control registers for armv8-a as this was missed from the original port to armv8-a (documented at G6.2.109 in (Issue B.a) of the ARM-ARM. This was discovered by an internal user of the GNU toolchain. I'd like to backport this to the binutils 2.28 and binutils 2.29 release branch if possible (with suitable testing and basically checking removing the armv8-r parts). Tristan - are you ok with the backports ? Applied to trunk. regards Ramana 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * gas/config/tc-arm.c (arm_regs): Add MVFR2. (do_vmrs): Constraint for MVFR2 and armv8. (do_vmsr): Likewise. * gas/testsuite/gas/arm/armv8-a+fp.d: Update. * gas/testsuite/gas/arm/armv8-ar+fp.s: Likewise. * gas/testsuite/gas/arm/armv8-r+fp.d: Likewise. * gas/testsuite/gas/arm/vfp-bad.s: Likewise. * gas/testsuite/gas/arm/vfp-bad.l: Likewise. * opcodes/arm-dis.c: Support MVFR2 in disassembly with vmrs and vmsr.
2017-07-04Regenerate configure.Tristan Gingold2-10/+14
bfd/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * version.m4: Bump version to 2.29.51 * configure: Regenerate. binutils/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gas/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gprof/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. ld/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. opcodes/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * configure: Regenerate.
2017-07-04Add markers.Tristan Gingold2-0/+6
binutils/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.29. gas/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.29. ld/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.29.
2017-07-03Disable symver test on hppa64-hpuxAlan Modra2-0/+5
The syntax for common symbols is different on that target. * testsuite/gas/elf/symver.d: Don't run on hppa64-hpux.
2017-07-01MIPS/GAS: Use a switch on relaxation type in microMIPS fixup creationMaciej W. Rozycki2-10/+20
Use a switch on the relaxation type rather than a chain of conditionals in microMIPS fixup creation, improving source code structure and aiding the compiler with code generation. gas/ * config/tc-mips.c (md_convert_frag): Use a switch on the microMIPS relaxation type rather than a chain of conditionals.
2017-07-01MIPS/GAS: Use frag symbol/offset directly in fixup creationMaciej W. Rozycki2-44/+38
There is no need to use a helper expression in the creation of fixups made from a frag's symbol and offset, because a simple `symbol+offset' expression can be handled directly, with the use of a `fix_new' rather than a `fix_new_exp' call. Rewrite `md_convert_frag' using `fix_new' then and remove all the unneeded helper expressions, simplifying code. gas/ * config/tc-mips.c (md_convert_frag): Rewrite `fix_new_exp' calls in terms of `fix_new'.
2017-07-01MIPS/GAS: Use non-zero frag offset directly in PIC branch relaxationMaciej W. Rozycki10-12/+137
Use frag symbols with a non-zero offset directly in `fix_new_exp' calls made in PIC branch relaxation. There is no need here to make a helper symbol to hold the result of a `symbol+offset' calculation requested as only branches to local symbols are relaxed and in this case the LO16 part of the PIC address load sequence will have the offset accounted for in calculation against the local GOT entry retrieved as the GOT16 high part. Consequently actual code produed is identical whether a helper symbol is used or the original `symbol+offset' expression used directly. Verify that this is indeed the case with GAS and LD tests. gas/ * config/tc-mips.c (md_convert_frag): Don't make a helper expression symbol for `fix_new_exp' called with a non-zero offset. * testsuite/gas/mips/relax-offset.d: New test. * testsuite/gas/mips/mips1@relax-offset.d: New test. * testsuite/gas/mips/r3000@relax-offset.d: New test. * testsuite/gas/mips/r3900@relax-offset.d: New test. * testsuite/gas/mips/micromips@relax-offset.d: New test. * testsuite/gas/mips/relax-offset.l: New stderr output. * testsuite/gas/mips/relax-offset.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/relax-offset.dd: New test. * testsuite/ld-mips-elf/relax-offset.gd: New test. * testsuite/ld-mips-elf/relax-offset-umips.dd: New test. * testsuite/ld-mips-elf/relax-offset-umips.gd: New test. * testsuite/ld-mips-elf/relax-offset.ld: New test linker script. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests. (prune_warnings): New temporary procedure.
2017-06-30Add support for a __gcc_isr pseudo isntruction to the AVR assembler.Georg-Johann Lay10-7/+1050
PR gas/21683 include * opcode/avr.h (AVR_INSN): Add one for __gcc_isr. gas * doc/c-avr.texi (AVR Options) <-mgcc-isr>: Document it. (AVR Pseudo Instructions): New node. * config/tc-avr.h (md_pre_output_hook): Define to avr_pre_output_hook. (md_undefined_symbol): Define to avr_undefined_symbol. (avr_pre_output_hook, avr_undefined_symbol): New protos. * config/tc-avr.c (struc-symbol.h): Include it. (ISR_CHUNK_Done, ISR_CHUNK_Prologue, ISR_CHUNK_Epilogue): New enums. (avr_isr, avr_gccisr_opcode) (avr_no_sreg_hash, avr_no_sreg): New static variables. (avr_opt_s) <have_gccisr>: Add field. (avr_opt): Add initializer for have_gccisr. (enum options) <OPTION_HAVE_GCCISR>: Add enum. (md_longopts) <"mgcc-isr">: Add entry. (md_show_usage): Document -mgcc-isr. (md_parse_option) [OPTION_HAVE_GCCISR]: Handle it. (md_undefined_symbol): Remove. (avr_undefined_symbol, avr_pre_output_hook): New fuctions. (md_begin) <avr_no_sreg_hash, avr_gccisr_opcode>: Initialize them. (avr_operand) <pregno>: Add argument and set *pregno if function is called for a register constraint. [N]: Handle constraint. (avr_operands) <avr_operand>: Pass 5th parameter to calls. [avr_opt.have_gccisr]: Call avr_update_gccisr. Call avr_gccisr_operands instead of avr_operands. (avr_update_gccisr, avr_emit_insn, avr_patch_gccisr_frag) (avr_gccisr_operands, avr_check_gccisr_done): New static functions. * testsuite/gas/avr/gccisr-01.d: New test. * testsuite/gas/avr/gccisr-01.s: New test. * testsuite/gas/avr/gccisr-02.d: New test. * testsuite/gas/avr/gccisr-02.s: New test. * testsuite/gas/avr/gccisr-03.d: New test. * testsuite/gas/avr/gccisr-03.s: New test.
2017-06-30MIPS/GAS: Update `match_float_constant' and `match_operand' descriptionsMaciej W. Rozycki2-5/+10
Complement commit a92713e60ef4 ("Preparse MIPS instructions into tokens"), <https://sourceware.org/ml/binutils/2013-07/msg00143.html>, and update `match_float_constant' and `match_operand' function descriptions according to semantics changes. gas/ * config/tc-mips.c (match_float_constant): Update description. (match_operand): Likewise.
2017-06-30MIPS: Add microMIPS XPA supportMaciej W. Rozycki4-5/+37
Add support for the base and Virtualization ASE microMIPS instructions as per the architecture specifications[1][2][3][4]. Most of this change by Andrew Bennett. [1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00582, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", p. 340 [2] "microMIPS32 Architecture for Programmers Volume IV-i: Virtualization Module of the microMIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00848, Revision 1.06, December 10, 2013, Section 6.1 "Overview", pp. 133, 136 [3] "MIPS Architecture for Programmers Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", pp. 415, 444 [4] "microMIPS64 Architecture for Programmers Volume IV-i: Virtualization Module of the microMIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00849, Revision 1.06, December 10, 2013, Section 6.1 "Overview", pp. 134-135, 139-140 binutils/ * NEWS: Mention microMIPS XPA support. opcodes/ * micromips-opc.c (XPA, XPAVZ): New macros. (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and "mthgc0". gas/ * config/tc-mips.c (mips_ases): Add microMIPS XPA support. * testsuite/gas/mips/micromips@xpa.d: New test. * testsuite/gas/mips/mips.exp: Run the new test. Enable `xpa-virt-err' test for `micromips'.
2017-06-30MIPS: Add microMIPS R5 supportMaciej W. Rozycki3-1/+16
Add base microMIPS Release 5 ISA support and the ERETNC instruction in particular, as per the architecture specifications[1][2]. Most of this change by Andrew Bennett. References: [1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00582, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", pp. 266-267 [2] "MIPS Architecture for Programmers Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", pp. 326-327 binutils/ * NEWS: Mention microMIPS Release 5 ISA support. opcodes/ * micromips-opc.c (I36): New macro. (micromips_opcodes): Add "eretnc". gas/ * testsuite/gas/mips/micromips@r5.d: New test. * testsuite/gas/mips/mips.exp: Run the new test.
2017-06-30MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki10-3/+62
Correct a commit 7d64c587c15f ("Add support for the MIPS eXtended Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization ASE instructions to be wrongly always enabled with the selection of the MIPS32r2 or higher ISA. For example this source assembles successfully as shown below: $ cat xpa.s mfhc0 $2, $1 $ as -32 -mips32 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1' $ as -32 -mips32r2 -o xpa.o xpa.s $ objdump -d xpa.o xpa.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: 40420800 mfhc0 v0,c0_random ... $ To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA instructions in the opcode table. Additionally, for XPA Virtualization ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA). Now the same source is correctly rejected unless the `-mxpa' option is also used: $ as -32 -mips32r2 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1' $ as -32 -mips32r2 -mxpa -o xpa.o xpa.s $ Add test cases for XPA base and XPA Virtualization ASE instructions. Parts of this change by Andrew Bennett. include/ * opcode/mips.h (ASE_XPA_VIRT): New macro. opcodes/ * mips-dis.c (mips_calculate_combination_ases): Handle the ASE_XPA_VIRT flag. (parse_mips_ase_option): New function. (parse_mips_dis_option): Factor out ASE option handling to the new function. Call `mips_calculate_combination_ases'. * mips-opc.c (XPAVZ): New macro. (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0", "mfhgc0", "mthc0" and "mthgc0". gas/ * config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag. * testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump' flags. Add `-mvirt' to `as' flags. * testsuite/gas/mips/xpa-err.d: New test. * testsuite/gas/mips/xpa-virt-err.d: New test. * testsuite/gas/mips/xpa-err.l: New stderr output. * testsuite/gas/mips/xpa-virt-err.l: New stderr output. * testsuite/gas/mips/xpa-err.s: New test source. * testsuite/gas/mips/xpa-virt-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.
2017-06-30MIPS/opcodes: Correctly combine ASE flags for ASE_MIPS16E2_MT calculationMaciej W. Rozycki3-42/+20
Correct a commit 25499ac7ee92 ("MIPS16e2: Add MIPS16e2 ASE support") disassembler bug with the handling of the ASE_MIPS16E2_MT combination ASE flag, where the calculation uses MIPS ABI Flags directly rather than calculated internal ASE flags. Consequently code does not correctly set the ASE_MIPS16E2_MT flag when the MIPS16e2 ASE flag and the MT ASE flag come from different sources, i.e. one from the BFD chosen and the other one from MIPS ABI Flags. Fix this by using internal ASE_MT and ASE_MIPS16E2 flags in a separate subsequent step, factored out to a dedicated function for use with future combination ASE flags. Adjust the `mips16e2@mips16e2-mt-sub.d' test case accordingly, where the MT flag comes from the BFD selected for the disassembler and the MIPS16e2 flag comes from the ELF binary itself. opcodes/ * mips-dis.c (mips_calculate_combination_ases): New function. (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT calculation to the new function. (set_default_mips_dis_options): Call the new function. gas/ * testsuite/gas/mips/mips16e2@mips16e2-mt-sub.d: Adjust for the ASE_MIPS16E2_MT flag disassembler fix. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e2-mt-sub.d: Likewise.
2017-06-30MIPS/GAS: Clear the ASE_MIPS16E2_MT flag for recalculationMaciej W. Rozycki6-0/+35
Correct a commit 25499ac7ee92 ("MIPS16e2: Add MIPS16e2 ASE support") GAS bug with the handling of the ASE_MIPS16E2_MT combination ASE flag, which is not correctly calculated as `.set nomips16e2' and `.set nomt' pseudo-ops are processed. This leads to code like: $ cat foo.s .set nomt evpe .align 4, 0 $ cat bar.s .set nomips16e2 dvpe .align 4, 0 $ to successfully assemble where it should not: $ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o foo.o foo.s $ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o bar.o bar.s $ objdump -m mips:16 -d foo.o foo.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: f027 6700 evpe ... bar.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: f026 6700 dvpe ... $ This happens because ASE_MIPS16E2_MT once set in `mips_set_ase' is never cleared. Fix the problem by clearing it there before it is calculated based on the ASE_MT and ASE_MIPS16E2 flags, making assembly fail as expected: $ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o foo.o foo.s foo.s: Assembler messages: foo.s:2: Error: opcode not supported on this processor: mips32r3 (mips32r3) `evpe' $ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o bar.o bar.s bar.s: Assembler messages: bar.s:2: Error: opcode not supported on this processor: mips32r3 (mips32r3) `dvpe' $ gas/ * config/tc-mips.c (mips_set_ase): Clear the ASE_MIPS16E2_MT flag before recalculating. * testsuite/gas/mips/mips16e2-mt-err.d: New test. * testsuite/gas/mips/mips16e2-mt-err.l: New stderr output. * testsuite/gas/mips/mips16e2-mt-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina5-3/+1105
gas/ * config/tc-aarch64.c (aarch64_reg_parse_32_64): Accept 4B. (aarch64_features): Added dotprod. * doc/c-aarch64.texi: Added dotprod. * testsuite/gas/aarch64/dotproduct.d: New. * testsuite/gas/aarch64/dotproduct.s: New. opcodes/ * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod. * aarch64-dis.c (aarch64_ext_reglane): Likewise. * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New. (aarch64_feature_dotprod, DOT_INSN): New. (udot, sdot): New. * aarch64-dis-2.c: Regenerated. include/ * opcode/aarch64.h: (AARCH64_FEATURE_DOTPROD): New. (aarch64_insn_class): Added dotprod.
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