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2019-12-12i386: Also check R12-R15 registers when optimizing testq to testbH.J. Lu5-3/+25
2019-12-12i386: Add tests for -malign-branch-boundary and -malign-branchH.J. Lu55-0/+2616
2019-12-12i386: Add -mbranches-within-32B-boundariesH.J. Lu3-0/+31
2019-12-12i386: Align branches within a fixed boundaryH.J. Lu4-3/+1160
2019-12-12gas: Add md_generic_table_relax_fragH.J. Lu3-1/+18
2019-12-12gas signed overflow fixesAlan Modra11-52/+68
2019-12-12obj-evax.c tidyAlan Modra2-29/+35
2019-12-11[gas][arm] Add -mwarn-restrict-itAndre Vieira10-8/+29
2019-12-11x86: further refine SSE check (SSE4a, SHA, GFNI)Jan Beulich7-25/+88
2019-12-10[gas][arm] Set context table for '.arch_extension'Andre Vieira4-0/+20
2019-12-09x86/Intel: fold "xmmword" with "oword"Jan Beulich2-11/+18
2019-12-09x86/Intel: support "mmword ptr"Jan Beulich7-5/+23
2019-12-09x86/Intel: fix "near ptr" / "far ptr" handlingJan Beulich4-3/+24
2019-12-09x86/Intel: drop pointless suffix setting for "tbyte ptr"Jan Beulich2-10/+11
2019-12-09x86/Intel: drop pointless suffix setting for "fword ptr"Jan Beulich2-2/+5
2019-12-09x86/Intel: drop pointless special casing of LxSJan Beulich2-6/+6
2019-12-08aarch64*-*-*ilp32 gas testsAlan Modra14-36/+50
2019-12-06[gas] Implement .cfi_negate_ra_state directiveKyrylo Tkachov4-0/+53
2019-12-05Arm64: simplify Crypto arch extension handlingJan Beulich2-3/+6
2019-12-05Arm64: correct "sha3" arch-extension directive handlingJan Beulich7-45/+49
2019-12-04x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifierJan Beulich9-8/+90
2019-12-04x86-64/Intel: fix CALL/JMP with dword operandJan Beulich4-6/+31
2019-12-04x86: consolidate tracking of MMX register useJan Beulich2-9/+8
2019-12-04x86/Intel: extend MOVDIRI testingJan Beulich7-0/+23
2019-12-04x86: make sure all PUSH/POP honor DefaultSizeJan Beulich4-8/+40
2019-12-04x86: drop some stray/bogus DefaultSizeJan Beulich4-9/+94
2019-11-28gas/riscv: Produce version 3 DWARF CIE by defaultAndrew Burgess6-4/+51
2019-11-28gas: Check for overflow on return column in version 1 CIE DWARFAndrew Burgess5-1/+36
2019-11-28binutils/gas/riscv: Add DWARF register numbers for CSRsAndrew Burgess4-0/+531
2019-11-28gas/riscv: Remove unneeded structureAndrew Burgess2-7/+6
2019-11-25Fix "psb CSYNC" and "bti C".Andrew Pinski7-3/+25
2019-11-25Introduce new section flag: SEC_ELF_OCTETSChristian Eggers6-11/+52
2019-11-25Reverts patches providing octet support in dwarfChristian Eggers4-63/+22
2019-11-22Arm: Change CRC from fpu feature to archititectural extensionMihail Ionescu4-16/+62
2019-11-20PR24944, gas doesn't read enough digits when parsing a floating point numberAlan Modra4-8/+23
2019-11-18gas: Add --gdwarf-cie-version command line flagAndrew Burgess13-2/+125
2019-11-14x86: fold individual Jump* attributes into a single Jump oneJan Beulich3-34/+41
2019-11-14x86: make JumpAbsolute an insn attributeJan Beulich3-21/+45
2019-11-14x86: make AnySize an insn attributeJan Beulich2-1/+5
2019-11-14x86/Intel: correct CMPSD test cases' regexp closing paren placementJan Beulich3-39/+45
2019-11-14x86/Intel: extend MOVSD/CMPSD testsuite coverageJan Beulich10-0/+386
2019-11-12RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive.Jim Wilson2-1/+5
2019-11-12[gas][arm] Enable VLDM, VSTM, VPUSH, VPOP for MVEMihail Ionescu4-44/+131
2019-11-12[binutils][arm] Update the decoding of MVE VMOV, VMVNMihail Ionescu4-2/+94
2019-11-12[gas][arm] Make .fpu reset the FPU/Coprocessor feature bitsMihail Ionescu5-2/+32
2019-11-12x86: fold EsSeg into IsStringJan Beulich2-34/+31
2019-11-12x86: eliminate ImmExt abuseJan Beulich12-352/+343
2019-11-12x86: introduce operand type "instance"Jan Beulich2-29/+55
2019-11-11Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same registerJan Beulich3-0/+10
2019-11-08i386: Only check suffix in instruction mnemonicH.J. Lu6-44/+69
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