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2018-12-19x86: Properly handle PLT expression in directiveH.J. Lu8-3/+34
For PLT expressions, we should subtract the PLT relocation size only for jump instructions. Since PLT relocations are PC relative, we only allow "symbol@PLT" in PLT expression. gas/ PR gas/23997 * config/tc-i386.c (x86_cons): Check for invalid PLT expression. (md_apply_fix): Subtract the PLT relocation size only for jump instructions. * testsuite/gas/i386/reloc32.s: Add test for invalid PLT expression. * testsuite/gas/i386/reloc64.s: Likewise. * testsuite/gas/i386/ilp32/reloc64.s: Likewise. * testsuite/gas/i386/reloc32.l: Updated. * testsuite/gas/i386/reloc64.l: Likewise. * testsuite/gas/i386/ilp32/reloc64.l: Likewise. ld/ PR gas/23997 * testsuite/ld-i386/i386.exp: Run PR gas/23997 test. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-x86-64/pr23997a.s: New file. * testsuite/ld-x86-64/pr23997b.c: Likewise. * testsuite/ld-x86-64/pr23997c.c: Likewise.
2018-12-14elf: Add PT_GNU_PROPERTY segment typeH.J. Lu3-3/+9
Linkers group input note sections with the same name into one output note section with the same name. One output note section is placed in one PT_NOTE segment. New linkers merge all input .note.gnu.property sections into one output .note.gnu.property section with a single NT_GNU_PROPERTY_TYPE_0 note in a single PT_NOTE segment. Since older linkers treat input .note.gnu.property section as a generic note section and just concatenate all input .note.gnu.property sections into one output .note.gnu.property section without merging them, we may see one or more NT_GNU_PROPERTY_TYPE_0 notes in PT_NOTE segment, which are invalid. GNU_PROPERTY_X86_UINT32_VALID was defined to address this issue such that linker sets the bit for non-relocatable outputs. But it isn't sufficient: 1. It doesn't cover generic properties. 2. When -mx86-used-note=yes is passed to x86 assembler, the GNU_PROPERTY_X86_UINT32_VALID bit is set in GNU_PROPERTY_X86_ISA_1_USED property in object file and older linkers generate invalid NT_GNU_PROPERTY_TYPE_0 notes with the GNU_PROPERTY_X86_UINT32_VALID bit set. I am proposing the following changes: 1. Add PT_GNU_PROPERTY segment type: # define PT_GNU_PROPERTY (PT_LOOS + 0x474e553) which covers .note.gnu.property section. 2. Remove GNU_PROPERTY_X86_UINT32_VALID. bfd/ PR ld/23900 * elf.c (get_program_header_size): Add a PT_GNU_PROPERTY segment for NOTE_GNU_PROPERTY_SECTION_NAME. (_bfd_elf_map_sections_to_segments): Create a PT_GNU_PROPERTY segment for NOTE_GNU_PROPERTY_SECTION_NAME. * elfxx-x86.c (_bfd_elf_link_setup_gnu_properties): Don't set GNU_PROPERTY_X86_UINT32_VALID. binutils/ PR ld/23900 * readelf.c (get_segment_type): Support PT_GNU_PROPERTY. (decode_x86_isa): Don't check GNU_PROPERTY_X86_UINT32_VALID. (decode_x86_feature_1): Likewise. (decode_x86_feature_2): Likewise. (print_gnu_property_note): Remove GNU_PROPERTY_X86_UINT32_VALID check. * testsuite/binutils-all/i386/empty.d: Updated. * testsuite/binutils-all/x86-64/empty-x32.d: Likewise. * testsuite/binutils-all/x86-64/empty.d: Likewise. * testsuite/binutils-all/i386/pr21231b.s: Change GNU_PROPERTY_X86_ISA_1_USED bits to 0x7fffffff. * testsuite/binutils-all/x86-64/pr21231b.s: Likewise. gas/ PR ld/23900 * config/tc-i386.c (x86_cleanup): Don't set GNU_PROPERTY_X86_UINT32_VALID. * testsuite/gas/i386/property-1.s: Change GNU_PROPERTY_X86_ISA_1_USED bits to 0. include/ PR ld/23900 * elf/common.h (PT_GNU_PROPERTY): New. (GNU_PROPERTY_X86_UINT32_VALID): Removed. ld/ PR ld/23900 * testsuite/ld-elf/elf.exp: Run PR ld/23900 test. * testsuite/ld-elf/pr23900-1-32.rd: New file. * testsuite/ld-elf/pr23900-1-64.rd: Likewise. * testsuite/ld-elf/pr23900-1.d: Likewise. * testsuite/ld-elf/pr23900-1.s: Likewise. * testsuite/ld-elf/pr23900-2.s: Likewise. * testsuite/ld-elf/pr23900-2a.d: Likewise. * testsuite/ld-elf/pr23900-2b.d: Likewise. * testsuite/ld-i386/ibt-plt-1.d: Adjusted. * testsuite/ld-i386/ibt-plt-2c.d: Likewise. * testsuite/ld-i386/ibt-plt-2d.d: Likewise. * testsuite/ld-i386/ibt-plt-3d.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3c-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3c.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d.d: Likewise. * testsuite/ld-i386/pr23372c.d: Expect <None> for GNU_PROPERTY_X86_ISA_1_USED. * testsuite/ld-x86-64/pr23372c-x32.d: Likewise. * testsuite/ld-x86-64/pr23372c.d: Likewise. * testsuite/ld-x86-64/pr23372d-x32.d: Likewise. * testsuite/ld-x86-64/pr23372d.d: Likewise. * testsuite/ld-x86-64/property-x86-5a.s: Change GNU_PROPERTY_X86_ISA_1_USED bits to 0. * testsuite/ld-x86-64/property-x86-5b.s: Likewise.
2018-12-13Fix typo/thinko in last change.Jeff Law2-1/+6
* dw2gencfi.c (output_cie): Add missing semicolon in last change.
2018-12-13Move aarch64 CIE code to aarch64 backendSam Tebbs4-13/+70
This commit moves all aarch64-specific code to deal with CIE structure introduced in 3a67e1a6b4430374f3073e51bb19347d4c421cfe from target-independent files to the aarch64 backend. 2018-12-13 Sam Tebbs <sam.tebbs@arm.com> binutils/ * dwarf.c (read_cie): Add check for 'B'. gas/ * config/tc-aarch64.h (enum pointer_auth_key, tc_fde_entry_extras, tc_cie_entry_extras, tc_fde_entry_init_extra, tc_output_cie_extra, tc_cie_fde_equivalent_extra, tc_cie_entry_init_extra): Define. * dw2gencfi.c (struct cie_entry): Add tc_cie_entry_extras invocation. (alloc_fde_entry, select_cie_for_fde): Add tc_fde_entry_init_extra invocation. (output_cie): Add tc_output_cie_extra invocation. (select_cie_for_fde): Add tc_cie_fde_equivalent_extra invocation. * dw2gencfi.h (enum pointer_auth_key): Move to config/tc-aarch64.h. (struct fde_entry): Add tc_fde_entry_extras invocation
2018-12-12[GAS][Arm] Skip Local BLX Thumb tests for arm-netbsdelf and arm-ntoAndre Vieira2-1/+6
gas/ChangeLog 2018-12-12 Andre Vieira <andre.simoesdiasvieira@arm.com> * testsuite/gas/arm/blx-local-thumb.d: Skip arm-nto and arm-netbsdelf.
2018-12-10RISC-V: Don't segfault for two regs in auipc or lui.Jim Wilson5-1/+27
gas/ PR gas/23954 * config/tc-riscv.c (my_getSmallExpression): Expand comment for register support. Set expr_end if parse a register. (riscv_ip) <'u'>: Break if imm_expr is not a symbol or constant. * testsuite/gas/riscv/auipc-parsing.d: New. * testsuite/gas/riscv/auipc-parsing.l: New. * testsuite/gas/riscv/auipc-parsing.s: New.
2018-12-10Correct gas/ChangeLog entry for PR gas/23968H.J. Lu1-1/+1
2018-12-09x86: Put back BFD_RELOC_X86_64_GOTPCRELH.J. Lu6-0/+39
Put back BFD_RELOC_X86_64_GOTPCREL in TC_FORCE_RELOCATION_LOCAL, which was removed by commit 56ceb5b5405af23eddd12e12d8ba849010120324 Author: H.J. Lu <hjl.tools@gmail.com> Date: Thu Oct 22 04:49:20 2015 -0700 Add R_X86_64_[REX_]GOTPCRELX support to gas and ld by accident.
2018-12-07RISC-V: Fix 4-arg add parsing.Jim Wilson5-3/+43
PR gas/23956 gas/ * config/tc-riscv.c (validate_riscv_insn) <'1'>: New case. (percent_op_null): New. (riscv_ip) <'j'>: Set imm_reloc before p. <'1'>: New case. <'0'>: Use percent_op_null and don't set imm_reloc. <alu_op>: Handle *args == '1'. * testsuite/gas/riscv/tprel-add.d: New. * testsuite/gas/riscv/tprel-add.l: New. * testsuite/gas/riscv/tprel-add.s: New. opcodes/ * riscv-opc.c (riscv_opcodes) <"add">: Use 1 not 0 for fourth arg.
2018-12-06PowerPC @l, @h and @ha warnings, plus VLE e_liAlan Modra2-33/+61
This patch started off just adding the warnings in tc-ppc.c about incorrect usage of @l, @h and @ha in instructions that don't have 16-bit D-form fields. That unfortunately showed up three warnings in ld/testsuite/ld-powerpc/vle-multiseg.s on instructions like e_li r3, IV_table@l+0x00 which was being assembled to 8: 70 60 00 00 e_li r3,0 a: R_PPC_ADDR16_LO IV_table The ADDR16_LO reloc is of course completely bogus on e_li, which has a split 20-bit signed integer field in bits 0x1f7fff, the low 11 bit in 0x7ff, the next 5 bits in 0x1f0000, and the high 4 bits in 0x7800. Applying an ADDR16_LO reloc to the instruction potentially changes the e_li instruction to e_add2i., e_add2is, e_cmp16i, e_mull2i, e_cmpl16i, e_cmph16i, e_cmphl16i, e_or2i, e_and2i., e_or2is, e_lis, e_and2is, or some invalid encodings. Now there is a relocation that suits e_li, R_PPC_VLE_ADDR20, which was added 2017-09-05 but I can't see code in gas to generate the relocation. In any case, VLE_ADDR20 probably doesn't have the correct semantics for @l since ideally you'd want an @l to pair with @h or @ha to generate a 32-bit constant. Thus @l should only produce a 16-bit value, I think. So we need some more relocations to handle e_li it seems, or as I do in this patch, modify the behaviour of existing relocations when applied to e_li instructions. include/ * opcode/ppc.h (E_OPCODE_MASK, E_LI_MASK, E_LI_INSN): Define. bfd/ * elf32-ppc.c (ppc_elf_howto_raw <R_PPC_VLE_ADDR20>): Correct mask and shift value. (ppc_elf_vle_split16): Use E_OPCODE_MASK. Handle e_li specially. gas/ * config/tc-ppc.c (md_assemble): Adjust relocs for VLE before TLS tweaks. Handle e_li. Warn on unexpected operand field for lo16/hi16/ha16 relocs.
2018-12-06opcodes/riscv: Hide '.L0 ' fake symbolsAndrew Burgess2-2/+8
The RISC-V assembler generates fake labels with the name '.L0 ' as part of the debug information (see gas/config/tc-riscv.h:FAKE_LABEL_NAME). The problem is that currently, when disassembling an object file, the output looks like this (this is an example from the GDB testsuite, but is pretty representative of anything with debug information): 000000000000001e <main>: 1e: 7179 addi sp,sp,-48 20: f406 sd ra,40(sp) 22: f022 sd s0,32(sp) 24: 1800 addi s0,sp,48 0000000000000026 <.L0 >: 26: 87aa mv a5,a0 28: feb43023 sd a1,-32(s0) 2c: fcc43c23 sd a2,-40(s0) 30: fef42623 sw a5,-20(s0) 0000000000000034 <.L0 >: 34: fec42783 lw a5,-20(s0) 38: 0007871b sext.w a4,a5 3c: 678d lui a5,0x3 3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d> 42: 02f71463 bne a4,a5,6a <.L0 > 0000000000000046 <.L0 >: 46: 000007b7 lui a5,0x0 4a: 0007b783 ld a5,0(a5) # 0 <need_malloc> 4e: 6f9c ld a5,24(a5) 0000000000000050 <.L0 >: 50: 86be mv a3,a5 52: 466d li a2,27 54: 4585 li a1,1 56: 000007b7 lui a5,0x0 5a: 00078513 mv a0,a5 5e: 00000097 auipc ra,0x0 62: 000080e7 jalr ra # 5e <.L0 +0xe> 0000000000000066 <.L0 >: 66: 4785 li a5,1 68: a869 j 102 <.L0 > 000000000000006a <.L0 >: 6a: 000007b7 lui a5,0x0 6e: 00078513 mv a0,a5 72: 00000097 auipc ra,0x0 76: 000080e7 jalr ra # 72 <.L0 +0x8> The frequent repeated '.L0 ' labels are pointless, as they are non-unique there's no way to match a use of '.L0 ' to its appearence in the output, so we'd be better off just not printing it at all. That's what this patch does by defining a 'symbol_is_valid' method for RISC-V. With this commit, the same disassembly now looks like this: 000000000000001e <main>: 1e: 7179 addi sp,sp,-48 20: f406 sd ra,40(sp) 22: f022 sd s0,32(sp) 24: 1800 addi s0,sp,48 26: 87aa mv a5,a0 28: feb43023 sd a1,-32(s0) 2c: fcc43c23 sd a2,-40(s0) 30: fef42623 sw a5,-20(s0) 34: fec42783 lw a5,-20(s0) 38: 0007871b sext.w a4,a5 3c: 678d lui a5,0x3 3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d> 42: 02f71463 bne a4,a5,6a <.L4> 46: 000007b7 lui a5,0x0 4a: 0007b783 ld a5,0(a5) # 0 <need_malloc> 4e: 6f9c ld a5,24(a5) 50: 86be mv a3,a5 52: 466d li a2,27 54: 4585 li a1,1 56: 000007b7 lui a5,0x0 5a: 00078513 mv a0,a5 5e: 00000097 auipc ra,0x0 62: 000080e7 jalr ra # 5e <main+0x40> 66: 4785 li a5,1 68: a869 j 102 <.L5> 000000000000006a <.L4>: 6a: 000007b7 lui a5,0x0 6e: 00078513 mv a0,a5 72: 00000097 auipc ra,0x0 76: 000080e7 jalr ra # 72 <.L4+0x8> In order to share the fake label between the assembler and the libopcodes library, I've added some new defines RISCV_FAKE_LABEL_NAME and RISCV_FAKE_LABEL_CHAR in include/opcode/riscv.h. I could have just moved FAKE_LABEL_NAME to the include file, however, I thnk this would be confusing, someone working on the assembler would likely not expect to find FAKE_LABEL_NAME defined outside of the assembler source tree. By introducing the RISCV_FAKE_LABEL_* defines I can leave the assembler standard FAKE_LABEL_ defines in the assembler source, but still share the RISCV_FAKE_LABEL_* with libopcodes. gas/ChangeLog: * config/tc-riscv.h (FAKE_LABEL_NAME): Define as RISCV_FAKE_LABEL_NAME. (FAKE_LABEL_CHAR): Define as RISCV_FAKE_LABEL_CHAR. include/ChangeLog: * dis-asm.h (riscv_symbol_is_valid): Declare. * opcode/riscv.h (RISCV_FAKE_LABEL_NAME): Define. (RISCV_FAKE_LABEL_CHAR): Define. opcodes/ChangeLog: * disassembler.c (disassemble_init_for_target): Add RISC-V initialisation. * riscv-dis.c (riscv_symbol_is_valid): New function.
2018-12-05[aarch64] Add support for pointer authentication B keySam Tebbs7-16/+150
Armv8.3-A has another key used in pointer authentication called the B-key (other than the A-key that is already supported). In order for stack unwinders to work it is necessary to be able to identify frames that have been signed with the B-key rather than the A-key and it was felt that keeping this as an augmentation character in the CIE was the best bet. The DWARF extensions for ARM therefore propose to add a new augmentation character 'B' to the CIE augmentation string and the corresponding cfi directive ".cfi_b_key_frame". I've made the relevant changes to GAS and LD to add support for B-key unwinding, which required modifying LD to check for 'B' in the augmentation string, adding the ".cfi_b_key_frame" directive to GAS and adding a "pauth_key" field to GAS's fde_entry and cie_entry structs. The pointer authentication instructions will behave as NOPs on architectures that don't support them, and so a check for the architecture being assembled for is not necessary since there will be no behavioural difference between augmentation strings with and without the 'B' character on such architectures. 2018-12-05 Sam Tebbs <sam.tebbs@arm.com> bfd/ * elf-eh-frame.c (_bfd_elf_parse_eh_frame): Add check for 'B'. gas/ * dw2gencfi.c (struct cie_entry): Add tc_cie_entry_extras invocation. (alloc_fde_entry): Add tc_fde_entry_init_extra invocation. (output_cie): Add tc_output_cie_extra invocation. (select_cie_for_fde): Add tc_cie_fde_equivalent_extra and tc_cie_entry_init_extra invocation. (frch_cfi_data, cfa_save_data): Move to dwgencfi.h. * config/tc-aarch64.c (s_aarch64_cfi_b_key_frame): Declare. (md_pseudo_table): Add "cfi_b_key_frame". * config/tc-aarch64.h (tc_fde_entry_extras, tc_cie_entry_extras, tc_fde_entry_init_extra, tc_output_cie_extra, tc_cie_fde_equivalent_extra, tc_cie_entry_init_extra): Define. * dw2gencfi.h (struct fde_entry): Add tc_fde_entry_extras invocation. (pointer_auth_key): Define. (frch_cfi_data, cfa_save_data): Move from dwgencfi.c. * doc/c-aarch64.texi (.cfi_b_key_frame): Add documentation. * testsuite/gas/aarch64/(pac_ab_key.d, pac_ab_key.s): New file.
2018-12-04PR23939, Check frch_cfi_data before usewu.heng2-1/+15
PR 23939 * dw2gencfi.c (dot_cfi_label): Check frch_cfi_data is non-NULL before use.
2018-12-03RISC-V: Accept version, supervisor ext and more than one NSE for -march.Jim Wilson29-141/+159
This patch moves all -march parsing logic into bfd, because we will use this code in ELF attributes. bfd/ * elfxx-riscv.h (RISCV_DONT_CARE_VERSION): New macro. (struct riscv_subset_t): New structure. (riscv_subset_t): New typedef. (riscv_subset_list_t): New structure. (riscv_release_subset_list): New prototype. (riscv_add_subset): Likewise. (riscv_lookup_subset): Likewise. (riscv_lookup_subset_version): Likewise. (riscv_release_subset_list): Likewise. * elfxx-riscv.c: Include safe-ctype.h. (riscv_parsing_subset_version): New function. (riscv_supported_std_ext): Likewise. (riscv_parse_std_ext): Likewise. (riscv_parse_sv_or_non_std_ext): Likewise. (riscv_parse_subset): Likewise. (riscv_add_subset): Likewise. (riscv_lookup_subset): Likewise. (riscv_lookup_subset_version): Likewise. (riscv_release_subset_list): Likewise. gas/ * config/tc-riscv.c: Include elfxx-riscv.h. (struct riscv_subset): Removed. (riscv_subsets): Change type to riscv_subset_list_t. (riscv_subset_supports): Removed argument: xlen_required and move logic into libbfd. (riscv_multi_subset_supports): Removed argument: xlen_required. (riscv_clear_subsets): Removed. (riscv_add_subset): Ditto. (riscv_set_arch): Extract parsing logic into libbfd. (riscv_ip): Update argument for riscv_multi_subset_supports and riscv_subset_supports. Update riscv_subsets due to struct definition changed. (riscv_after_parse_args): Update riscv_subsets due to struct definition changed, update and argument for riscv_subset_supports. * testsuite/gas/riscv/empty.s: New. * testsuite/gas/riscv/march-fail-rv32ef.d: Likewise. * testsuite/gas/riscv/march-fail-rv32ef.l: Likewise. * testsuite/gas/riscv/march-fail-rv32i.d: Likewise. * testsuite/gas/riscv/march-fail-rv32i.l: Likewise. * testsuite/gas/riscv/march-fail-rv32iam.d: Likewise. * testsuite/gas/riscv/march-fail-rv32iam.l: Likewise. * testsuite/gas/riscv/march-fail-rv32ic.d: Likewise. * testsuite/gas/riscv/march-fail-rv32ic.l: Likewise. * testsuite/gas/riscv/march-fail-rv32icx2p.d: Likewise. * testsuite/gas/riscv/march-fail-rv32icx2p.l: Likewise. * testsuite/gas/riscv/march-fail-rv32imc.d: Likewise. * testsuite/gas/riscv/march-fail-rv32imc.l: Likewise. * testsuite/gas/riscv/march-fail-rv64I.d: Likewise. * testsuite/gas/riscv/march-fail-rv64I.l: Likewise. * testsuite/gas/riscv/march-fail-rv64e.d: Likewise. * testsuite/gas/riscv/march-fail-rv64e.l: Likewise. * testsuite/gas/riscv/march-ok-g2.d: Likewise. * testsuite/gas/riscv/march-ok-g2p0.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0.d: Likewise. * testsuite/gas/riscv/march-ok-nse-with-version.: Likewise.d * testsuite/gas/riscv/march-ok-s-with-version.d: Likewise. * testsuite/gas/riscv/march-ok-s.d: Likewise. * testsuite/gas/riscv/march-ok-sx.d: Likewise. * testsuite/gas/riscv/march-ok-two-nse.d: Likewise. * testsuite/gas/riscv/march-ok-g2_p1.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise. include/ * opcode/riscv.h (riscv_opcode): Change type of xlen_requirement to unsigned. opcodes/ * riscv-opc.c: Change the type of xlen, because type of xlen_requirement changed.
2018-12-03[aarch64] - Only use MOV for disassembly when shifter op is LSL #0Egeyar Bagcioglu3-2/+16
ARM Architecture Reference Manual for the profile ARMv8-A, Issue C.a, states that MOV (register) is an alias of the ORR (shifted register) iff shift == '00' && imm6 == '000000' && Rn == '11111'. However, mov is currently preferred for a broader range of orr instructions, which is incorrect. 2018-12-03 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com> opcodes: PR 23193 PR 19721 * aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR encoding as MOV if the shift operation is a left shift of zero. gas: PR 23193 PR 19721 * testsuite/gas/aarch64/pr19721.s: Add new test cases. * testsuite/gas/aarch64/pr19721.d: Correct existing test cases and add new ones.
2018-12-03Update the assembler to use a version of 3 when generating the header of the ↵Nick Clifton19-19/+41
.debug_line section. PR 23941 gas * dwarf2dbg.c (DWARF2_LINE_VERSION): Change to 3. * testsuite/gas/elf/dwarf2-3.d: Update expected output. * testsuite/gas/elf/dwarf2-5.d: Likewise. * testsuite/gas/i386/debug1.d: Likewise. * testsuite/gas/i386/dw2-compress-1.d: Likewise. * testsuite/gas/i386/dw2-compress-3a.d: Likewise. * testsuite/gas/i386/dw2-compress-3b.d: Likewise. * testsuite/gas/i386/dw2-compressed-1.d: Likewise. * testsuite/gas/i386/dw2-compressed-3a.d: Likewise. * testsuite/gas/i386/dw2-compressed-3b.d: Likewise. * testsuite/gas/ia64/pr13167.d: Likewise. * testsuite/gas/mips/loc-swap-2.d: Likewise. * testsuite/gas/mips/loc-swap.d: Likewise. * testsuite/gas/mips/micromips@loc-swap-2.d: Likewise. * testsuite/gas/mips/micromips@loc-swap.d: Likewise. * testsuite/gas/mips/mips16@loc-swap-2.d: Likewise. * testsuite/gas/mips/mips16@loc-swap.d: Likewise. * testsuite/gas/mips/mips16e@loc-swap.d: Likewise. binutils* testsuite/binutils-all/i386/compressed-1a.d: Update expected output. * testsuite/binutils-all/x86-64/compressed-1a.d: Likewise.
2018-12-01PR23938, should not free memory alloced in obstack by free()Alan Modra8-44/+67
This removes ineffectual and wrong code caching section names in gas/stabs.c. Code like seg = subseg_new (name, 0); ... if (seg->name == name) seg->name = xstrdup (name); with the idea of being able to unconditionally free "name" later no longer works. "name" is referenced by the section hash table as well as in the section->name field. It would be possible to use "bfd_rename_section (stdoutput, seg, xstrdup (name))", but instead I opted for a fairly straight-forward approach of adding extra parameters to two functions to indicate section name strings should be freed if possible. PR 23938 * read.h (get_stab_string_offset): Update prototype. * stabs.c (get_stab_string_offset): Add free_stabstr_secname parameter. Free stabstr_secname if unused as section name. Don't xstrdup name when used. (s_stab_generic): Remove forward declaration. Add stab_secname_obstack_end param. Reference notes obstack via macros. Delete cached_secname. Adjust get_stab_string_offset call. Free stab_secname if unused as section name. (s_stab): Adjust s_stab_generic call. (s_xstab): Likewise. Delete saved_secname and saved_strsecname. * config/obj-elf.c (obj_elf_init_stab_section): Adjust get_stab_string_offset call. * config/obj-coff.c (obj_coff_init_stab_section): Likewise. * config/obj-som.c (obj_som_init_stab_section): Likewise. * testsuite/gas/all/pr23938.s: New test. * testsuite/gas/all/gas.exp: Run it.
2018-11-30GAS/MIPS: Add `-mfix-r5900' option for the R5900 short loop erratumFredrik Noring9-1/+161
`-march=r5900' already enables the R5900 short loop workaround. However, the R5900 ISA and most other MIPS ISAs are mutually exclusive since R5900-specific instructions are generated as well. The `-mfix-r5900' option can be used in combination with e.g. `-mips2' or `-mips3' to generate generic MIPS binaries that also work with the R5900 target. This change has been tested with `make RUNTESTFLAGS=mips.exp check-gas' for the targets `mipsr5900el-unknown-linux-gnu', `mipsr5900el-elf' and `mips3-unknown-linux-gnu'. gas/ * config/tc-mips.c (mips_fix_r5900, mips_fix_r5900_explicit): New variables. (options): Add OPTION_FIX_R5900 and OPTION_NO_FIX_R5900 enumeration constants. (md_longopts): Add "mfix-r5900" and "mno-fix-r5900" options. (can_swap_branch_p, md_parse_option, mips_after_parse_args): Handle the new options. (md_show_usage): Document the `-mfix-r5900' option. * doc/as.texi: Likewise. * doc/c-mips.texi: Likewise. * testsuite/gas/mips/mips.exp: Run R5900 dump tests. * testsuite/gas/mips/r5900-fix.d: Test `-mfix-r5900' option. * testsuite/gas/mips/r5900-fix.s: Likewise. * testsuite/gas/mips/r5900-no-fix.d: Test `-mno-fix-r5900'. * testsuite/gas/mips/r5900-no-fix.s: Likewise.
2018-11-27RISC-V: Add .insn CA support.Jim Wilson5-13/+65
gas/ * config/tc-riscv.c (validate_riscv_insn) <'F'>: Add support for CF6 and CF2 operands. (riscv_ip) <'F'>: Likewise. * doc/c-riscv.texi (RISC-V-Formats): Add func6 abbreviation. Use rs2 instead of rs1 in CR description. Add CA docs. * gas/testsuite/riscv/insn.s: Add use of .insn ca. * gas/testsuite/riscv/insn.d: Update to match. include/ * opcode/riscv.h (OP_MASK_CFUNCT6, OP_SH_CFUNCT6): New. (OP_MASK_CFUNCT2, OP_SH_CFUNCT2): New. opcodes/ * riscv-opc.c (ciw): Fix whitespace to align columns. (ca): New.
2018-11-27[ARM] Update knowledge of bfd architecturesThomas Preud'homme150-0/+1145
Commit c0c468d562649df0f695737262b6230b7a56a4bb updated bfd's knowledge of Arm architectures to Armv5TEJ and later but missed the list of CPUs recognized by objdump -d -m<cpu>. .note.gnu.arm.ident related code is intentionally not updated as build attributes are a better mechanism to express the ISA in a file. However this patch adds tests for the existing code since no existing testcase cover those codepaths. Since I've only ever managed for bfd_arm_get_mach_from_notes () to have an effect by using objcopy on a file with a note but no Arm build attribute, the tests make use of both objcopy actions supported by run_dump_test which requires to have a ld line as well. Note that the CPU list in bfd/cpu-arm.c was simply copied over from GAS' CPU list but sorted alphabetically as already done for existing entries. 2018-11-27 Thomas Preud'homme <thomas.preudhomme@linaro.org> bfd/ * cpu-arm.c (processors): Add processors known to GAS but missing here and reindent. (bfd_arm_update_notes): Add comment explaining why the list of architectures in the switch should not be updated. (architectures): Likewise. gas/ * testsuite/gas/arm/cpu-arm1020.d: New testcase. * testsuite/gas/arm/cpu-arm1020e.d: Likewise. * testsuite/gas/arm/cpu-arm1020t.d: Likewise. * testsuite/gas/arm/cpu-arm1022e.d: Likewise. * testsuite/gas/arm/cpu-arm1026ej-s.d: Likewise. * testsuite/gas/arm/cpu-arm1026ejs.d: Likewise. * testsuite/gas/arm/cpu-arm10e.d: Likewise. * testsuite/gas/arm/cpu-arm10t.d: Likewise. * testsuite/gas/arm/cpu-arm10tdmi.d: Likewise. * testsuite/gas/arm/cpu-arm1136j-s.d: Likewise. * testsuite/gas/arm/cpu-arm1136jf-s.d: Likewise. * testsuite/gas/arm/cpu-arm1136jfs.d: Likewise. * testsuite/gas/arm/cpu-arm1136js.d: Likewise. * testsuite/gas/arm/cpu-arm1156t2-s.d: Likewise. * testsuite/gas/arm/cpu-arm1156t2f-s.d: Likewise. * testsuite/gas/arm/cpu-arm1176jz-s.d: Likewise. * testsuite/gas/arm/cpu-arm1176jzf-s.d: Likewise. * testsuite/gas/arm/cpu-arm2.d: Likewise. * testsuite/gas/arm/cpu-arm250.d: Likewise. * testsuite/gas/arm/cpu-arm3.d: Likewise. * testsuite/gas/arm/cpu-arm6.d: Likewise. * testsuite/gas/arm/cpu-arm60.d: Likewise. * testsuite/gas/arm/cpu-arm600.d: Likewise. * testsuite/gas/arm/cpu-arm610.d: Likewise. * testsuite/gas/arm/cpu-arm620.d: Likewise. * testsuite/gas/arm/cpu-arm7.d: Likewise. * testsuite/gas/arm/cpu-arm70.d: Likewise. * testsuite/gas/arm/cpu-arm700.d: Likewise. * testsuite/gas/arm/cpu-arm700i.d: Likewise. * testsuite/gas/arm/cpu-arm710.d: Likewise. * testsuite/gas/arm/cpu-arm7100.d: Likewise. * testsuite/gas/arm/cpu-arm710c.d: Likewise. * testsuite/gas/arm/cpu-arm710t.d: Likewise. * testsuite/gas/arm/cpu-arm720.d: Likewise. * testsuite/gas/arm/cpu-arm720t.d: Likewise. * testsuite/gas/arm/cpu-arm740t.d: Likewise. * testsuite/gas/arm/cpu-arm7500.d: Likewise. * testsuite/gas/arm/cpu-arm7500fe.d: Likewise. * testsuite/gas/arm/cpu-arm7d.d: Likewise. * testsuite/gas/arm/cpu-arm7di.d: Likewise. * testsuite/gas/arm/cpu-arm7dm.d: Likewise. * testsuite/gas/arm/cpu-arm7dmi.d: Likewise. * testsuite/gas/arm/cpu-arm7m.d: Likewise. * testsuite/gas/arm/cpu-arm7t.d: Likewise. * testsuite/gas/arm/cpu-arm7tdmi-s.d: Likewise. * testsuite/gas/arm/cpu-arm7tdmi.d: Likewise. * testsuite/gas/arm/cpu-arm8.d: Likewise. * testsuite/gas/arm/cpu-arm810.d: Likewise. * testsuite/gas/arm/cpu-arm9.d: Likewise. * testsuite/gas/arm/cpu-arm920.d: Likewise. * testsuite/gas/arm/cpu-arm920t.d: Likewise. * testsuite/gas/arm/cpu-arm922t.d: Likewise. * testsuite/gas/arm/cpu-arm926ej-s.d: Likewise. * testsuite/gas/arm/cpu-arm926ej.d: Likewise. * testsuite/gas/arm/cpu-arm926ejs.d: Likewise. * testsuite/gas/arm/cpu-arm940t.d: Likewise. * testsuite/gas/arm/cpu-arm946e-r0.d: Likewise. * testsuite/gas/arm/cpu-arm946e-s.d: Likewise. * testsuite/gas/arm/cpu-arm946e.d: Likewise. * testsuite/gas/arm/cpu-arm966e-r0.d: Likewise. * testsuite/gas/arm/cpu-arm966e-s.d: Likewise. * testsuite/gas/arm/cpu-arm966e.d: Likewise. * testsuite/gas/arm/cpu-arm968e-s.d: Likewise. * testsuite/gas/arm/cpu-arm9e-r0.d: Likewise. * testsuite/gas/arm/cpu-arm9e.d: Likewise. * testsuite/gas/arm/cpu-arm9tdmi.d: Likewise. * testsuite/gas/arm/cpu-arm_any.d: Likewise. * testsuite/gas/arm/cpu-cortex-a12.d: Likewise. * testsuite/gas/arm/cpu-cortex-a15.d: Likewise. * testsuite/gas/arm/cpu-cortex-a17.d: Likewise. * testsuite/gas/arm/cpu-cortex-a32.d: Likewise. * testsuite/gas/arm/cpu-cortex-a35.d: Likewise. * testsuite/gas/arm/cpu-cortex-a5.d: Likewise. * testsuite/gas/arm/cpu-cortex-a53.d: Likewise. * testsuite/gas/arm/cpu-cortex-a55.d: Likewise. * testsuite/gas/arm/cpu-cortex-a57.d: Likewise. * testsuite/gas/arm/cpu-cortex-a7.d: Likewise. * testsuite/gas/arm/cpu-cortex-a72.d: Likewise. * testsuite/gas/arm/cpu-cortex-a73.d: Likewise. * testsuite/gas/arm/cpu-cortex-a75.d: Likewise. * testsuite/gas/arm/cpu-cortex-a76.d: Likewise. * testsuite/gas/arm/cpu-cortex-a8.d: Likewise. * testsuite/gas/arm/cpu-cortex-a9.d: Likewise. * testsuite/gas/arm/cpu-cortex-m0.d: Likewise. * testsuite/gas/arm/cpu-cortex-m0plus.d: Likewise. * testsuite/gas/arm/cpu-cortex-m1.d: Likewise. * testsuite/gas/arm/cpu-cortex-m23.d: Likewise. * testsuite/gas/arm/cpu-cortex-m3.d: Likewise. * testsuite/gas/arm/cpu-cortex-m33.d: Likewise. * testsuite/gas/arm/cpu-cortex-m4.d: Likewise. * testsuite/gas/arm/cpu-cortex-m7.d: Likewise. * testsuite/gas/arm/cpu-cortex-r4.d: Likewise. * testsuite/gas/arm/cpu-cortex-r4f.d: Likewise. * testsuite/gas/arm/cpu-cortex-r5.d: Likewise. * testsuite/gas/arm/cpu-cortex-r52.d: Likewise. * testsuite/gas/arm/cpu-cortex-r7.d: Likewise. * testsuite/gas/arm/cpu-cortex-r8.d: Likewise. * testsuite/gas/arm/cpu-ep9312.d: Likewise. * testsuite/gas/arm/cpu-exynos-m1.d: Likewise. * testsuite/gas/arm/cpu-fa526.d: Likewise. * testsuite/gas/arm/cpu-fa606te.d: Likewise. * testsuite/gas/arm/cpu-fa616te.d: Likewise. * testsuite/gas/arm/cpu-fa626.d: Likewise. * testsuite/gas/arm/cpu-fa626te.d: Likewise. * testsuite/gas/arm/cpu-fa726te.d: Likewise. * testsuite/gas/arm/cpu-fmp626.d: Likewise. * testsuite/gas/arm/cpu-i80200.d: Likewise. * testsuite/gas/arm/cpu-iwmmxt.d: Likewise. * testsuite/gas/arm/cpu-iwmmxt2.d: Likewise. * testsuite/gas/arm/cpu-marvell-pj4.d: Likewise. * testsuite/gas/arm/cpu-marvell-whitney.d: Likewise. * testsuite/gas/arm/cpu-mpcore.d: Likewise. * testsuite/gas/arm/cpu-mpcorenovfp.d: Likewise. * testsuite/gas/arm/cpu-sa1.d: Likewise. * testsuite/gas/arm/cpu-strongarm.d: Likewise. * testsuite/gas/arm/cpu-strongarm1.d: Likewise. * testsuite/gas/arm/cpu-strongarm110.d: Likewise. * testsuite/gas/arm/cpu-strongarm1100.d: Likewise. * testsuite/gas/arm/cpu-strongarm1110.d: Likewise. * testsuite/gas/arm/cpu-xgene1.d: Likewise. * testsuite/gas/arm/cpu-xgene2.d: Likewise. * testsuite/gas/arm/cpu-xscale.d: Likewise. * testsuite/gas/arm/nop-asm.s: Likewise. * testsuite/gas/arm/note-march-armv2.d: Likewise. * testsuite/gas/arm/note-march-armv2.s: Likewise. * testsuite/gas/arm/note-march-armv2a.d: Likewise. * testsuite/gas/arm/note-march-armv2a.s: Likewise. * testsuite/gas/arm/note-march-armv3.d: Likewise. * testsuite/gas/arm/note-march-armv3.s: Likewise. * testsuite/gas/arm/note-march-armv3m.d: Likewise. * testsuite/gas/arm/note-march-armv3m.s: Likewise. * testsuite/gas/arm/note-march-armv4.d: Likewise. * testsuite/gas/arm/note-march-armv4.s: Likewise. * testsuite/gas/arm/note-march-armv4t.d: Likewise. * testsuite/gas/arm/note-march-armv4t.s: Likewise. * testsuite/gas/arm/note-march-armv5.d: Likewise. * testsuite/gas/arm/note-march-armv5.s: Likewise. * testsuite/gas/arm/note-march-armv5t.d: Likewise. * testsuite/gas/arm/note-march-armv5t.s: Likewise. * testsuite/gas/arm/note-march-armv5te.d: Likewise. * testsuite/gas/arm/note-march-armv5te.d: Likewise. * testsuite/gas/arm/note-march-ep9312.d: Likewise. * testsuite/gas/arm/note-march-ep9312.s: Likewise. * testsuite/gas/arm/note-march-iwmmxt.d: Likewise. * testsuite/gas/arm/note-march-iwmmxt.s: Likewise. * testsuite/gas/arm/note-march-iwmmxt2.d: Likewise. * testsuite/gas/arm/note-march-iwmmxt2.s: Likewise. * testsuite/gas/arm/note-march-xscale.d: Likewise. * testsuite/gas/arm/note-march-xscale.s: Likewise.
2018-11-27Tighten the constraints for warning about NOPs for the MSP 430 ISA, so NOPs ↵Jozef Lawrynowicz24-71/+751
are only inserted/warned about when needed. Specifically: 430 and 430x ISA require a NOP after DINT. Only the 430x ISA requires NOP before EINT. Only the 430x ISA requires NOP after every EINT. CPU42 errata. * config/tc-msp430.c (is_dint): New. (is_eint): New. (gen_nop): New. (warn_eint_nop): New. (warn_unsure_interrupt): New. (msp430_operands): Determine the effect MOV #N,SR insns have on interrupt state. Only emit NOP warnings for 430 ISA in certain situations. (msp430_md_end): Only warn about an EINT at the end of the file if NOP warnings are enabled. * testsuite/gas/msp430/bad.l: Adjust expected output for new warnings. * testsuite/gas/msp430/msp430.exp: Run new tests. * testsuite/gas/msp430/nop-dint-430.d: New. * testsuite/gas/msp430/nop-dint-430.l: New. * testsuite/gas/msp430/nop-dint-430x-ignore.d: New. * testsuite/gas/msp430/nop-dint-430x-silent.d: New. * testsuite/gas/msp430/nop-dint-430x.d: New. * testsuite/gas/msp430/nop-dint-430x.l: New. * testsuite/gas/msp430/nop-dint.s: New. * testsuite/gas/msp430/nop-eint-430.d: New. * testsuite/gas/msp430/nop-eint-430.l: New. * testsuite/gas/msp430/nop-eint-430x-ignore.d: New. * testsuite/gas/msp430/nop-eint-430x-silent.d: New. * testsuite/gas/msp430/nop-eint-430x.d: New. * testsuite/gas/msp430/nop-eint-430x.l: New. * testsuite/gas/msp430/nop-eint.s: New. * testsuite/gas/msp430/nop-int-430.d: New. * testsuite/gas/msp430/nop-int-430.l: New. * testsuite/gas/msp430/nop-int-430x-silent.d: New. * testsuite/gas/msp430/nop-int-430x.d: New. * testsuite/gas/msp430/nop-int-430x.l: New. * testsuite/gas/msp430/nop-int.s: New.
2018-11-23[GAS][ARM] Fix testism for bl local v4t testAndre Vieira4-1/+61
gas/ChangeLog 2018-11-23 Andre Vieira <andre.simoesdiasvieira@arm.com> * testsuite/gas/arm/bl-local-v4t.d: Remove warning check. * testsuite/gas/arm/blx-local-thumb.s: New. * testsuite/gas/arm/blx-local-thumb.d: New.
2018-11-21S12Z opcodes: Fix bug disassembling certain shift instructions.John Darrington3-1/+10
Shift and rotate instructions when the number of bit positions was an immediate value greater than 1 were incorrectly disassembled. This change fixes that problem and extends the test to check for it. gas/ChangeLog: testsuite/gas/s12z/shift.s: Add new test case. testsuite/gas/s12z/shift.d: Add expected result. opcodes/ChangeLog: s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case if the postbyte matches the appropriate pattern.
2018-11-21S12Z: Add alias instructions BHS and BLO.John Darrington4-2/+14
These are documented by NXP as alternative mnemonics for BCC and BCS respectively. gas/ChangeLog: * config/tc-s12z.c (opcodes): bhs, blo: New members. * testsuite/gas/s12z/bra.d: Add tests for aliases. * testsuite/gas/s12z/bra.s: Add tests for aliases.
2018-11-13[ARM] Improve indentation of ARM architecture declarationsThomas Preud'homme2-51/+55
This commit cleans up indentation of ARM architecture declaration, namely entries of arm_archs and definition of macros ARM_EXT_*, ARM_AEXT_*, ARM_AEXT2_*, FPU_EXT_*, FPU_ARCH_* and ARM_ARCH_*. It also gets rid of unused ARM_ARCH_V6M-ONLY and merge AEM_AEXT_V6M_ONLY in ARM_AEXT_V6M now sole user. gas/ 2018-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (arm_archs): Reindent. include/ 2018-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com> * opcode/arm.h (ARM_AEXT_V6M_ONLY): Merge into its use in ARM_AEXT_V6M. (ARM_ARCH_V6M_ONLY): Remove. (ARM_EXT_V1, ARM_EXT_V2, ARM_EXT_V2S, ARM_EXT_V3, ARM_EXT_V3M, ARM_EXT_V4, ARM_EXT_V4T, ARM_EXT_V5, ARM_EXT_V5T, ARM_EXT_V5ExP, ARM_EXT_V5E, ARM_EXT_V5J, ARM_EXT_V6, ARM_EXT_V6K, ARM_EXT_V8, ARM_EXT_V6T2, ARM_EXT_DIV, ARM_EXT_V5E_NOTM, ARM_EXT_V6_NOTM, ARM_EXT_V7, ARM_EXT_V7A, ARM_EXT_V7R, ARM_EXT_V7M, ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR, ARM_EXT_V6_DSP, ARM_EXT_MP, ARM_EXT_SEC, ARM_EXT_OS, ARM_EXT_ADIV, ARM_EXT_VIRT, ARM_EXT2_PAN, ARM_EXT2_V8_2A, ARM_EXT2_V8M, ARM_EXT2_ATOMICS, ARM_EXT2_V6T2_V8M, ARM_EXT2_FP16_INST, ARM_EXT2_V8M_MAIN, ARM_EXT2_RAS, ARM_EXT2_V8_3A, ARM_EXT2_V8A, ARM_EXT2_V8_4A, ARM_EXT2_FP16_FML, ARM_EXT2_V8_5A, ARM_EXT2_SB, ARM_EXT2_PREDRES, ARM_CEXT_XSCALE, ARM_CEXT_MAVERICK, ARM_CEXT_IWMMXT, ARM_CEXT_IWMMXT2, FPU_ENDIAN_PURE, FPU_ENDIAN_BIG, FPU_FPA_EXT_V1, FPU_FPA_EXT_V2, FPU_MAVERICK, FPU_VFP_EXT_V1xD, FPU_VFP_EXT_V1, FPU_VFP_EXT_V2, FPU_VFP_EXT_V3xD, FPU_VFP_EXT_V3, FPU_NEON_EXT_V1, FPU_VFP_EXT_D32, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA, FPU_VFP_EXT_FMA, FPU_VFP_EXT_ARMV8, FPU_NEON_EXT_ARMV8, FPU_CRYPTO_EXT_ARMV8, CRC_EXT_ARMV8, FPU_VFP_EXT_ARMV8xD, FPU_NEON_EXT_RDMA, FPU_NEON_EXT_DOTPROD, ARM_AEXT_V1, ARM_AEXT_V2, ARM_AEXT_V2S, ARM_AEXT_V3, ARM_AEXT_V3M, ARM_AEXT_V4xM, ARM_AEXT_V4, ARM_AEXT_V4TxM, ARM_AEXT_V4T, ARM_AEXT_V5xM, ARM_AEXT_V5, ARM_AEXT_V5TxM, ARM_AEXT_V5T, ARM_AEXT_V5TExP, ARM_AEXT_V5TE, ARM_AEXT_V5TEJ, ARM_AEXT_V6, ARM_AEXT_V6K, ARM_AEXT_V6Z, ARM_AEXT_V6KZ, ARM_AEXT_V6T2, ARM_AEXT_V6KT2, ARM_AEXT_V6ZT2, ARM_AEXT_V6KZT2, ARM_AEXT_V7_ARM, ARM_AEXT_V7A, ARM_AEXT_V7VE, ARM_AEXT_V7R, ARM_AEXT_NOTM, ARM_AEXT_V6M_ONLY, ARM_AEXT_V6M, ARM_AEXT_V6SM, ARM_AEXT_V7M, ARM_AEXT_V7, ARM_AEXT_V7EM, ARM_AEXT_V8A, ARM_AEXT2_V8A, ARM_AEXT2_V8_1A, ARM_AEXT2_V8_2A, ARM_AEXT2_V8_3A, ARM_AEXT2_V8_4A, ARM_AEXT2_V8_5A, ARM_AEXT_V8M_BASE, ARM_AEXT_V8M_MAIN, ARM_AEXT_V8M_MAIN_DSP, ARM_AEXT2_V8M, ARM_AEXT2_V8M_BASE, ARM_AEXT2_V8M_MAIN, ARM_AEXT2_V8M_MAIN_DSP, ARM_AEXT_V8R, ARM_AEXT2_V8R, FPU_VFP_V1xD, FPU_VFP_V1, FPU_VFP_V2, FPU_VFP_V3D16, FPU_VFP_V3, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4, FPU_VFP_V4_SP_D16, FPU_VFP_V5D16, FPU_VFP_ARMV8, FPU_NEON_ARMV8, FPU_CRYPTO_ARMV8, FPU_VFP_HARD, FPU_FPA, FPU_ARCH_VFP, FPU_ARCH_FPE, FPU_ARCH_FPA, FPU_ARCH_VFP_V1xD, FPU_ARCH_VFP_V1, FPU_ARCH_VFP_V2, FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_NEON_V1, FPU_ARCH_VFP_V3_PLUS_NEON_V1, FPU_ARCH_NEON_FP16, FPU_ARCH_VFP_HARD, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16, FPU_ARCH_VFP_V4_SP_D16, FPU_ARCH_VFP_V5D16, FPU_ARCH_VFP_V5_SP_D16, FPU_ARCH_NEON_VFP_V4, FPU_ARCH_VFP_ARMV8, FPU_ARCH_NEON_VFP_ARMV8, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD, ARCH_CRC_ARMV8, FPU_ARCH_NEON_VFP_ARMV8_1, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1, FPU_ARCH_DOTPROD_NEON_VFP_ARMV8, ARM_ARCH_V1, ARM_ARCH_V2, ARM_ARCH_V2S, ARM_ARCH_V3, ARM_ARCH_V3M, ARM_ARCH_V4xM, ARM_ARCH_V4, ARM_ARCH_V4TxM, ARM_ARCH_V4T, ARM_ARCH_V5xM, ARM_ARCH_V5, ARM_ARCH_V5TxM, ARM_ARCH_V5T, ARM_ARCH_V5TExP, ARM_ARCH_V5TE, ARM_ARCH_V5TEJ, ARM_ARCH_V6, ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6KZ, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, ARM_ARCH_V6KZT2, ARM_ARCH_V6M, ARM_ARCH_V6SM, ARM_ARCH_V7, ARM_ARCH_V7A, ARM_ARCH_V7VE, ARM_ARCH_V7R, ARM_ARCH_V7M, ARM_ARCH_V7EM, ARM_ARCH_V8A, ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A, ARM_ARCH_V8_3A, ARM_ARCH_V8_4A, ARM_ARCH_V8_5A, ARM_ARCH_V8M_BASE, ARM_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN_DSP, ARM_ARCH_V8R): Reindent.
2018-11-12[BINUTILS, AARCH64, 8/8] Add data cache instructions for Memory Tagging ↵Sudakshina Das4-0/+68
Extension This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch adds all the data cache instructions that are part of this extension: - DC IGVAC, Xt - DC IGSW, Xt - DC CGSW, Xt - DC CIGSW, Xt - DC CGVAC, Xt - DC CGVAP, Xt - DC CGVADP, Xt - DC CIGVAC, Xt - DC GVA, Xt - DC IGDVAC, Xt - DC IGDSW, Xt - DC CGDSW, Xt - DC CIGDSW, Xt - DC CGDVAC, Xt - DC CGDVAP, Xt - DC CGDVADP, Xt - DC CIGDVAC, Xt - DC GZVA, Xt *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_sys_regs_dc): New entries for IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA, IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP, CIGDVAC and GZVA. (aarch64_sys_ins_reg_supported_p): New check for above. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/sysreg-4.s: Test IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA, IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP, CIGDVAC and GZVA with DC. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 7/8] Add system registers for Memory Tagging ExtensionSudakshina Das4-1/+75
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch adds all the system registers that are part of this extension and are accessible via the MRS/MSR instructions: - TCO - TFSRE0_SL1 - TFSR_EL1 - TFSR_EL2 - TFSR_EL3 - TFSR_EL12 - RGSR_EL1 - GCR_EL1 TCO is also accessible with the MSR(immediate) instruction. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_sys_regs): New entries for TCO, TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, RGSR_EL1 and GCR_EL1. (aarch64_sys_reg_supported_p): New check for above. (aarch64_pstatefields): New entry for TCO. (aarch64_pstatefield_supported_p): New check for above. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/sysreg-4.s: Test TCO, TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, RGSR_EL1 and GCR_EL1 MSR and MRS. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das6-3/+70
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Bulk Allocation Tag instructions from MTE. These are the following instructions added in this patch: - LDGV <Xt>, [<Xn|SP>]! - STGV <Xt>, [<Xn|SP>]! This needed a new kind of operand for the new addressing [<Xn|SP>]! since this has no offset and only takes a pre-indexed version. Hence AARCH64_OPND_ADDR_SIMPLE_2 and ldtdgv_indexed are introduced. (AARCH64_OPND_ADDR_SIMPLE fulfilled the no offset criteria but does not allow writeback). We also needed new encoding and decoding functions to be able to do the same. where <Xt> : Is the 64-bit destination GPR. <Xn|SP> : Is the 64-bit first source GPR or Stack pointer. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2. (aarch64_insn_class): Add ldstgv_indexed. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-asm.c (aarch64_ins_addr_simple_2): New. * aarch64-asm.h (ins_addr_simple_2): Declare the above. * aarch64-dis.c (aarch64_ext_addr_simple_2): New. * aarch64-dis.h (ext_addr_simple_2): Declare the above. * aarch64-opc.c (operand_general_constraint_met_p): Add case for AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed. (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2. * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv. (AARCH64_OPERANDS): Define ADDR_SIMPLE_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it. (warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv and stgv. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 5/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das5-1/+33
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Tag Getting instruction from Memory Tagging Extension. - LDG <Xt>, [<Xn|SP>, #<simm>] where <Xt> : Is the 64-bit destination GPR. <Xn|SP> : Is the 64-bit first source GPR or Stack pointer. <simm> : Is the optional signed immediate offset, a multiple of 16 in the range of -4096 and 4080, defaulting to 0. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-tbl.h (QL_LDG): New. (aarch64_opcode_table): Add ldg. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldg. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging ↵Sudakshina Das6-0/+140
Extension This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Tag setting instructions from MTE which consists of the following instructions: - STG [<Xn|SP>, #<simm>] - STG [<Xn|SP>, #<simm>]! - STG [<Xn|SP>], #<simm> - STZG [<Xn|SP>, #<simm>] - STZG [<Xn|SP>, #<simm>]! - STZG [<Xn|SP>], #<simm> - ST2G [<Xn|SP>, #<simm>] - ST2G [<Xn|SP>, #<simm>]! - ST2G [<Xn|SP>], #<simm> - STZ2G [<Xn|SP>, #<simm>] - STZ2G [<Xn|SP>, #<simm>]! - STZ2G [<Xn|SP>], #<simm> - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>] - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]! - STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm> where <Xn|SP> : Is the 64-bit GPR or Stack pointer. <simm> : Is the optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data for AARCH64_OPND_QLF_imm_tag. (operand_general_constraint_met_p): Add case for AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New. (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp for both offset and pre/post indexed versions. (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (fix_insn): Likewise. (warn_unpredictable_ldst): Exempt STGP. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g, stzg, stz2g and stgp. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instructions in Memory ↵Sudakshina Das5-0/+66
Tagging Extension This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Pointer Arithmetic instructions from MTE. These are the following instructions added in this patch: - SUBP <Xd>, <Xn|SP>, <Xm|SP> - SUBPS <Xd>, <Xn|SP>, <Xm|SP> - CMPP <Xn|SP>, <Xm|SP> where CMPP is an alias to SUBPS XZR, <Xn|SP>, <Xm|SP> where <Xd> : Is the 64-bit destination GPR. <Xn|SP> : Is the 64-bit first source GPR or Stack pointer. <Xm|SP> : Is the 64-bit second source GPR or Stack pointer. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for subp, subps and cmpp. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging ↵Sudakshina Das7-0/+120
Extension This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Tag generation instructions from MTE. These are the following instructions added in this patch: - IRG <Xd|SP>, <Xn|SP>{, Xm} - ADDG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2> - SUBG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2> - GMI <Xd>, <Xn|SP>, <Xm> where <Xd|SP> : Is the 64-bit destination GPR or Stack pointer. <Xn|SP> : Is the 64-bit source GPR or Stack pointer. <uimm6> : Is the unsigned immediate, a multiple of 16 in the range 0 to 1008. <uimm4> : Is the unsigned immediate, in the range 0 to 15. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3. (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New. * aarch64-opc.c (fields): Add entry for imm4_3. (operand_general_constraint_met_p): Add cases for AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_ADDG): New. (aarch64_opcode_table): Add addg, subg, irg and gmi. (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10. * aarch64-asm.c (aarch64_ins_imm): Add case for operand_need_shift_by_four. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10. * testsuite/gas/aarch64/armv8_5-a-memtag.s: New. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.d: Likewise.
2018-11-12[BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-ASudakshina Das3-0/+10
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions. Memory Tagging Extension is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch adds the new command line option and the new feature macros. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-tbl.h (aarch64_feature_memtag): New. (MEMTAG, MEMTAG_INSN): New. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_features): Add "memtag" as a new option. * doc/c-aarch64.texi: Document the same.
2018-11-09S/390: Fix optional operand handling after memory addressesAndreas Krebbel4-24/+42
Instructions having an optional argument following a memory address operand were not handled correctly if the optional argument was not specified. gas/ChangeLog: 2018-11-09 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (skip_optargs_p): New function. (md_gather_operands): Use skip_optargs_p. * testsuite/gas/s390/s390.exp: Run the new test. * testsuite/gas/s390/zarch-optargs.d: New test. * testsuite/gas/s390/zarch-optargs.s: New test.
2018-11-09PowerPC, don't use bfd reloc howto in md_assembleAlan Modra2-11/+255
We support source like the following .data .quad x-. .space 8 x: where at the time the .quad line is assembled, x is unknown so a fixup is emitted for later evaluation. This is supported for data even when the target may not have relocations for the expression, for example, 32-bit powerpc targets lack a 64-bit reloc. As long as the fixup resolves at assembly time, gas is happy. The idea of this patch is to support fixups that resolve at assembly time for instructions too, even when the target might lack the necessary relocations (and thus no howto). * config/tc-ppc.c (fixup_size): New function. (md_assemble): Use it to derive size and pcrel directly from fixup reloc type.
2018-11-07Add updated French and Portuguese translations.Nick Clifton2-2994/+3076
gas * po/fr.po: Updated French translation. bfd * po/fr.po: Updated French translation. * po/pt.po: Updated Portuguese translation. binutils* po/pt.po: Updated Portuguese translation.
2018-11-07rx: Add target rx-*-linux.Yoshinori Sato5-2/+13
2018-11-06[arm] fix testsuite breakage on pe-coffMatthew Malcomson2-2/+8
The PE target can insert NOP's for padding to 4 byte alignment. This was causing a testcase failure, this commit fixes the testcase. This commit also escapes some full-stops in the testcase regexp. 2018-11-06 Matthew Malcomson <matthew.malcomson@arm.com> * testsuite/gas/arm/neon-cond-bad_t2.d: Fix testcase for PE target.
2018-11-06[arm] Check for neon and condition in vcvt.f16.f32Matthew Malcomson7-14/+40
VCVT between f16 and f32 is an Advanced SIMD instruction. Not all the VCVT alternatives need neon, hence the check for neon is in the encode function. The check on neon for VCVT.f16.f32 (and vice versa) is missing. vshcmd: > echo 'vcvt.f16.f32 d1, q1' | gas/as-new -mfpu=vfpxd -march=armv8.5-a - testdir [15:59:10] $ Also, the handling of the condition code behaves differently to other SIMD instructions -- no error message is produced when assembling an instruction with a condition code suffix despite the arm encoding not allowing a condition code. (n.b. the actual binary produced is independent of the suffix). The instruction should be treated similarly to VSUBL that has the same caveat of "must be unconditional" describing the {<c>} symbol. vcvt half-precision to single precision found in F6.1.58 in the ARM Architecture Reference Manual issue C.a, vsubl found in F6.1.240 in the ARM Architecture Reference Manual issue C.a 2018-11-06 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (do_neon_cvt_1): Add check for neon and condition codes to half-precision conversion. * testsuite/gas/arm/neon-cond-bad-inc.s: Check vcvteq disallowed. * testsuite/gas/arm/neon-cond-bad.l: Likewise. * testsuite/gas/arm/neon-cond-bad_t2.d: Check vcvteq allowed in IT block. * testsuite/gas/arm/vfp-bad.l: Ensure vcvt doesn't work without neon. * testsuite/gas/arm/vfp-bad.s: Likewise.
2018-11-06PowerPC instruction mask checksAlan Modra2-14/+29
The instruction mask bits should never overlap any of the operands, nor should operand bits overlap, but some operands weren't checked. This patch arranges to check the omitted operands, using a mask returned by the operand->insert function. Some tweaking of various insert functions is needed to support this: The error case must set field bits. Since I was looking at the insert functions, I tidied some dead code and simplified some of the powerpc_operands entries. gas/ * config/tc-ppc.c (insn_validate): Don't ignore mask in PPC_OPSHIFT_INV case. Call the insert function to calculate a mask. opcodes/ * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls), (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0), (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16), (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd): Don't return zero on error, insert mask bits instead. (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete. (insert_sh6, extract_sh6): Delete dead code. (insert_sprbat, insert_sprg): Use unsigned comparisions. (powerpc_operands <OIMM>): Set shift count rather than using PPC_OPSHIFT_INV. <SE_SDH, SE_SDW>: Likewise. Don't use insert/extract functions.
2018-11-06PowerPC instruction operand flag validationAlan Modra2-0/+14
This adds another check that might have saved me a little time recently if it had been present. * config/tc-ppc.c (insn_validate): Check that optional operands are not followed by non-optional operands.
2018-11-06x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit modeJan Beulich4-0/+10
For the flavor having a GPR operand EVEX.W is ignored outside of 64-bit mode. The mnemonic should therefore not be VPBROADCASTQ.
2018-11-06x86: correctly handle VMOVD with EVEX.W set outside of 64-bit modeJan Beulich4-0/+20
For the flavors having a GPR operand EVEX.W is ignored outside of 64-bit mode. The mnemonic should therefore not be KMOVQ, the GPR operand should not name a non-existing 64-bit register, just like is already the case for the AVX counterparts, and the Disp8 scaling factor should be 4 rather than 8.
2018-11-06x86: correctly handle KMOVD with VEX.W set outside of 64-bit modeJan Beulich3-0/+9
For the flavors having a GPR operand VEX.W is ignored outside of 64-bit mode. The mnemonic should therefore not be KMOVQ.
2018-11-06x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich8-0/+60
PEXTR{B,W} and PINSR{B,W}, just like for AVX512BW, are WIG, no matter that the SDM uses a nonstandard description of that fact. PEXTRD, even with EVEX.W set, ignores that bit outside of 64-bit mode, just like its AVX counterpart.
2018-11-06x86: adjust {,E}VEX.W handling outside of 64-bit modeJan Beulich13-31/+241
Many VEX-/EVEX-encoded instructions accessing GPRs become WIG outside of 64-bit mode. The respective templates should specify neither VexWIG nor VexW0, but instead the setting of the bit should be determined from - REX.W in 64-bit mode, - the setting established through -mvexwig= / -mevexwig= otherwise. This implies that the evex-wig2 testcase needs to go away, as being wrong altogether. A few test additions desirable here will only happen in later patches, as the disassembler needs adjustments first. Once again SSE2AVX templates are left alone, for it being unclear what the behavior there should be.
2018-11-06x86: fix various non-LIG templatesJan Beulich10-0/+433
Quite a few templates were marked LIG while really the insns aren't. Introduce descriptive shorthands once again, instead of continuing to use the less legible original forms.
2018-11-06x86: allow {store} to select alternative {,}PEXTRW encodingJan Beulich5-2/+51
The 0F C5 encoding is indeed a load type one (just that memory operands are not permitted), while the 0F 3A 15 encoding is obviously a store. Allow the pseudo prefixes to be used to select between them. Also move (without any change) the secondary AVX512BW templates next to the primary one.
2018-11-06x86: add more VexWIGJan Beulich9-18/+70
Commits 6865c0435a ("x86: Support VEX/EVEX WIG encoding") and 6fa52824c3 ("x86: Replace VexW=3 with VexWIG") omitted quite a few templates, oddly enough in some cases despite testcases getting added (which then were recorded with wrong expected output). Also adjust VPMAXUB's attributes in the AVX512BW case to match ordering of that of neighboring templates. For the moment SSE2AVX templates are left alone, as it isn't clear whether they were intentionally left untouched by the original commits (the descriptions don't say either way). In this context I question the decision in commit 0375113302 ("x86: Add -mvexwig=[0|1] option to assembler") to move the logic to determine the value of the W bit ahead of the decision whether to use 2-byte VEX: While I can see this as one possible interpretation of -mvexwig=, the other alternative (setting the value of the bit only if it actually exists in the encoding) looks as reasonable to me, and perhaps even more in line with us generally trying to pick the shortest encoding.
2018-11-05Correct ChangeLog entries for PR gas/23854 commitH.J. Lu1-1/+1
commit e60f4d3bdac25f02875afe36b7436bc2dfbbb978 Author: H.J. Lu <hjl.tools@gmail.com> Date: Mon Nov 5 09:01:26 2018 -0800 x86: Disable GOT relaxation with data prefix Since linker GOT relaxation isn't valid for 16-bit GOT access, we should disable GOT relaxation with data prefix.
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