Age | Commit message (Expand) | Author | Files | Lines |
2016-11-04 | Update RISC-V documentation and make sure that it is included in the gas info... | Palmer Dabbelt | 6 | -4/+32 |
2016-11-03 | [ARC] Fix ldbit test on 32-bit systems | Graham Markall | 3 | -7/+13 |
2016-11-03 | arc: Implement NPS-400 dcmac instruction | Graham Markall | 3 | -0/+100 |
2016-11-03 | arc: Change max instruction length to 64-bits | Andrew Burgess | 2 | -125/+44 |
2016-11-03 | arc: Replace ARC_SHORT macro with arc_opcode_len function | Graham Markall | 2 | -2/+9 |
2016-11-03 | gas/arc: Replace short_insn flag with insn length field | Graham Markall | 2 | -45/+27 |
2016-11-04 | New option falkor for Qualcomm server part | Siddhesh Poyarekar | 5 | -0/+15 |
2016-11-03 | X86: Decode opcode 0x82 as opcode 0x80 in 32-bit mode | H.J. Lu | 4 | -0/+32 |
2016-11-03 | [ARM] Allow MOV/MOV.W to accept all possible immediates | Jiong Wang | 10 | -17/+108 |
2016-11-02 | Enable Intel AVX512_4VNNIW instructions | Igor Tsimbalist | 16 | -2/+762 |
2016-11-02 | Enable Intel AVX512_4FMAPS instructions | Igor Tsimbalist | 24 | -3/+1124 |
2016-11-01 | Add support for RISC-V architecture. | Nick Clifton | 16 | -7/+2667 |
2016-10-27 | gas/arc: Don't rely on bfd list of cpu type for cpu selection | Andrew Burgess | 3 | -91/+131 |
2016-10-26 | Revert "bison warning fixes" | Alan Modra | 3 | -2/+8 |
2016-10-21 | X86: Remove pcommit instruction | H.J. Lu | 10 | -84/+13 |
2016-10-20 | Check invalid mask registers | H.J. Lu | 4 | -0/+30 |
2016-10-19 | [GAS][ARM]Generate unpredictable warning for pc used in data processing instr... | Renlin Li | 5 | -0/+103 |
2016-10-17 | Fixed matching in newly added test. | Cupertino Miranda | 2 | -1/+5 |
2016-10-17 | Removed pseudo invalid instructions opcodes. | Cupertino Miranda | 3 | -0/+21 |
2016-10-14 | [ARC] Disassembler: fix LIMM detection for short instructions. | Claudiu Zissulescu | 5 | -0/+47 |
2016-10-11 | Enhance objdump so that it will use .got, .plt and .plt.got section symbols w... | Nick Clifton | 2 | -2/+6 |
2016-10-11 | [AArch64] PR target/20666, fix wrong encoding of new introduced BFC pseudo | Jiong Wang | 2 | -17/+22 |
2016-10-10 | MIPS64: Adjust cfi* testcases. | Andreas Krebbel | 10 | -17/+29 |
2016-10-08 | Auto-generated dependencies for rx-parse.o and rl78-parse.o | Alan Modra | 3 | -27/+22 |
2016-10-07 | [AArch64] PR target/20667, fix disassembler for the "special" optional SYS_Rt... | Jiong Wang | 3 | -0/+162 |
2016-10-06 | [ARC] Fix parsing leave_s and enter_s mnemonics. | Claudiu Zissulescu | 6 | -2/+68 |
2016-10-06 | -Wimplicit-fallthrough dodgy fixes | Alan Modra | 3 | -4/+9 |
2016-10-06 | Refine .cfi_sections check to only consider compact eh_frame | Matthew Fortune | 5 | -1/+42 |
2016-10-06 | -Wimplicit-fallthrough warning fixes | Alan Modra | 37 | -18/+193 |
2016-10-06 | -Wimplicit-fallthrough noreturn fixes | Alan Modra | 2 | -1/+5 |
2016-10-06 | -Wimplicit-fallthrough error fixes | Alan Modra | 9 | -10/+28 |
2016-10-06 | bison warning fixes | Alan Modra | 3 | -2/+7 |
2016-09-30 | [AArch64] PR target/20553, fix opcode mask for SIMD multiply by element | Jiong Wang | 3 | -0/+22 |
2016-09-29 | Add .cfi_val_offset GAS command. | Andreas Krebbel | 6 | -0/+76 |
2016-09-29 | Disallow 3-operand cmp[l][i] for ppc64 | Alan Modra | 4 | -4/+12 |
2016-09-26 | tc-xtensa.c: fixup xg_reverse_shift_count typo | Trevor Saunders | 2 | -1/+6 |
2016-09-26 | When building target binaries, ensure that the warning flags selected for the... | Vlad Zakharov | 4 | -6/+58 |
2016-09-26 | PowerPC .gnu.attributes | Alan Modra | 2 | -0/+29 |
2016-09-22 | Remove legacy basepri_mask MRS/MSR special reg | Thomas Preud'homme | 2 | -1/+5 |
2016-09-21 | [AArch64] Print spaces after commas in addresses | Richard Sandiford | 16 | -9612/+9633 |
2016-09-21 | [AArch64] Use "must" rather than "should" in error messages | Richard Sandiford | 6 | -80/+90 |
2016-09-21 | [AArch64] Add SVE condition codes | Richard Sandiford | 11 | -69/+228 |
2016-09-21 | Fix misplaced ChangeLog | Richard Sandiford | 2 | -11/+15 |
2016-09-21 | [AArch64][SVE 32/32] Add SVE tests | Richard Sandiford | 15 | -0/+79428 |
2016-09-21 | [AArch64][SVE 31/32] Add SVE instructions | Richard Sandiford | 3 | -1/+27 |
2016-09-21 | [AArch64][SVE 29/32] Add new SVE core & FP register operands | Richard Sandiford | 2 | -0/+11 |
2016-09-21 | [AArch64][SVE 28/32] Add SVE FP immediate operands | Richard Sandiford | 2 | -3/+44 |
2016-09-21 | [AArch64][SVE 27/32] Add SVE integer immediate operands | Richard Sandiford | 2 | -0/+32 |
2016-09-21 | [AArch64][SVE 26/32] Add SVE MUL VL addressing modes | Richard Sandiford | 2 | -15/+68 |
2016-09-21 | [AArch64][SVE 25/32] Add support for SVE addressing modes | Richard Sandiford | 2 | -23/+237 |