| Age | Commit message (Collapse) | Author | Files | Lines |
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On further reading of ISA manual it appears gas should have been
treating mftb and mftbu as extended mnemonics for mfspr, for ISA 2.03
and later.
opcodes/
* ppc-opc.c (powerpc_opcodes): Make mftb* generate mfspr for
power4 and later.
gas/testsuite/
* gas/ppc/a2.d: Update for mftb change.
* gas/ppc/476.d: Likewise.
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2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
include/opcode/
* nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
(NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
(NIOS2_INSN_OPTARG): Renumber.
opcodes/
* nios2-opc.c (nios2_r1_opcodes): Remove deleted attributes
from descriptors.
gas/
* config/tc-nios2.c (can_evaluate_expr, get_expr_value): Delete.
(output_addi, output_andi, output_ori, output_xori): Delete.
(md_assemble): Remove calls to deleted functions.
gas/testsuite/
* gas/nios2/nios2.exp: Make "movi" a list test.
* gas/nios2/movi.s: Adjust comments, add another case.
* gas/nios2/movi.l: New.
* gas/nios2/movi.d: Delete.
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For conditional branches that need more than one trampoline to reach its
target assembler couldn't always find suitable trampoline because
post-loop condition check was placed inside the loop, resulting in
premature loop termination. Move check outside the loop.
This fixes the following build errors seen when assembling huge files
produced by gcc:
Error: jump target out of range; no usable trampoline found
Error: operand 1 of 'j' has out of range value '307307'
2014-11-25 Max Filippov <jcmvbkbc@gmail.com>
gas/
* config/tc-xtensa.c (search_trampolines): Move post-loop
condition check outside the search loop.
gas/testsuite/
* gas/xtensa/trampoline.d: Add expected output for branches.
* gas/xtensa/trampoline.s: Add test case for branches.
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* libtool.m4: Updated from GCC trunk.
bfd/
* configure: Regenerated.
binutils/
* configure: Regenerated.
gas/
* configure: Regenerated.
gprof/
* configure: Regenerated.
ld/
* configure: Regenerated.
opcodes/
* configure: Regenerated.
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gas/
2014-11-21 Terry Guo <terry.guo@arm.com>
* config/tc-arm.c (md_assemble): Do not consider relaxation.
(md_convert_frag): Test and set target arch attribute accordingly.
(aeabi_set_attribute_string): Turn it into a global function.
* config/tc-arm.h (md_post_relax_hook): Enable it for ARM target.
(aeabi_set_public_attributes): Declare it.
gas/testsuite/
2014-11-21 Terry Guo <terry.guo@arm.com>
* gas/arm/attr-arch-assumption.d: New file.
* gas/arm/attr-arch-assumption.s: Likewise.
ld/testsuite/
2014-11-21 Terry Guo <terry.guo@arm.com>
* ld-arm/tls-longplt-lib.s: Require ARMv6T2.
* ld-arm/tls-longplt.s: Likewise.
* ld-arm/tls-longplt-lib.d: Updated.
* ld-arm/tls-longplt.d: Likewise.
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include/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* opcode/arm.h (FPU_VFP_EXT_ARMV8xD): New macro.
(FPU_VFP_V5D16): Likewise.
(FPU_VFP_V5_SP_D16): Likewise.
(FPU_ARCH_VFP_V5D16): Likewise.
(FPU_ARCH_VFP_V5_SP_D16): Likewise.
bfd/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Support FPv5.
binutils/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* readelf.c (arm_attr_tag_FP_arch): Extended to support FPv5.
gas/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* config/tc-arm.c (fpu_vfp_ext_armv8xd): New.
(arm_cpus): Support cortex-m7.
(arm_fpus): Support fpv5-sp-d16 and fpv5-d16.
(do_vfp_nsyn_cvt_fpv8): Generate error when use D register for S
register only target like FPv5-SP-D16.
(do_neon_cvttb_1): Likewise.
(do_vfp_nsyn_fpv8): Likewise.
(do_vrint_1): Likewise.
(aeabi_set_public_attributes): Set proper FP arch for FPv5.
* doc/c-arm.texi: Document new cpu and fpu names for cortex-m7.
gas/testsuite/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* gas/arm/armv7e-m+fpv5-d16.s: New.
* gas/arm/armv7e-m+fpv5-d16.d: Likewise.
* gas/arm/armv7e-m+fpv5-sp-d16.s: Likewise.
* gas/arm/armv7e-m+fpv5-sp-d16.d: Likewise.
ld/testsuite/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* ld-arm/attr-merge-vfp-4-sp.s: New test source file.
* ld-arm/attr-merge-vfp-5-sp.s: Likewise.
* ld-arm/attr-merge-vfp-5.s: Likewise.
* ld-arm/attr-merge-vfp-8.d: New test.
* ld-arm/attr-merge-vfp-8r.d: Likewise.
* ld-arm/attr-merge-vfp-9.d: Likewise.
* ld-arm/attr-merge-vfp-9r.d: Likewise.
* ld-arm/attr-merge-vfp-10.d: Likewise.
* ld-arm/attr-merge-vfp-10r.d: Likewise.
* ld-arm/attr-merge-vfp-11.d: Likewise.
* ld-arm/attr-merge-vfp-11r.d: Likewise.
* ld-arm/attr-merge-vfp-12.d: Likewise.
* ld-arm/attr-merge-vfp-12r.d: Likewise.
* ld-arm/attr-merge-vfp-13.d: Likewise.
* ld-arm/attr-merge-vfp-13r.d: Likewise.
* ld-arm/attr-merge-vfp-14.d: Likewise.
* ld-arm/attr-merge-vfp-14r.d: Likewise.
* ld-arm/arm-elf.exp: Run the new tests.
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* config/tc-aarch64.c (warn_unpredictable_ldst): Check that transfer
registers are in the GP register set. Adjust warnings. Use correct
field member for address register.
* testsuite/gas/aarch64/diagnostic.l: Update.
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2014-11-19 Ryan Mansfield <rmansfield@qnx.com>
* config/tc-aarch64.c (md_assemble): Call warn_unpredictable_ldst.
(warn_unpredictable_ldst): New.
2014-11-19 Ryan Mansfield <rmansfield@qnx.com>
* gas/aarch64/diagnostic.s: Add new warnings test patterns.
* gas/aarch64/diagnostic.l: Update expected diagnostic output.
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This patch adds "-z bndplt" option Linux/x86-64 linker to generate BND
prefix in PLT entries. It also updated Linux/x86-64 assembler not to
generate R_X86_64_PLT32_BND nor R_X86_64_PC32_BND relocations.
bfd/
2014-11-18 Igor Zamyatin <igor.zamyatin@intel.com>
* elf64-x86-64.c (elf_x86_64_check_relocs): Enable MPX PLT only
for -z bndplt.
gas/
2014-11-18 Igor Zamyatin <igor.zamyatin@intel.com>
* config/tc-i386-intel.c (i386_operator): Remove last argument
from lex_got call.
* config/tc-i386.c (reloc): Remove bnd_prefix from parameters'
list. Return always BFD_RELOC_32_PCREL.
* (output_branch): Remove condition for BFD_RELOC_X86_64_PC32_BND.
* (output_jump): Update call to reloc accordingly.
* (output_interseg_jump): Likewise.
* (output_disp): Likewise.
* (output_imm): Likewise.
* (x86_cons_fix_new): Likewise.
* (lex_got): Remove bnd_prefix from parameters' list in macro and
declarations. Don't use BFD_RELOC_X86_64_PLT32_BND.
* (x86_cons): Update call to lex_got accordingly.
* (i386_immediate): Likewise.
* (i386_displacement): Likewise.
* (md_apply_fix): Don't use BFD_RELOC_X86_64_PLT32_BND nor
BFD_RELOC_X86_64_PC32_BND.
* (tc_gen_reloc): Likewise.
include/
2014-11-18 Igor Zamyatin <igor.zamyatin@intel.com>
* bfdlink.h (struct bfd_link_info): Add bndplt.
ld/
2014-11-18 Igor Zamyatin <igor.zamyatin@intel.com>
* emulparams/elf_x86_64.sh (BNDPLT): Set to yes for x86_64.
* emultempl/elf32.em (gld${EMULATION_NAME}_handle_option): Handle
"-z bndplt" if BNDPLT is yes.
(gld${EMULATION_NAME}_list_options): Add "-z bndplt" entry.
* ld.texinfo: Add description for bndplt.
ld/testsuite/
2014-11-18 Igor Zamyatin <igor.zamyatin@intel.com>
* testsuite/ld-x86-64/bnd-ifunc-1.d: Add bndplt option.
* testsuite/ld-x86-64/bnd-ifunc-2.d: Likewise.
* testsuite/ld-x86-64/bnd-plt-1.d: Likewise. Update dissassembly
sections.
* testsuite/ld-x86-64/mpx.exp: Handle mpx3 and mpx4 tests.
* testsuite/ld-x86-64/mpx1a.rd: Remove _BND from relocation name.
* testsuite/ld-x86-64/mpx1c.rd: Likewise.
* testsuite/ld-x86-64/mpx2a.rd: Likewise.
* testsuite/ld-x86-64/mpx2c.rd: Likewise.
* testsuite/ld-x86-64/mpx3.dd: New file.
* testsuite/ld-x86-64/mpx3a.s: Likewise.
* testsuite/ld-x86-64/mpx3b.s: Likewise.
* testsuite/ld-x86-64/mpx4.dd: Likewise.
* testsuite/ld-x86-64/mpx4a.s: Likewise.
* testsuite/ld-x86-64/mpx4b.s: Likewise.
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Rather than requiring to always also set/change the base architecture,
allow just en-/disabling of architecture extensions, matching what ARM
has.
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The name xgene1 superceeds xgene-1. We retain support for the
original xgene-1 for compatibility but drop it from documentation.
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gas/
* config/tc-i386.c (cpu_arch): Add .avx512vbmi.
* doc/c-i386.texi: Document it.
opcodes/
* i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
vpmultishiftqb.
* i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS.
(cpu_flags): Add CpuAVX512VBMI.
* i386-opc.h (enum): Add CpuAVX512VBMI.
(i386_cpu_flags): Add cpuavx512vbmi.
* i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b,
vpermt2b.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
/gas/testsuite/
* gas/i386/i386.exp: Run new tests.
* gas/i386/avx512vbmi-intel.d: New file.
* gas/i386/avx512vbmi.d: Likewise.
* gas/i386/avx512vbmi.s: Likewise.
* gas/i386/avx512vbmi_vl-intel.d: Likewise.
* gas/i386/avx512vbmi_vl.d: Likewise.
* gas/i386/avx512vbmi_vl.s: Likewise.
* gas/i386/x86-64-avx512vbmi-intel.d: Likewise.
* gas/i386/x86-64-avx512vbmi.d: Likewise.
* gas/i386/x86-64-avx512vbmi.s: Likewise.
* gas/i386/x86-64-avx512vbmi_vl-intel.d: Likewise.
* gas/i386/x86-64-avx512vbmi_vl.d: Likewise.
* gas/i386/x86-64-avx512vbmi_vl.s: Likewise.
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gas/
* config/tc-i386.c (cpu_arch): Add .avx512ifma.
* doc/c-i386.texi: Document it.
opcodes/
* i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
* i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
PREFIX_EVEX_0F38B5.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
(cpu_flags): Add CpuAVX512IFMA.
* i386-opc.h (enum): Add CpuAVX512IFMA.
(i386_cpu_flags): Add cpuavx512ifma.
* i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
/gas/testsuite/
* gas/i386/i386.exp: Run new tests.
* gas/i386/avx512ifma-intel.d: New file.
* gas/i386/avx512ifma.d: Likewise.
* gas/i386/avx512ifma.s: Likewise.
* gas/i386/avx512ifma_vl-intel.d: Likewise.
* gas/i386/avx512ifma_vl.d: Likewise.
* gas/i386/avx512ifma_vl.s: Likewise.
* gas/i386/x86-64-avx512ifma-intel.d: Likewise.
* gas/i386/x86-64-avx512ifma.d: Likewise.
* gas/i386/x86-64-avx512ifma.s: Likewise.
* gas/i386/x86-64-avx512ifma_vl-intel.d: Likewise.
* gas/i386/x86-64-avx512ifma_vl.d: Likewise.
* gas/i386/x86-64-avx512ifma_vl.s: Likewise.
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gas/
* config/tc-i386.c (cpu_arch): Add .pcommit.
* doc/c-i386.texi: Document it.
/opcodes
* i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
(prefix_table): Add pcommit.
* i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
(cpu_flags): Add CpuPCOMMIT.
* i386-opc.h (enum): Add CpuPCOMMIT.
(i386_cpu_flags): Add cpupcommit.
* i386-opc.tbl: Add pcommit.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
/gas/testsuite/
* gas/i386/i386.exp: Run new tests.
* gas/i386/pcommit-intel.d: New file.
* gas/i386/pcommit.d: Likewise.
* gas/i386/pcommit.s: Likewise.
* gas/i386/x86-64-pcommit-intel.d: Likewise.
* gas/i386/x86-64-pcommit.d: Likewise.
* gas/i386/x86-64-pcommit.s: Likewise.
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gas/
* config/tc-i386.c (cpu_arch): Add .clwb.
* doc/c-i386.texi: Document it.
opcodes/
* i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
(prefix_table): Add clwb.
* i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
(cpu_flags): Add CpuCLWB.
* i386-opc.h (enum): Add CpuCLWB.
(i386_cpu_flags): Add cpuclwb.
* i386-opc.tbl: Add clwb.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
gas/testsuite/
* gas/i386/i386.exp: Run new tests.
* gas/i386/clwb-intel.d: New file.
* gas/i386/clwb.d: Likewise.
* gas/i386/clwb.s: Likewise.
* gas/i386/x86-64-clwb-intel.d: Likewise.
* gas/i386/x86-64-clwb.d: Likewise.
* gas/i386/x86-64-clwb.s: Likewise.
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* config/tc-i386.c (cpu_arch): Re-arrange avx512* and xsave*
items.
* doc/c-i386.texi: Re-arrange avx512* and xsave*. Add
clflushopt and se1. Remove duplicated entries.
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Obsolete R_X86_64_GOTPLT64 and treat it the same as R_X86_64_GOT64.
bfd/
PR gas/17598
* elf64-x86-64.c (elf_x86_64_check_relocs): Treat
R_X86_64_GOTPLT64 the same as R_X86_64_GOT64.
(elf_x86_64_relocate_section): Likewise.
gas/
PR gas/17598
* config/tc-i386.c (reloc): Support BFD_RELOC_X86_64_GOTPLT64.
gas/testsuite/
PR gas/17598
* gas/i386/reloc64.s: Add @gotplt check.
* gas/i386/reloc64.d: Updated.
* gas/i386/reloc64.l: Likewise.
ld/testsuite/
PR gas/17598
* ld-x86-64/x86-64.exp: Run gotplt1.
* ld-x86-64/gotplt1.d: New file.
* ld-x86-64/gotplt1.s: Likewise.
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PR binutils/17512
* config/obj-coff.c (coff_obj_symbol_new_hook): Set the is_sym
field.
* coffcode.h (coff_ptr_struct): Add is_sym field.
(coff_new_section_hook): Set the is_sym field.
(coff_pointerize_aux_hook): Check the is_sym field.
(coff_print_aux): Likewise.
(coff_compute_section_file_positions): Likewise.
(coff_write_object_contents): Likewise.
(coff_slurp_line_table): Likewise.
(coff_slurp_symbol_table): Likewise.
(CALC_ADDEND): Likewise.
* coffgen.c (coff_renumber_symbols): Likewise.
(coff_mangle_symbols): Likewise.
(coff_fix_symbol_name): Likewise.
(coff_write_symbol): Likewise.
(coff_write_alien_symbol): Likewise.
(coff_write_native_symbol): Likewise.
(coff_write_symbols): Likewise.
(coff_write_linenumbers): Likewise.
(coff_pointerize_aux): Likewise.
(coff_get_normalized_symtab): Likewise.
(coff_get_symbol_info): Likewise.
(bfd_coff_get_syment): Likewise.
(bfd_coff_get_auxent): Likewise.
(coff_print_symbol): Likewise.
(coff_find_nearest_line_with_names): Likewise.
(bfd_coff_set_symbol_class): Likewise.
(coff_make_empty_symbol): Set the is_sym field.
(coff_bfd_make_debug_symbol): Likewise.
* peicode.h (pe_ILF_make_a_symbol): Likewise.
* libcoff.h: Regenerate.
* libcoff-in.h: Regenerate.
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* config/tc-z80.c (parse_exp_not_indexed, parse_exp): Warning fixes.
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PR ld/17482
* config/tc-i386.c (output_insn): Don't test x86_elf_abi when
not ELF.
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* po/uk.po: Updated Ukranian translation.
* po/fr.po: Updated French translation.
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Structions with R_X86_64_GOTTPOFF relocation must be encoded with REX
prefix even if it isn't required by destination register. Otherwise
linker can't safely perform IE -> LE optimization.
bfd/
PR ld/17482
* elf64-x86-64.c (elf_x86_64_relocate_section): Update comments
for IE->LE transition.
gas/
PR ld/17482
* config/tc-i386.c (output_insn): Add a dummy REX_OPCODE prefix
for structions with R_X86_64_GOTTPOFF relocation for x32 if needed.
gas/testsuite/
PR ld/17482
* gas/i386/ilp32/x32-tls.d: New file.
* gas/i386/ilp32/x32-tls.s: Likewise.
ld/testsuite/
PR ld/17482
* ld-x86-64/tlsie4.dd: Updated.
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2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
include/opcode/
* nios2.h (nios2_find_opcode_hash): Add mach parameter to
declaration. Fix obsolete comment.
opcodes/
* nios2-dis.c (nios2_find_opcode_hash): Add mach parameter.
(nios2_disassemble): Adjust call to nios2_find_opcode_hash.
gas/
* config/tc-nios2.c (nios2_diagnose_overflow): Adjust call to
nios2_find_opcode_hash.
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bfd/
* elfxx-mips.c (update_mips_abiflags_isa): Add E_MIPS_ARCH_32R6
and E_MIPS_ARCH_64R6 support.
ld/testsuite/
* ld-mips-elf/abiflags-strip10-ph.d: New file.
* ld-mips-elf/mips-eld.exp: Run the new test.
gas/
* config/tc-mips.c (mips_elf_final_processing): Add INSN_ISA32R6
and INSN_ISA64R6 support.
gas/testsuite/
* gas/mips/elf_arch_mips32r6.d: New file.
* gas/mips/elf_arch_mips64r6.d: New file.
* gas/mips/mips.exp: Run the new tests.
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* expr.c (expr_symbol_where): Don't use register keyword.
* app.c (app_push, app_pop, do_scrub_chars): Likewise.
* ecoff.c (add_string, add_ecoff_symbol, add_aux_sym_symint,
add_aux_sym_rndx, add_aux_sym_tir, add_procedure, add_file,
ecoff_build_lineno, ecoff_setup_ext, allocate_cluster.
allocate_scope, allocate_vlinks, allocate_shash,
allocate_thash, allocate_tag, allocate_forward, allocate_thead,
allocate_lineno_list): Likewise.
* frags.c (frag_more, frag_var, frag_variant, frag_wane): Likewise.
* input-file.c (input_file_push, input_file_pop): Likewise.
* input-scrub.c (input_scrub_push, input_scrub_next_buffer): Likewise.
* subsegs.c (subseg_change): Likewise.
* symbols.c (colon, symbol_table_insert, symbol_find_or_make)
(dollar_label_name, fb_label_name): Likewise.
* write.c (relax_align): Likewise.
* config/tc-alpha.c (s_alpha_pdesc): Likewise.
* config/tc-bfin.c (bfin_s_bss): Likewise.
* config/tc-i860.c (md_estimate_size_before_relax): Likewise.
* config/tc-m68hc11.c (md_convert_frag): Likewise.
* config/tc-m68k.c (m68k_ip, crack_operand): Likewise.
(md_convert_frag_1, s_even): Likewise.
* config/tc-mips.c (mips_clear_insn_labels): Likewise.
* config/tc-mn10200.c (md_begin): Likewise.
* config/tc-s390.c (s390_setup_opcodes, md_begin): Likewise.
* config/tc-sh.c (sh_elf_cons): Likewise.
* config/tc-tic4x.c (tic4x_cons, tic4x_stringer): Likewise.
* config/m68k-parse.y (m68k_reg_parse): Likewise. Convert from K&R.
(yylex, m68k_ip_op, yyerror): Convert from K&R.
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obstack_next_free is supposed to return a void* rather than the char*
it does currently, so expressions involving pointer arithmetic need
a cast. Avoid the issue.
* config/tc-d10v.c (find_opcode): Call frag_now_fix_octets rather
than equivalent obstack_next_free expression.
* config/tc-d30v.c (find_format): Likewise.
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* config/tc-msp430.c (msp430_srcoperand): Fix range test for
20-bit values.
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binutils:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* readelf.c (print_mips_isa_ext): Print the value of Octeon3.
gas:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* config/tc-mips.c (CPU_IS_OCTEON): Handle CPU_OCTEON3.
(mips_cpu_info_table): Octeon3 enables virt ase.
* doc/c-mips.texi: Document octeon3 as an acceptable value for
-march=.
gas/testsuite:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* gas/mips/mips.exp: Add support for Octeon3 architecture.
Also add in support for running Octeon3 tests.
* gas/mips/octeon3.d: New test.
* gas/mips/octeon3.s: New test source.
opcodes:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* mips-dis.c (mips_arch_choices): Add octeon3.
* mips-opc.c (IOCT): Include INSN_OCTEON3.
(IOCT2): Likewise.
(IOCT3): New define.
(IVIRT): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
IVIRT instructions.
Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
operand for IOCT3.
bfd:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* archures.c: Add octeon3 for mips target.
* bfd-in2.h: Regenerate.
* bfd/cpu-mips.c: Define I_mipsocteon3.
nfo_struct): Add octeon3 support.
* bfd/elfxx-mips.c: (_bfd_elf_mips_mach): Add support for
octeon3.
(mips_set_isa_flags): Add support for octeon3.
(bfd_mips_isa_ext): Add bfd_mach_mips_octeon3.
(mips_mach_extensions): Make bfd_mach_mips_octeon3 an
extension of bfd_mach_mips_octeon2.
(print_mips_isa_ext): Print the value of Octeon3.
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2014-10-21 Andrew Pinski <apinski@cavium.com>
* config/tc-aarch64.c (aarch64_cpus):
Add thunderx.
* doc/c-aarch64.texi: Document that thunderx
is a valid processor name.
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fixed part of a fragment for output generation only, which required
MAX_MEM_FOR_RS_ALIGN_CODE to be large enough to hold the maximum pad.
* config/tc-aarch64.h (MAX_MEM_FOR_RS_ALIGN_CODE): Define to 7.
* config/tc-aarch64.c (aarch64_handle_align): Rewrite to handle
large alignments with a constant fragment size of
MAX_MEM_FOR_RS_ALIGN_CODE.
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2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
include/opcode/
* nios2.h (enum iw_format_type): New.
(struct nios2_opcode): Update comments. Add size and format fields.
(NIOS2_INSN_OPTARG): New.
(REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
(struct nios2_reg): Add regtype field.
(GET_INSN_FIELD, SET_INSN_FIELD): Delete.
(IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
(IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
(IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
(IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
(IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
(IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
(IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
(IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
(IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
(IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
(IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
(OP_MASK_OP, OP_SH_OP): Delete.
(OP_MASK_IOP, OP_SH_IOP): Delete.
(OP_MASK_IRD, OP_SH_IRD): Delete.
(OP_MASK_IRT, OP_SH_IRT): Delete.
(OP_MASK_IRS, OP_SH_IRS): Delete.
(OP_MASK_ROP, OP_SH_ROP): Delete.
(OP_MASK_RRD, OP_SH_RRD): Delete.
(OP_MASK_RRT, OP_SH_RRT): Delete.
(OP_MASK_RRS, OP_SH_RRS): Delete.
(OP_MASK_JOP, OP_SH_JOP): Delete.
(OP_MASK_IMM26, OP_SH_IMM26): Delete.
(OP_MASK_RCTL, OP_SH_RCTL): Delete.
(OP_MASK_IMM5, OP_SH_IMM5): Delete.
(OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
(OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
(OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
(OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
(OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
(OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
(OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
(OP_MASK_<insn>, OP_MASK): Delete.
(GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
(GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
Include nios2r1.h to define new instruction opcode constants
and accessors.
(nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
(bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
(bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
(NUMOPCODES, NUMREGISTERS): Delete.
* nios2r1.h: New file.
opcodes/
* nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
(nios2_builtin_opcodes): Rename to nios2_r1_opcodes. Use new
MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers. Add
size and format initializers. Merge 'b' arguments into 'j'.
(NIOS2_NUM_OPCODES): Adjust definition.
(bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
(nios2_opcodes): Adjust.
(bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
* nios2-dis.c (INSNLEN): Update comment.
(nios2_hash_init, nios2_hash): Delete.
(OPCODE_HASH_SIZE): New.
(nios2_r1_extract_opcode): New.
(nios2_disassembler_state): New.
(nios2_r1_disassembler_state): New.
(nios2_init_opcode_hash): Add state parameter. Adjust to use it.
(nios2_find_opcode_hash): Use state object.
(bad_opcode): New.
(nios2_print_insn_arg): Add op parameter. Use it to access
format. Remove 'b' case.
(nios2_disassemble): Remove special case for nop. Remove
hard-coded instruction size.
gas/
* config/tc-nios2.c (nios2_insn_infoS): Add constant_bits field.
(nios2_arg_infoS, nios2_arg_hash, nios2_arg_lookup): Delete.
(nios2_control_register_arg_p): Delete.
(nios2_coproc_reg): Delete.
(nios2_relax_frag): Remove hard-coded instruction size.
(md_convert_frag): Use new insn accessor macros.
(nios2_diagnose_overflow): Remove hard-coded instruction size.
(md_apply_fix): Likewise.
(bad_opcode): New.
(nios2_parse_reg): New.
(nios2_assemble_expression): Remove prev_reloc parameter. Adjust
uses and callers.
(nios2_assemble_arg_c): New.
(nios2_assemble_arg_d): New.
(nios2_assemble_arg_s): New.
(nios2_assemble_arg_t): New.
(nios2_assemble_arg_i): New.
(nios2_assemble_arg_u): New.
(nios2_assemble_arg_o): New.
(nios2_assemble_arg_j): New.
(nios2_assemble_arg_l): New.
(nios2_assemble_arg_m): New.
(nios2_assemble_args): New.
(nios2_assemble_args_dst): Delete.
(nios2_assemble_args_tsi): Delete.
(nios2_assemble_args_tsu): Delete.
(nios2_assemble_args_sto): Delete.
(nios2_assemble_args_o): Delete.
(nios2_assemble_args_is): Delete.
(nios2_assemble_args_m): Delete.
(nios2_assemble_args_s): Delete.
(nios2_assemble_args_tis): Delete.
(nios2_assemble_args_dc): Delete.
(nios2_assemble_args_cs): Delete.
(nios2_assemble_args_ds): Delete.
(nios2_assemble_args_ldst): Delete.
(nios2_assemble_args_none): Delete.
(nios2_assemble_args_dsj): Delete.
(nios2_assemble_args_d): Delete.
(nios2_assemble_args_b): Delete.
(nios2_arg_info_structs): Delete.
(NIOS2_NUM_ARGS): Delete.
(nios2_consume_arg): Remove insn parameter. Use new macros.
Don't check register arguments here. Remove 'b' case.
(nios2_consume_separator): Move check for missing separators to...
(nios2_parse_args): ...here. Remove special case for optional
arguments.
(output_insn): Avoid using hard-coded insn size.
(output_ubranch): Likewise.
(output_cbranch): Likewise.
(output_call): Use new macros.
(output_addi): Likewise.
(output_ori): Likewise.
(output_xori): Likewise.
(output_movia): Likewise.
(md_begin): Remove nios2_arg_info_structs initialization.
(md_assemble): Initialize constant_bits field. Use
nios2_parse_args instead of looking up parse function in hash table.
gdb/
* nios2-tdep.c (nios2_analyze_prologue): Use new instruction field
accessors and constants from nios2 opcodes update.
(nios2_get_next_pc): Likewise.
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gas/
* doc/as.texinfo: Update the MIPS FP ABI descriptions.
* doc/c-mips.texi: Spell check and correct throughout.
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This makes sure `HAVE_CODE_COMPRESSION' evaluates correctly when the
`.insn' directive is used at the beginning of a source file before any
instructions have been produced and that ELF file header's MIPS16 and
microMIPS ASE flags are set correctly in the case where no instructions
have been produced other than with the said directive.
gas/
* config/tc-mips.c (s_insn): Set file options.
gas/testsuite/
* gas/mips/insn-opts.d: New test.
* gas/mips/insn-opts.s: New test source.
* gas/mips/mips.exp: Run the new test.
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This patch adds -mcpu=thunderx support to gas.
OK? Tested with no regressions.
ChangeLog:
* config/tc-aarch64.c (aarch64_cpus):
Add thunderx.
* doc/c-aarch64.texi: Document that thunderx
is a valid processor name.
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The construct being added to the cond.s test case otherwise triggered
both the "missing closing ..." and the "stray ..." (twice) warnings in
_find_end_of_line(). As that code fragments suggests, this is needed to
support (include) files that can be used for both assembler .include
and compiler #include directives.
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According to my reading of the spec it was an oversight for them to
not having got enabled when Power8 support got added.
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Asserting "idx" to be non-negative when subsequent code handles this
case is bogus. In fact the assertion triggers e.g. when mistakenly
using the arm32 comment character @ following an instruction.
While doing this I also noticed that despite there being local
variables "detail" and "idx", not all places where they could be used
did actually make use of them, so this is being adjusted at once.
Finally, for the code to be slightly more robust, also change
comparisons against -1 to such checking for a (non-)negative value.
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The write.c change is to make gas report an error if reg_section
symbols should leak in future. The tc-i386.c change is the real fix.
Note that the error isn't the most helpful, "redefined symbol cannot
be used on reloc", but I'm not inclined to improve what is really an
internal gas error. reg_section symbols shouldn't leak..
gas/
PR 17493
* write.c (adjust_reloc_syms): Don't allow symbols in reg_section
to be reduced to reg_section section symbol.
* gas/config/tc-i386.c (i386_finalize_immediate): Reject all
reg_section immediates.
gas/testsuite/
* gas/i386/inval-equ-2.l: Adjust.
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gas/
* doc/c-mips.texi: Fix bad @value references.
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bfd/
2014-10-15 Tristan Gingold <gingold@adacore.com>
* version.m4: Bump version to 2.25.51
* configure: Regenerate.
binutils/
2014-10-15 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
gas/
2014-10-15 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
gprof/
2014-10-15 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
ld/
2014-10-15 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
opcodes/
2014-10-15 Tristan Gingold <gingold@adacore.com>
* configure: Regenerate.
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If src contains n or more bytes, strncat() writes n+1 bytes to dest
(n from src plus the terminating null byte). Therefore, the size of
dest must be at least strlen(dest)+n+1.
* config/tc-tic4x.c (md_assemble): Correct strncat size.
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binutils/
2014-10-14 Tristan Gingold <gingold@adacore.com>
* NEWS: Add marker for 2.25.
gas/
2014-10-14 Tristan Gingold <gingold@adacore.com>
* NEWS: Add marker for 2.25.
ld/
2014-10-14 Tristan Gingold <gingold@adacore.com>
* NEWS: Add marker for 2.25.
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PR 17453
bfd/
* libbfd.c (COERCE16, COERCE32, COERCE64): Use unsigned types.
(EIGHT_GAZILLION): Delete.
binutils/
* dwarf.c (read_leb128): Avoid signed overflow.
(read_debug_line_header): Likewise.
gas/
* config/tc-i386.c (fits_in_signed_long): Use unsigned param and
expression to avoid signed overflow.
(fits_in_signed_byte, fits_in_unsigned_byte, fits_in_unsigned_word,
fits_in_signed_word, fits_in_unsigned_long): Similarly.
* expr.c (operand <'-'>): Avoid signed overflow.
* read.c (s_comm_internal): Likewise.
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