Age | Commit message (Collapse) | Author | Files | Lines |
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* tc-i386.c (md_assemble): Return after the error message;
move testing for 64bit operands to proper place.
* i386.exp: Add tests for presence of 32bit versus 64bit output
format; run both 64bit and 32bit tests when format is available;
add x86_64 test.
* x86_64.s: New file.
* x86_64.d: New file.
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* doc/as.texinfo: Document '#' as comment character for i386 and
x86_64. Add AMD x86-64 into menu of machine dependent information.
* doc/c-i386.texi: Document x86_64 extensions.
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* i386.h (i386_optab): Make [sml]fence template to use immext field.
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* NEWS: Add note about Pentium4 support.
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(type_names): Add new types.
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CpuUnknown): Renumber
(CpuP4, CpuSSE2): New.
(CpuUnknownFlags): Add CpuP4 and CpuSSE2
* i386.h (i386_optab): Fix 64bit pushf template; Add instructions
introduced by Pentium4
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* config/tc-alpha.c (alpha_force_relocation): Handle vtable
relocs.
(alpha_fix_adjustable): Likewise.
(md_apply_fix): Likewise.
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* gas/arm/adrl.s, gas/arm/pic.s, gas/arm/msr-bad.s: New tests.
* gas/arm/arm.exp: Run them.
* gas/arm/adrl.d, gas/arm/pic.d: Expected results for above.
* gas/arm/arm6.s: Also test uppercase `CPSR' and `SPSR'.
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* listing.c (listing_message): Allocate string only if it is
used.
* configure: Rebuild.
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Point out caveats with generating fixups for the opcode in a frag.
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* NEWS: Add x86_64.
* i386.h (i386_optab): Add "rex*" instructions;
add swapgs; disable jmp/call far direct instructions for
64bit mode; add syscall and sysret; disable registers for 0xc6
template. Add 'q' suffixes to extendable instructions, disable
obsoletted instructions, add new sign/zero extension ones.
(i386_regtab): Add extended registers.
(*Suf): Add No_qSuf.
(q_Suf, wlq_Suf, bwlq_Suf): New.
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* listing.c (calc_hex): Print the variable part only if the
fragment type is rs_fill.
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TC_LINKRELAX_FIXUP): Fix typos.
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"optimize" the alignment == 0 case.
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* frags.c (NOP_OPCODE): Move default from read.c.
(MAX_MEM_FOR_RS_ALIGN_CODE): New default.
(frag_align_code): New.
* frags.h (frag_align_code): Declare.
* read.c (NOP_OPCODE): Remove.
(do_align): Use frag_align_code.
* write.c (NOP_OPCODE): Remove.
(get_recorded_alignment): New.
(cvt_frag_to_fill): Handle rs_align_test.
(relax_segment): Likewise.
(subsegs_finish): Align last subseg in section to the
section alignment. Use frag_align_code.
* write.h (get_recorded_alignment): Declare.
* config/obj-coff.c (size_section): Handle rs_align_test.
(fill_section, fixup_mdeps): Likewise.
(write_object_file): Use frag_align_code.
* config/tc-alpha.c (alpha_align): Use frag_align_code.
(alpha_handle_align): New.
* config/tc-alpha.h (HANDLE_ALIGN): New.
(MAX_MEM_FOR_RS_ALIGN_CODE): New.
* config/tc-i386.h (md_do_align): Use frag_align_code.
(MAX_MEM_FOR_RS_ALIGN_CODE): New.
* config/tc-ia64.c (ia64_md_do_align): Don't do code alignment.
(ia64_handle_align): New.
* config/tc-ia64.h (HANDLE_ALIGN): New.
(MAX_MEM_FOR_RS_ALIGN_CODE): New.
* config/tc-m32r.c (m32r_do_align): Remove.
(m32r_handle_align): New.
(fill_insn): Use frag_align_code.
* config/tc-m32r.h (md_do_align): Remove.
(HANDLE_ALIGN, MAX_MEM_FOR_RS_ALIGN_CODE): New.
* config/tc-m88k.c, config/tc-m88k.h: Similarly.
* config/tc-mips.c, config/tc-mips.h: Similarly.
* config/tc-sh.c (sh_cons_align): Use rs_align_test.
(sh_handle_align): Likewise. Handle rs_align_code.
(sh_do_align): Remove.
* config/tc-sh.h (md_do_align): Remove.
(MAX_MEM_FOR_RS_ALIGN_CODE): New.
* config/tc-sparc.c (sparc_cons_align): Use rs_align_test.
(sparc_handle_align): Likewise. Handle rs_align_code.
* config/tc-sparc.h (md_do_align): Remove.
(MAX_MEM_FOR_RS_ALIGN_CODE): New.
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when we assemble the first half of a pair.
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* gas/i386/intel.s: Replace "nop" with ".p2align 4,0".
* gas/i386/intel.d: Updated.
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* config/tc-i386.c (reloc): Update the macro for non-bfd
assembler.
(BFD_RELOC_X86_64_GOTPCREL): Set to 0 for non-bfd assembler.
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* dwarf2dbg.c (dwarf2_finish): Remove #if BFD_ASSEMBLER.
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(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
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* config/tc-i386.c (intel_e09_1): Only flag as a memory operand if
it's not an offset expression.
(intel_e10_1): Ditto. Also, if the operand is an offset expression,
keep the braces '[' and ']' in the output string.
(intel_e11): Ditto. Also remove comparison intel_parser.op_modifier
!= FLAT. There is no such op_modifier.
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* as.h: Fix formatting.
* cgen.h: Likewise.
* dwarf2dbg.c: Likewise.
* input-scrub.c: Likewise.
* read.h: Likewise.
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configure: Regenerate.
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* elfxx-ia64.c (get_dyn_sym_info): Cast %p argument to void *.
* config/tc-ia64.h (ia64_init): Add prototype.
* gas/ia64/dv-imply.d, gas/ia64/dv-mutex.d, gas/ia64/dv-safe.d,
gas/ia64/dv-srlz.d, gas/ia64/opc-m.d: Update.
* ia64-dis.c (print_insn_ia64): Cast away const on ia64_free_opcode
argument.
* ia64_gen.c (insert_deplist): Cast sizeof result to int.
(print_dependency_table): Print NULL if semantics field not set.
(insert_opcode_dependencies): Mark cmp parameter as unused.
(print_main_table): Use fprintf_vma to print long long fields.
(main): Mark argv paramter as unused. Convert to old style definition.
* ia64-opc.c (ia64_find_dependency): Cast sizeof result to int.
* ia64-asmtab.c: Regnerate.
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* dwarf2dbg.c: Enabled only if BFD_ASSEMBLER is defined.
* read.h (outputting_stabs_line_debug): Change it to int.
* stabs.c (outputting_stabs_line_debug): Likewise.
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the address of a function result.
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* config/tc-ppc.c (md_pseudo_table): Add .file and .loc.
(md_assemble): Call dwarf2_emit_insn.
(shlib): Fix typo SHILB -> SHLIB.
(md_parse_option): Likewise.
(ppc_elf_validate_fix): Likewise:
* config/tc-ppc.h (DWARF2_LINE_MIN_INSN_LENGTH): New.
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Fix formatting
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* gas/i386/intel.d: Adjusted for the a.out assembler.
* gas/i386/intel.s: Likewise.
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mode; convert 'd' suffix to 's' or 'l'; remove all DWORD_MNEM_SUFFIX
references.
(intel_e09_1): Convert QWORD to 'l' suffix for FP operations; refuse
otherwise.
* tc-i386.h (DWORD_MNEM_SUFFIX): Kill.
(No_dSuf): Kill.
* i386.h (*_Suf): Remove No_dSuf.
(d_suf, wld_Suf,sld_Suf, sldx_Suf, bwld_Suf, d_FP, sld_FP, sldx_FP)
Remove.
(i386_optab): Remove 'd' in the suffixes.
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* config/tc-mips.c: Fix formatting.
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