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2017-02-20Downgrade powerpc register error to warningAlan Modra3-5/+12
PR 21118 * NEWS: Revise powerpc register check. * config/tc-ppc.c (ppc_optimize_expr, md_assemble): Make "invalid register expression" a warning.
2017-02-17GAS: Add ECOFF `.aent' pseudo-op supportMaciej W. Rozycki8-14/+76
Implement the ECOFF `.aent' pseudo-op for ECOFF-style `.mdebug' section support with ELF objects and, for consistency, also with ECOFF objects. This is so that the same MIPS source can be assembled without and with `.mdebug' section generation enabled. Taking the `gas/testsuite/gas/mips/aent.s' test case source as an example and the `mips-linux' target we have: $ as -o aent.o aent.s $ as -mdebug -o aent.o aent.s aent.s: Assembler messages: aent.s:10: Error: unknown pseudo-op: `.aent' $ because for the !ECOFF_DEBUGGING case (which is the default) the pseudo-op is already handled by the MIPS backend with `s_mips_ent', however no handler is present for the opposite case. For the MIPS target this is a functional regression introduced with commit ecb4347adecd ("Last take: approval for MIPS_STABS_ELF killing"), <https://sourceware.org/ml/binutils/2002-06/msg00443.html>, where support for the `.mdebug' section was added along with its associated `-mdebug'/`-no-mdebug' command-line options, bringing an inconsistency between the assembly syntax supported for each of these options as far as the `.aent' pseudo-op is concerned. Assembly language documentation available describes the pseudo-op respectively as follows[1]: " .aent name, symno Sets an alternate entry point for the current procedure. Use this information when you want to generate information for the debugger. It must appear inside an .ent/.end pair." and[2]: " .aent name [,symno] Sets an alternate entry point for the current procedure. Use this information when you want to generate information for the debugger. This directive must appear between a pair of .ent and .end directives. (The optional symno is for compiler use only. It refers to a dense number in a .T file (symbol table).)" Copy the approach from `s_mips_ent' then and add `.aent' support to the `.ent' pseudo-op handler shared between the ELF and ECOFF object file format backends, by setting BSF_FUNCTION for the symbol requested. References: [1] "MIPSpro Assembly Language Programmer's Guide", Silicon Graphics, Inc., Document Number 007-2418-004, Section 8.1 "Op-Codes", p. 96 <http://techpubs.sgi.com/library/manuals/2000/007-2418-004/pdf/007-2418-004.pdf> [2] "Digital UNIX Assembly Language Programmer's Guide", Digital Equipment Corporation, Order Number: AA-PS31D-TE, March 1996, Chapter 5 "Assembler Directives", p. 5-2 <http://h41361.www4.hpe.com/docs/base_doc/DOCUMENTATION/V40G_PDF/APS31DTE.PDF> gas/ * ecoff.c (ecoff_directive_ent, add_procedure): Handle `.aent'. * config/obj-ecoff.c (obj_pseudo_table): Add "aent" entry. * config/obj-elf.c (ecoff_debug_pseudo_table): Likewise. * testsuite/gas/mips/aent-2.d: New test. * testsuite/gas/mips/aent-mdebug.d: New test. * testsuite/gas/mips/aent-mdebug-2.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests.
2017-02-15[AArch64] Add SVE system registersRichard Sandiford5-0/+85
This patch adds the SVE-specific system registers. opcodes/ * aarch64-opc.c (aarch64_sys_regs): Add SVE registers. (aarch64_sys_reg_supported_p): Handle them. gas/ * testsuite/gas/aarch64/sve-sysreg.s, testsuite/gas/aarch64/sve-sysreg.d, testsuite/gas/aarch64/sve-sysreg-invalid.d, testsuite/gas/aarch64/sve-sysreg-invalid.l: New tests.
2017-02-15[AArch64] Fix +sve documentationRichard Sandiford2-2/+6
The documentation entry for the SVE feature incorrectly said that it was enabled by default for ARMv8-A or later. This patch fixes that and also mentions that +sve implies +simd. (It also implies +fp, but that follows by transitivity.) gas/ * doc/c-aarch64.texi: Fix sve entry.
2017-02-15[ARC] Fix assembler relaxation.Claudiu Zissulescu28-9/+355
Fix assembler relaxation step for add, ld, mov, mpy and sub instructions. Add tests to it. gas/ 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (md_convert_frag): Remove @pcl relocation information from input expression. (assemble_insn): Make sure pcrel is correctly set. (arc_pcrel_adjust): Compensate for PCL rounding. * testsuite/gas/arc/relax-add01.d: New file. * testsuite/gas/arc/relax-add01.s: Likewise. * testsuite/gas/arc/relax-add02.d: Likewise. * testsuite/gas/arc/relax-add02.s: Likewise. * testsuite/gas/arc/relax-add03.d: Likewise. * testsuite/gas/arc/relax-add03.s: Likewise. * testsuite/gas/arc/relax-add04.d: Likewise. * testsuite/gas/arc/relax-add04.s: Likewise. * testsuite/gas/arc/relax-ld01.d: Likewise. * testsuite/gas/arc/relax-ld01.s: Likewise. * testsuite/gas/arc/relax-ld02.d: Likewise. * testsuite/gas/arc/relax-ld02.s: Likewise. * testsuite/gas/arc/relax-mov01.d: Likewise. * testsuite/gas/arc/relax-mov01.s: Likewise. * testsuite/gas/arc/relax-mov02.d: Likewise. * testsuite/gas/arc/relax-mov02.s: Likewise. * testsuite/gas/arc/relax-mpy01.d: Likewise. * testsuite/gas/arc/relax-mpy01.s: Likewise. * testsuite/gas/arc/relax-sub01.d: Likewise. * testsuite/gas/arc/relax-sub01.s: Likewise. * testsuite/gas/arc/relax-sub02.d: Likewise. * testsuite/gas/arc/relax-sub02.s: Likewise. * testsuite/gas/arc/relax-sub03.d: Likewise. * testsuite/gas/arc/relax-sub03.s: Likewise. * testsuite/gas/arc/relax-sub04.d: Likewise. * testsuite/gas/arc/relax-sub04.s: Likewise. opcodes/ 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (UIMM6_20R): Define. (SIMM12_20): Use above. (SIMM12_20R): Define. (SIMM3_5_S): Use above. (UIMM7_A32_11R_S): Define. (UIMM7_9_S): Use above. (UIMM3_13R_S): Define. (SIMM11_A32_7_S): Use above. (SIMM9_8R): Define. (UIMM10_A32_8_S): Use above. (UIMM8_8R_S): Define. (W6): Use above. (arc_relax_opcodes): Use all above defines.
2017-02-15Distinguish some of the registers different on ARC700 and HS38 cpusVineet Gupta2-1/+5
opcodes * arc-regs.h: Distinguish some of the registers different on ARC700 and HS38 cpus. gas * testsuite/gas/arc/st.d: Update for 0xe having a name now
2017-02-14PowerPC register expression checksAlan Modra4-484/+568
This stops powerpc gas blithely accepting such nonsense as "addi %f4,%cr3,%r31". PR 21118 gas/ * NEWS: Mention powerpc register checks. * config/tc-ppc.c (struct pd_reg): Make value a short. Add flags. (pre_defined_registers): Delete fpscr and pmr entries. Set register type in flags. (cr_names): Set type in flags. (reg_name_search): Return pointer to struct pd_reg rather than value. (register_name): Adjust to suit. Set X_md from flags. (ppc_parse_name): Likewise. (ppc_optimize_expr): New function. (md_assemble): Verify expresion reg flags match operand. * config/tc-ppc.h (md_optimize_expr): Define. (ppc_optimize_expr): Declare. include/ * opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first. (PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define. opcodes/ * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
2017-02-14Fix powerpc testsuite source errorsAlan Modra4-22/+28
PR 21118 work exposed these errors in the testsuite. * testsuite/gas/ppc/cell.s: Correct invalid registers. * testsuite/gas/ppc/vle-simple-1.s: Likewise. * testsuite/gas/ppc/vle-simple-2.s: Likewise.
2017-02-13[ARM] Allow immediate without prefix in unified syntax for VCMPThomas Preud'homme4-3/+29
2017-02-13 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (parse_ifimm_zero): Make prefix optional in unified syntax. * testsuite/gas/arm/vcmp-noprefix-imm.d: New file. * testsuite/gas/arm/vcmp-noprefix-imm.s: New file.
2017-02-10POWER9 add scv/rfscv instruction supportNicholas Piggin3-0/+10
opcodes/ * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics. gas/ * testsuite/gas/ppc/power9.d <scv, rfscv>: New tests.
2017-02-06[ARC] Provide an interface to decode ARC instructions.Claudiu Zissulescu1-0/+4
gas/ 2017-02-06 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (parse_opcode_flags): Ignore implicit flags. include/ 2017-02-06 Claudiu Zissulescu <claziss@synopsys.com> Anton Kolesov <anton.kolesov@synopsys.com> * opcode/arc.h (insn_class_t): Add ENTER, LEAVE, POP, PUSH, BBIT0, BBIT1, BI, BIH, BRCC, EI, JLI, and SUB instruction classes. (flag_class_t): Add F_CLASS_WB, F_CLASS_ZZ, and F_CLASS_IMPLICIT flag classes. opcode/ 2017-02-06 Claudiu Zissulescu <claziss@synopsys.com> Anton Kolesov <anton.kolesov@synopsys.com> * arc-dis.c (arc_disassemble_info): New structure. (init_arc_disasm_info): New function. (find_format_from_table): Ignore implicit flags. (find_format): Update dissassembler private data. (print_flags): Likewise. (print_insn_arc): Likewise. (arc_opcode_to_insn_type): Consider the new added instruction classes. (arcAnalyzeInstr): Remove. (arc_insn_decode): New function. * arc-dis.h (arc_ldst_writeback_mode): New enum. (arc_ldst_data_size): Likewise. (arc_condition_code): Likewise. (arc_operand_kind): Likewise. (arc_insn_kind): New struct. (arc_instruction): Likewise. (arc_insn_decode): Declare function. (ARC_Debugger_OperandType): Deleted. (Flow): Likewise. (NullifyMode): Likewise. (allOperandsSize): Likewise. (arcDisState): Likewise. (arcAnalyzeInstr): Likewise. * arc-dis.c (arc_opcode_to_insn_type): Handle newly introduced insn_class_t enums. * arc-opc.c (F_SIZED): New define. (C_CC_EQ, C_CC_GE, C_CC_GT, C_CC_HI, C_CC_HS): Likewise. (C_CC_LE, C_CC_LO, C_CC_LS, C_CC_LT, C_CC_NE): Likewise. (C_CC_NE, C_AA_AB, C_AA_AW, C_ZZ_D, C_ZZ_H, C_ZZ_B): Likewise. (arc_flag_classes): Add F_CLASS_COND/F_CLASS_IMPLICIT flags. * opcodes/arc-tbl.h: Update instructions to include new F_CLASS_IMPLICIT flags. (bbit0, lp): Change class. (bbit1, bi, bih, br*, ei_s, jli_s): Likewsie
2017-02-02MIPS/GAS/doc: Include MIPS options in the man pageMaciej W. Rozycki2-0/+7
Include the detailed MIPS option description in the man page along with other target descriptions and complementing the terse list earlier on. gas/ * doc/as.texinfo (Overview): Select MIPS options for man page inclusion.
2017-01-30MIPS: Add options to control branch ISA checksMaciej W. Rozycki11-0/+267
Complement commit 9d862524f6ae ("MIPS: Verify the ISA mode and alignment of branch and jump targets") and add GAS and LD options to control the checks for invalid branches between ISA modes introduced there, to help with some handwritten code lacking `.insn' annotation for labels used as branch targets and code produced by older versions of GCC which suffers from the issue with branches to code that has been optimized away, addressed with GCC commit 242424 ("MIPS/GCC: Mark trailing labels with `.insn'"), <https://gcc.gnu.org/ml/gcc-patches/2016-11/msg01061.html>. bfd/ * elfxx-mips.h (_bfd_mips_elf_insn32): Rename prototype to... (_bfd_mips_elf_linker_flags): ... this. Add another parameter. * elfxx-mips.c (mips_elf_link_hash_table): Add `ignore_branch_isa' member. (mips_elf_perform_relocation): Do not treat an ISA mode mismatch in branch relocation calculation as an error if `ignore_branch_isa' has been set. (_bfd_mips_elf_insn32): Rename to... (_bfd_mips_elf_linker_flags): ... this. Rename the `on' parameter to `insn32' and add an `ignore_branch_isa' parameter. Handle the new parameter. gas/ * config/tc-mips.c (mips_ignore_branch_isa): New variable. (options): Add OPTION_IGNORE_BRANCH_ISA and OPTION_NO_IGNORE_BRANCH_ISA enum values. (md_longopts): Add "mignore-branch-isa" and "mno-ignore-branch-isa" options. (md_parse_option): Handle OPTION_IGNORE_BRANCH_ISA and OPTION_NO_IGNORE_BRANCH_ISA. (fix_bad_cross_mode_branch_p): Return FALSE if `mips_ignore_branch_isa' has been set. (md_show_usage): Add `-mignore-branch-isa' and `-mno-ignore-branch-isa'. * doc/as.texinfo (Target MIPS options): Add `-mignore-branch-isa' and `-mno-ignore-branch-isa' options. (-mignore-branch-isa, -mno-ignore-branch-isa): New options. * doc/c-mips.texi (MIPS Options): Add `-mignore-branch-isa' and `-mno-ignore-branch-isa' options. * testsuite/gas/mips/branch-local-ignore-2.d: New test. * testsuite/gas/mips/branch-local-ignore-3.d: New test. * testsuite/gas/mips/branch-local-ignore-n32-2.d: New test. * testsuite/gas/mips/branch-local-ignore-n32-3.d: New test. * testsuite/gas/mips/branch-local-ignore-n64-2.d: New test. * testsuite/gas/mips/branch-local-ignore-n64-3.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * emultempl/mipself.em (ignore_branch_isa): New variable. (mips_create_output_section_statements): Rename `_bfd_mips_elf_insn32' called to `_bfd_mips_elf_linker_flags', add `ignore_branch_isa' argument. (PARSE_AND_LIST_PROLOGUE): Add OPTION_IGNORE_BRANCH_ISA and OPTION_NO_IGNORE_BRANCH_ISA enum values. (PARSE_AND_LIST_LONGOPTS): Add "ignore-branch-isa" and "no-ignore-branch-isa" options. (PARSE_AND_LIST_OPTIONS): Add `--ignore-branch-isa' and `--no-ignore-branch-isa'. (PARSE_AND_LIST_ARGS_CASES): Handle OPTION_IGNORE_BRANCH_ISA and OPTION_NO_IGNORE_BRANCH_ISA. * ld.texinfo (Options specific to MIPS targets): Add `--ignore-branch-isa' and `--no-ignore-branch-isa' options. (ld and the MIPS family): Likewise. * testsuite/ld-mips-elf/bal-jalx-pic-ignore.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-n32.d: New test. * testsuite/ld-mips-elf/bal-jalx-pic-ignore-n64.d: New test. * testsuite/ld-mips-elf/unaligned-branch-ignore-2.d: New test. * testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1: New test. * testsuite/ld-mips-elf/unaligned-branch-ignore-mips16: New test. * testsuite/ld-mips-elf/unaligned-branch-ignore-micromips: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2017-01-30MIPS/GAS/testsuite: Convert branch local list tests to dump testsMaciej W. Rozycki8-12/+35
gas/ * testsuite/gas/mips/branch-local-2.d: New test. * testsuite/gas/mips/branch-local-3.d: New test. * testsuite/gas/mips/branch-local-n32-2.d: New test. * testsuite/gas/mips/branch-local-n32-3.d: New test. * testsuite/gas/mips/branch-local-n64-2.d: New test. * testsuite/gas/mips/branch-local-n64-3.d: New test. * testsuite/gas/mips/mips.exp: Fold corresponding list tests into the new tests.
2017-01-27Fix disassembling of TIC6X parallel instructions where the previous fetch ↵Alexis Deruell3-0/+91
packet ended with a 32-bit insn. PR 21056 opcodes * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel instructions when the previous fetch packet ends with a 32-bit instruction. gas * testsuite/gas/tic6x/insns16-parallel.s: New test case. * testsuite/gas/tic6x/insns16-parallel.d: New test driver.
2017-01-25gas: Default to ELF for RTEMS targetsSebastian Huber2-14/+23
* configure.tgt (aarch64*-*-rtems*): Remove. (bfin-*-rtems*): Likewise. (h8300-*-rtems*): Likewise. (i386-*-rtems*): Likewise. (m32c-*-rtems*): Likewise. (m32r-*-rtems*): Likewise. (m68k-*-rtems*): Likewise. (mips-*-rtems*): Likewise. (nios2-*-rtems*): Likewise. (ppc-*-rtems*): Likewise. (sh-*-rtems*): Likewise. (sparc64-*-rtems*): Likewise. (sparc-*-rtems*): Likewise. (*-*-rtems*) Use ELF format.
2017-01-25gas: Use ARM EABI for RTEMSSebastian Huber2-2/+5
* configure.tgt (arm-*-rtems*): Move to (arm-*-eabi*).
2017-01-25Remove all RTEMS COFF targetsSebastian Huber2-1/+4
bfd/ * config.bfd (*-*-rtemscoff*): Mark as removed. gas/ * configure.tgt (sh-*-rtemscoff*): Remove. ld/ * configure.tgt (h8300-*-rtemscoff*): Remove. (i960-*-rtems*): Likewise. (m68*-*-rtemscoff*): Likewise. (sh-*-rtemscoff*): Likewise.
2017-01-24RISC-V gas: Remove em=linux from configure.tgtSebastian Huber2-1/+5
The use of te-linux.h is unnecessary since the TE_LINUX define is unused and LOCAL_LABELS_FB is defined to 1 in tc-riscv.h as well. gas/ * configure.tgt (riscv*-*-*): Remove em=linux.
2017-01-23Fix spelling mistakes and typos in the GAS sources.Nick Clifton103-410/+516
PR gas/21072 * asintl.h: Fix spelling mistakes and typos. * atof-generic.c: Likewise. * bit_fix.h: Likewise. * config/atof-ieee.c: Likewise. * config/bfin-defs.h: Likewise. * config/bfin-parse.y: Likewise. * config/obj-coff-seh.h: Likewise. * config/obj-coff.c: Likewise. * config/obj-evax.c: Likewise. * config/obj-macho.c: Likewise. * config/rx-parse.y: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-avr.c: Likewise. * config/tc-bfin.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-cris.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-d10v.c: Likewise. * config/tc-d30v.c: Likewise. * config/tc-dlx.c: Likewise. * config/tc-epiphany.c: Likewise. * config/tc-frv.c: Likewise. * config/tc-hppa.c: Likewise. * config/tc-i370.c: Likewise. * config/tc-i386-intel.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m32r.c: Likewise. * config/tc-m68hc11.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mcore.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-mep.h: Likewise. * config/tc-metag.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-mmix.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-msp430.c: Likewise. * config/tc-msp430.h: Likewise. * config/tc-nds32.c: Likewise. * config/tc-nds32.h: Likewise. * config/tc-nios2.c: Likewise. * config/tc-nios2.h: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-pdp11.c: Likewise. * config/tc-ppc.c: Likewise. * config/tc-pru.c: Likewise. * config/tc-rx.c: Likewise. * config/tc-s390.c: Likewise. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sh.c: Likewise. * config/tc-sh64.c: Likewise. * config/tc-sparc.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-v850.c: Likewise. * config/tc-vax.c: Likewise. * config/tc-visium.c: Likewise. * config/tc-xgate.c: Likewise. * config/tc-xtensa.c: Likewise. * config/tc-z80.c: Likewise. * config/tc-z8k.c: Likewise. * config/te-vms.c: Likewise. * config/xtensa-relax.c: Likewise. * doc/as.texinfo: Likewise. * doc/c-arm.texi: Likewise. * doc/c-hppa.texi: Likewise. * doc/c-i370.texi: Likewise. * doc/c-i386.texi: Likewise. * doc/c-m32r.texi: Likewise. * doc/c-m68k.texi: Likewise. * doc/c-mmix.texi: Likewise. * doc/c-msp430.texi: Likewise. * doc/c-nds32.texi: Likewise. * doc/c-ns32k.texi: Likewise. * doc/c-riscv.texi: Likewise. * doc/c-rx.texi: Likewise. * doc/c-s390.texi: Likewise. * doc/c-tic6x.texi: Likewise. * doc/c-tilegx.texi: Likewise. * doc/c-tilepro.texi: Likewise. * doc/c-v850.texi: Likewise. * doc/c-xgate.texi: Likewise. * doc/c-xtensa.texi: Likewise. * dwarf2dbg.c: Likewise. * ecoff.c: Likewise. * itbl-ops.c: Likewise. * listing.c: Likewise. * macro.c: Likewise. * po/gas.pot: Likewise. * read.c: Likewise. * struc-symbol.h: Likewise. * symbols.h: Likewise. * testsuite/gas/arc/relocs-errors.err: Likewise. * write.c: Likewise.
2017-01-23Updated Irish translation for ld and Swedish translation for gas.Nick Clifton2-1010/+1037
2017-01-20Fix potential array overrun in x86 assembler.Nick Clifton2-1/+6
* config/tc-i386.c (parse_operands): Check for operand overflow before setting the unspecified bit.
2017-01-18PR gas/20649: MIPS: Fix GOT16/LO16 reloc pairing with comdat sectionsMaciej W. Rozycki5-5/+89
Correct a regression from commit 8614eeee67f9 ("Traditional MIPS patches"), <https://sourceware.org/ml/binutils/2000-07/msg00018.html>, which caused symbols in linkonce or what is these days known as comdat sections to be treated as external for the purpose of PIC relocation generation even if their binding remains STB_LOCAL. This in turn disabled GOT16/LO16 relocation pairing with references to such symbols, as no complementing LO16 relocation is expected for external GOT16 references in the o32 ABI, which ultimately leads to link errors, e.g.: ld: comdat-reloc.o: Can't find matching LO16 reloc against `foo' for R_MIPS_GOT16 at 0x24 in section `.text.bar[bar]' as with the LD test case included with this change. Revert the special case for symbols in comdat sections then, making code actually match `adjust_reloc_syms' as indicated in its explanatory comment, and adjust calling code accordingly. Also bring back the corresponding description of what now is `s_is_linkonce', lost with commit 5f0fe04bc550 ("Improved MIPS16/MIPS32 code intermixing for gas."), <https://www.sourceware.org/ml/binutils/2006-07/msg00039.html>. gas/ PR gas/20649 * config/tc-mips.c (pic_need_relax): Don't check for linkonce symbols, remove the `segtype' parameter. (mips_frob_file, md_estimate_size_before_relax): Adjust accordingly. (s_is_linkonce): Add an explanatory comment. * testsuite/gas/mips/comdat-reloc.d: New test. * testsuite/gas/mips/comdat-reloc.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test. ld/ PR gas/20649 * testsuite/ld-mips-elf/mips-elf.exp: Add PIC comdat GOT16/LO16 relocation pairing link test.
2017-01-18[ARM] Fix the decoding of indexed element VCMLA instructionSzabolcs Nagy3-0/+31
Bit 24 of the indexed element vcmla decode mask was incorrectly left unset. This could cause incorrect disassembly of some currently undefined instructions as vcmla. Rotatation immediates were not printed correctly in the disassembly (could print 170 and 280 instead of 180 and 270). opcodes/ * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly. gas/ * testsuite/gas/arm/armv8_3-a-simd.s: Add vcmla tests. * testsuite/gas/arm/armv8_3-a-simd.d: Update.
2017-01-18Add support for processing lex source files with flex v 2.6.3Bernhard Rosenkranzer3-17/+10
PR 21059 binutils* arlex.l: Support processing with flex 2.6.3. * deflex.l: Likewise. gas * config/bfin-lex.l: Support processing with flex 2.6.3. * itbl-lex.l: Likewise.
2017-01-18Catch gas exit-via-signalNathan Sidwell7-24/+88
gas/ * as.h (gas_assert): Use abort. (as_assert): Remove. (signal_init): Declare. * as.c (main): Call signal_init. * messages.c: #include <signal.h> (as_assert): Delete. (as_abort): Allow NULL FILE. (signal_crash): New. (signal_init): Register fatal signal handlers. * configure.ac: Check for strsignal. * config.in: Rebuilt. * configure: Rebuilt.
2017-01-18Updated Swedish translation for GAS.Nick Clifton2-203/+205
2017-01-16Updated Swedish translations for GAS and LD subdirectories.Nick Clifton2-833/+861
gas * po/sv.po: Updated Swedish translation. ld * po/sv.po: Updated Swedish translation.
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist10-1/+421
gas/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq. (cpu_noarch): Add noavx512_vpopcntdq. * doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq. * testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests. * testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file. * testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto. opcodes/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS, CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VPOPCNTDQ. * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New. (i386_cpu_flags): Add cpuavx512_vpopcntdq. * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2017-01-12Prevent internal assembler errors if a stabs creation function builds an ↵Nick Clifton4-25/+81
badly formatted input string. * read.c (temp_ilp): New function. Installs a temporary input line pointer. (restore_ilp): New function. Restores the original input line pointer. * read.h (temp_ilp): Prototype. (restore_ilp): Prototype. * stabs.c (dot_func_p): Use bfd_boolean type. (generate_asm_file): Use temp_ilp and restore_ilp. (stabs_generate_asm_lineno): Likewise. (stabs_generate_asm_endfunc): Likewise.
2017-01-11Add support for x86/64 redox target.Jeremy Soller2-0/+5
bfd * config.bfd: Add entries for i686-redox and x86_64-redox. gas * configure.tgt: Add entry for i386-redox. ld * configure.tgt: Add entries for x86-redox and x86_64-redox.
2017-01-10Fix sleb128-8 regressions.Tristan Gingold3-2/+7
gas/ * testsuite/gas/all/sleb128-8.d: Adjust test. * testsuite/gas/all/gas.exp (test_cond): Likewise.
2017-01-10Updated Swedish translations for GAS and LDNick Clifton2-700/+719
2017-01-10This patch ensure same output for sleb128 with large number.Tristan Gingold5-3/+29
gas/ * read.c (emit_leb128_expr): Extended unsigned big number for sleb128. * testsuite/gas/all/gas.exp (test_cond): Add sleb128-8 test. * testsuite/gas/all/sleb128.d: New test. * testsuite/gas/all/sleb128.s: New test source.
2017-01-09RISC-V/GAS: Support more relocs against constant addressesAndrew Waterman2-3/+8
Previously, some pseudoinstructions like "call" only accepted symbolic addresses and rejected constant addresses with an esoteric internal error. This patch enables them by deferring application of constant relocations to md_apply_fix, rather than eagerly applying them during instruction assembly. gas/ChangeLog 2017-01-09 Andrew Waterman <andrew@sifive.com> * config/tc-riscv.c (append_insn): Don't eagerly apply relocations against constants. (md_apply_fix): Mark relocations against constants as "done."
2017-01-09RISC-V/GAS: Improve handling of invalid relocsAndrew Waterman2-1/+15
TLS relocs against constants previously segfaulted, and illegal symbol subtractions were silently ignored. The previous behavior was to segfault. gas/ChangeLog 2017-01-09 Andrew Waterman <andrew@sifive.com> * config/tc-riscv.c (md_apply_fix): Report TLS relocations against constants. Report disallowed symbol subtractions.
2017-01-09Remove some custom sections from RISC-V's default linker scriptsPalmer Dabbelt1-0/+7
This was added so compressed loads could have smaller offsets for accessing the data section, but the result was that writable sections ended up in INITIAL_READONLY_SECTIONS. This is a bad idea. The fix is to just remove this micro-optimization. Thanks to Alan Morda for finding the problem! ld/ChangeLog 2017-01-09 Palmer Dabbelt <palmer@dabbelt.com> Kito Cheng <kito.cheng@gmail.com> * emulparams/elf32lriscv-defs.sh (INITIAL_READONLY_SECTIONS): Removed. (SDATA_START_SYMBOLS): Likewise.
2017-01-09Add Swedish translation for GAS.Nick Clifton4-2/+19967
* po/sv.po: New Swedish translation. * configure.ac (ALL_LINGUAS): Add sv. * configure: Regenerate.
2017-01-09RISC-V/GAS: Correct branch relaxation for weak symbols.Andrew Waterman2-0/+6
* config/tc-riscv.c (relaxed_branch_length): Use the long sequence when the target is a weak symbol.
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy5-0/+33
The weaker release consistency support of ARMv8.3-A is allowed as an optional extension for ARMv8.2-A, so separate command line option and feature flag is added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on. opcodes/ * aarch64-tbl.h (RCPC, RCPC_INSN): Define. (aarch64_opcode_table): Use RCPC_INSN. include/ * opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define. (AARCH64_ARCH_V8_3): Update. gas/ * config/tc-aarch64.c (aarch64_features): Add rcpc. * doc/c-aarch64.texi (AArch64 Extensions): Document rcpc. * testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ... * testsuite/gas/aarch64/ldst-rcpc.d: This. * testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ... * testsuite/gas/aarch64/ldst-rcpc.s: This. * testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
2017-01-04When configuring GAS treat as sparcv9 target the same way as a sparc64 target.Norm Jacobs2-1/+6
PR gas/20992 * configure.tgt: Treat sparcv9 as sparc64.
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng2-2/+19
gas * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA extension. (riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is enabled and no other ABI is specified. include * opcode/riscv-opc.h: Add support for the "q" ISA extension. opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA extension. * riscv-opcodes/all-opcodes: Likewise.
2017-01-03Fix PRU GAS for 32-bit hostsDimitar Dimitrov2-7/+18
The PRU GAS port I originally submitted does not build on 32bit hosts. This patch fixes it by aligning md_number_to_chars's definition with the global declaration in tc.h. Here is the original bug report I got: https://github.com/rcn-ee/repos/pull/23#issuecomment-269915175 * config/tc-pru.c (md_number_to_chars): Fix parameter to be valueT, as declared in tc.h. (md_apply_fix): Fix to work on 32-bit hosts. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2017-01-02Update year range in copyright notice of all files.Alan Modra560-562/+566
2017-01-02ChangeLog rotationAlan Modra2-6012/+6026
2016-12-31PRU GAS PortDimitar Dimitrov36-0/+2830
* NEWS: Mention new PRU target. * Makefile.am: Add PRU target. * config/obj-elf.c: Ditto. * configure.tgt: Ditto. * config/tc-pru.c: New file. * config/tc-pru.h: New file. * doc/Makefile.am: Add documentation for PRU GAS port. * doc/all.texi, Ditto. * doc/as.texinfo: Ditto. * doc/c-pru.texi: Document PRU GAS options. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. * testsuite/gas/pru/alu.d: New file for PRU GAS testsuite. * testsuite/gas/pru/alu.s: Ditto. * testsuite/gas/pru/branch.d: Ditto. * testsuite/gas/pru/branch.s: Ditto. * testsuite/gas/pru/illegal.l: Ditto. * testsuite/gas/pru/illegal.s: Ditto. * testsuite/gas/pru/ldi.d: Ditto. * testsuite/gas/pru/ldi.s: Ditto. * testsuite/gas/pru/ldst.d: Ditto. * testsuite/gas/pru/ldst.s: Ditto. * testsuite/gas/pru/loop.d: Ditto. * testsuite/gas/pru/loop.s: Ditto. * testsuite/gas/pru/misc.d: Ditto. * testsuite/gas/pru/misc.s: Ditto. * testsuite/gas/pru/pru.exp: Ditto. * testsuite/gas/pru/pseudo.d: Ditto. * testsuite/gas/pru/pseudo.s: Ditto. * testsuite/gas/pru/warn_reglabel.l: Ditto. * testsuite/gas/pru/warn_reglabel.s: Ditto. * testsuite/gas/pru/xfr.d: Ditto. * testsuite/gas/pru/xfr.s: Ditto. * testsuite/gas/lns/lns.exp: Mark lns-common-1-alt variant for PRU. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki6-0/+79
Add ASMACRO instruction support as per the MIPS16e ASE architecture specifications [1][2], completing MIPS16e instruction set support. [1] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00076, Revision 2.63, July 16, 2013, Section 4.1 "MIPS16e Instruction Descriptions", p. 65 [2] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e Application-Specific Extension to the MIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00077, Revision 2.60, June 25, 2008, Section 1.1 "MIPS16e Instruction Descriptions", p. 66 include/ * opcode/mips.h: Document `0', `1', `2', `3', `4' and `s' operand codes. opcodes/ * mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3', `4' and `s' operand codes. (mips16_opcodes): Add "asmacro" entry. binutils/ * testsuite/binutils-all/mips/mips16-extend-insn.d: Update for ASMACRO support. gas/ * testsuite/gas/mips/mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test. * testsuite/gas/mips/mips16-asmacro.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-23MIPS16: Simplify extended operand handlingMaciej W. Rozycki2-1/+6
Simplify extended operand handling and only specially process immediates which require bit shuffling, using the generic operand insertion and extraction handlers for the '<' (5-bit shift amount) operand code in particular. Require the least significant bit of all extended operand forms to be (artificially) set to 0 for their special processing to trigger. gas/ * config/tc-mips.c (mips16_immed): Limit `mips16_immed_extend' use to operands whose LSB position is zero. opcodes/ * mips-dis.c (print_mips16_insn_arg): Simplify processing of extended operands. * mips16-opc.c (decode_mips16_operand): Switch the extended form of the `<' operand type to LSB position 22.
2016-12-23MIPS16/GAS: Clean up invalid unextended operand handlingMaciej W. Rozycki9-2/+245
Bail out right away when an unextended instruction encoding is required either with the use of a `.t' suffix or by means of `.set noautoextend', however an operand supplied requires the extended instruction form to be used. This is to avoid messing up with the internal state of the assembler, even though no actual failures are known to happen as a result. Add test cases for the situation concerned. gas/ * config/tc-mips.c (match_mips16_insn): Don't update `forced_insn_length' or the instruction opcode if an operand requires an extended instruction form, but an unextended one has been requested. * testsuite/gas/mips/mips16-relax-unextended-1.d: New test. * testsuite/gas/mips/mips16-relax-unextended-2.d: New test. * testsuite/gas/mips/mips16-relax-unextended-1.l: New stderr output. * testsuite/gas/mips/mips16-relax-unextended-2.l: New stderr output. * testsuite/gas/mips/mips16-relax-unextended-1.s: New test source. * testsuite/gas/mips/mips16-relax-unextended-2.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki2-5/+11
Replace `0' and `4' operand codes with `.' and `F' respectively to free up the `0'-`4' consecutive range. No functional change. gas/ * config/tc-mips.c (mips16_macro_build): Replace `0' and `4' operand codes with `.' and `F' respectively. (mips16_macro): Likewise. include/ * opcode/mips.h: Replace `0' and `4' operand codes with `.' and `F' respectively. opcodes/ * mips16-opc.c (decode_mips16_operand): Replace `0' and `4' operand codes with `.' and `F' respectively. (mips16_opcodes): Likewise.
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