| Age | Commit message (Collapse) | Author | Files | Lines |
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Before this commit we didn't cleanly support CFI directives because the
internal offsets used to get relaxed which broke them. This patch
significantly reworks how we handle linker relaxations:
* DWARF is now properly supported
* There is a ".option norelax" to disable relaxations, for when users
write assembly that can't be relaxed (if it's to be later patched up,
for example).
* There is an additional _RELAX relocation that specifies when previous
relocations can be relaxed.
We're in the process of documenting the RISC-V ELF ABI, which will
include documentation of our relocations
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
but we expect that this relocation set will remain ABI compatible in the
future (ie, it's safe to release).
Thanks to Kuan-Lin Chen for figuring out how to correctly relax the
debug info!
include/
* elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32.
bfd/
* reloc.c (BFD_RELOC_RISCV_TPREL_I): New relocation.
(BFD_RELOC_RISCV_TPREL_S): Likewise.
(BFD_RELOC_RISCV_RELAX): Likewise.
(BFD_RELOC_RISCV_CFA): Likewise.
(BFD_RELOC_RISCV_SUB6): Likewise.
(BFD_RELOC_RISCV_SET8): Likewise.
(BFD_RELOC_RISCV_SET8): Likewise.
(BFD_RELOC_RISCV_SET16): Likewise.
(BFD_RELOC_RISCV_SET32): Likewise.
* elfnn-riscv.c (perform_relocation): Handle the new
relocations.
(_bfd_riscv_relax_tls_le): Likewise.
(_bfd_riscv_relax_align): Likewise.
(_bfd_riscv_relax_section): Likewise.
(howto_table): Likewise.
(riscv_reloc_map): Likewise.
(relax_func_t): New type.
(_bfd_riscv_relax_call): Add reserve_size argument, which
controls the maximal offset pessimism. Correct type of max_alignment.
(_bfd_riscv_relax_lui): Likewise.
(_bfd_riscv_relax_tls_le): Likewise.
(_bfd_riscv_relax_align): Likewise.
(_bfd_riscv_relax_section): Compute the required reserve size
when relocating and use it to when calling relax_func.
* bfd-in2.h: Regenerate.
* libbfd.h: Likewise.
gas/
* config/tc-riscv.c (riscv_set_options): Add relax.
(riscv_opts): Likewise.
(s_riscv_option): Add relax and norelax.
(riscv_apply_const_reloc): New function.
(append_insn): Move constant relocation handling to
riscv_apply_const_reloc.
(md_pcrel_from): Likewise.
(parse_relocation): Skip BFD_RELOC_UNUSED.
(md_pcrel_from): Handle BFD_RELOC_RISCV_SUB6,
BFD_RELOC_RISCV_RELAX, BFD_RELOC_RISCV_CFA.
(md_apply_fix): Likewise.
(riscv_pre_output_hook): New function.
* config/tc-riscv.h (md_pre_output_hook): Define.
(riscv_pre_output_hook): Declare.
(DWARF_CIE_DATA_ALIGNMENT): Always -4.
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This is a mixed bag of format changes:
* Replacing constants with macros (0xffffffff with MINUS_ONE, for
example). There's one technically functional change in here (some
MINUS_ONEs are changed to 0), but it only changes the behavior of an
otherwise-unused field.
* Using 0 instead of 0x0 in the relocation table.
* There were some missing spaces before parens, the spaces have been
added.
* A handful of comments are now more descriptive.
* A bunch of whitespace-only changes, mostly alignment and brace
newlines.
bfd/
* elfnn-riscv.c: Formatting and comment fixes throughout.
* elfxx-riscv.c: Likewise.
(howto_table): Change the src_mask field from MINUS_ONE to 0 for
R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPREL32,
R_RISCV_TLS_DTPREL64, R_RISCV_TLS_TPREL32, R_RISCV_TLS_TPREL64.
opcodes/
* riscv-opc.c: Formatting fixes.
gas/
* config/tc-riscv.c: Formatting and comment fixes throughout.
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Complement commit c9775dde3277 ("MIPS16: Add R_MIPS16_PC16_S1 branch
relocation support)" and report an assembly error when a relocation is
required for an instruction, currently a branch only, that has been
forced to use its unextended encoding, either with the use of an
explicit `.t' mnemonic suffix, or by means of `.set noautoextend' being
active, fixing an assertion failure currently caused instead.
gas/
* config/tc-mips.c (md_convert_frag): Report an error instead of
asserting on `ext'.
* testsuite/gas/mips/mips16-branch-unextended-1.d: New test.
* testsuite/gas/mips/mips16-branch-unextended-2.d: New test.
* testsuite/gas/mips/mips16-branch-unextended-1.s: New test
source.
* testsuite/gas/mips/mips16-branch-unextended-2.s: New test.
* testsuite/gas/mips/mips16-branch-unextended.l: New stderr
output.
* testsuite/gas/mips/mips.exp: Run the new tests.
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Fix the annotation of SP-relative SD instructions incorrectly marked as
reading from the PC rather than SP, which in turn prevented their 16-bit
forms from being scheduled into jump delay slots. This bug has been
there since forever.
opcodes/
* mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
`pinfo2' with SP-relative "sd" entries.
gas/
* testsuite/gas/mips/mips16-sprel-swap.d: New test.
* testsuite/gas/mips/mips16-sprel-swap.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
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The internal CN register representation for coprocessor fields used in aarch64
sys, sysl instructions are removed in this patch.
After the change, those fields are represented as immediate. Related checks are
added as well.
opcodes/
* aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
qualifier.
(operand_general_constraint_met_p): Remove case for CP_REG.
(aarch64_print_operand): Print CRn, CRm operand using imm field.
* aarch64-tbl.h (QL_SYS): Use CR qualifier.
(QL_SYSL): Likewise.
(aarch64_opcode_table): Change CRn, CRm operand class and type.
* aarch64-opc-2.c : Regenerate.
* aarch64-asm-2.c : Likewise.
* aarch64-dis-2.c : Likewise.
include/
* opcode/aarch64.h (aarch64_operand_class): Remove
AARCH64_OPND_CLASS_CP_REG.
(enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn,
AARCH64_OPND_Cm to AARCH64_OPND_CRm.
(aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier.
gas/
* config/tc-aarch64.c (AARCH64_REG_TYPES): Remove CN register.
(get_reg_expected_msg): Remove CN register case.
(parse_operands): rewrite parser for CRn, CRm operand.
(reg_names): Remove CN register.
* testsuite/gas/aarch64/diagnostic.s: Add a new test case.
* testsuite/gas/aarch64/diagnostic.l: Adjust error message.
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gas/
* gas/testsuite/gas/aarch64/addsub.d: Support ILP32 mode.
* gas/testsuite/gas/aarch64/advsimd-across.d: Likewise.
* gas/testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise.
* gas/testsuite/gas/aarch64/advsimd-fp16.d: Likewise.
* gas/testsuite/gas/aarch64/advsimd-misc.d: Likewise.
* gas/testsuite/gas/aarch64/advsisd-copy.d: Likewise.
* gas/testsuite/gas/aarch64/advsisd-misc.d: Likewise.
* gas/testsuite/gas/aarch64/alias.d: Likewise.
* gas/testsuite/gas/aarch64/armv8-ras-1.d: Likewise.
* gas/testsuite/gas/aarch64/b_1.d: Likewise.
* gas/testsuite/gas/aarch64/beq_1.d: Likewise.
* gas/testsuite/gas/aarch64/bitfield-dump: Likewise.
* gas/testsuite/gas/aarch64/bitfield-no-aliases.d: Likewise.
* gas/testsuite/gas/aarch64/codealign.d: Likewise.
* gas/testsuite/gas/aarch64/codealign_1.d: Likewise.
* gas/testsuite/gas/aarch64/crc32-directive.d: Likewise.
* gas/testsuite/gas/aarch64/crc32.d: Likewise.
* gas/testsuite/gas/aarch64/crypto-directive.d: Likewise.
* gas/testsuite/gas/aarch64/crypto.d: Likewise.
* gas/testsuite/gas/aarch64/dwarf.d: Likewise.
* gas/testsuite/gas/aarch64/float-fp16.d: Likewise.
* gas/testsuite/gas/aarch64/floatdp2.d: Likewise.
* gas/testsuite/gas/aarch64/fp-armv8_3.d: Likewise.
* gas/testsuite/gas/aarch64/fp-const0-parse.d: Likewise.
* gas/testsuite/gas/aarch64/fp_cvt_int.d: Likewise.
* gas/testsuite/gas/aarch64/fpmov.d: Likewise.
* gas/testsuite/gas/aarch64/inst-directive.d: Likewise.
* gas/testsuite/gas/aarch64/ldr_1.d: Likewise.
* gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Likewise.
* gas/testsuite/gas/aarch64/ldst-exclusive.d: Likewise.
* gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.d: Likewise.
* gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d: Likewise.
* gas/testsuite/gas/aarch64/ldst-reg-pair.d: Likewise.
* gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d: Likewise.
* gas/testsuite/gas/aarch64/ldst-reg-uns-imm.d: Likewise.
* gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.d: Likewise.
* gas/testsuite/gas/aarch64/lor-directive.d: Likewise.
* gas/testsuite/gas/aarch64/lor.d: Likewise.
* gas/testsuite/gas/aarch64/lse-atomic.d: Likewise.
* gas/testsuite/gas/aarch64/mapmisc.d: Likewise.
* gas/testsuite/gas/aarch64/mov-no-aliases.d: Likewise.
* gas/testsuite/gas/aarch64/mov.d: Likewise.
* gas/testsuite/gas/aarch64/movi.d: Likewise.
* gas/testsuite/gas/aarch64/movw_label.d: Likewise.
* gas/testsuite/gas/aarch64/msr.d: Likewise.
* gas/testsuite/gas/aarch64/neon-fp-cvt-int.d: Likewise.
* gas/testsuite/gas/aarch64/neon-frint.d: Likewise.
* gas/testsuite/gas/aarch64/neon-ins.d: Likewise.
* gas/testsuite/gas/aarch64/neon-not.d: Likewise.
* gas/testsuite/gas/aarch64/neon-vfp-reglist-post.d: Likewise.
* gas/testsuite/gas/aarch64/neon-vfp-reglist.d: Likewise.
* gas/testsuite/gas/aarch64/no-aliases.d: Likewise.
* gas/testsuite/gas/aarch64/optional.d: Likewise.
* gas/testsuite/gas/aarch64/pac.d: Likewise.
* gas/testsuite/gas/aarch64/pan-directive.d: Likewise.
* gas/testsuite/gas/aarch64/pan.d: Likewise.
* gas/testsuite/gas/aarch64/rdma-directive.d: Likewise.
* gas/testsuite/gas/aarch64/rdma.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_g0.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_g0_nc.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_g1.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_hi12.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12-1.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-tlsldm-1.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-tlsldm-page-1.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-tlsldm_lo12_nc-1.d: Likewise.
* gas/testsuite/gas/aarch64/shifted.d: Likewise.
* gas/testsuite/gas/aarch64/sve.d: Likewise.
* gas/testsuite/gas/aarch64/symbol.d: Likewise.
* gas/testsuite/gas/aarch64/sysreg-1.d: Likewise.
* gas/testsuite/gas/aarch64/sysreg-2.d: Likewise.
* gas/testsuite/gas/aarch64/sysreg-3.d: Likewise.
* gas/testsuite/gas/aarch64/sysreg.d: Likewise.
* gas/testsuite/gas/aarch64/system-2.d: Likewise.
* gas/testsuite/gas/aarch64/system-3.d: Likewise.
* gas/testsuite/gas/aarch64/system.d: Likewise.
* gas/testsuite/gas/aarch64/tbz_1.d: Likewise.
* gas/testsuite/gas/aarch64/tlbi_op.d: Likewise.
* gas/testsuite/gas/aarch64/tls.d: Likewise.
* gas/testsuite/gas/aarch64/uao-directive.d: Likewise.
* gas/testsuite/gas/aarch64/uao.d: Likewise.
* gas/testsuite/gas/aarch64/virthostext-directive.d: Likewise.
* gas/testsuite/gas/aarch64/virthostext.d: Likewise.
* gas/testsuite/gas/aarch64/adr_1.d: Restrict test under -mabi=lp64.
* gas/testsuite/gas/aarch64/int-insns.d: Likewise.
* gas/testsuite/gas/aarch64/programmer-friendly.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-data.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_g1_nc.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_g2.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst16.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst32.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst64.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst8.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst16.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst32.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst64.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst8.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-gotoff_g0_nc.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-gotoff_g1.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-gottprel_g0_nc.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-gottprel_g1.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-insn.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-tlsdesc_off_g0_nc.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-tlsdesc_off_g1.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-tlsgd_g0_nc.d: Likewise.
* gas/testsuite/gas/aarch64/reloc-tlsgd_g1.d: Likewise.
* gas/testsuite/gas/aarch64/tail_padding.d: Likewise.
* gas/testsuite/gas/aarch64/tls-desc.d: Likewise.
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This code has never been used throughout the repository history, and
likely not before either, as due to the assymetry of MIPS16 instruction
set encoding there are no 32-bit shift operations having their immediate
shift count placed in the position of the usual `rx' instruction field.
gas/
* config/tc-mips.c (mips16_macro_build) <'>'>: Remove case.
include/
* opcode/mips.h: Remove references to `>' operand code.
opcodes/
* mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
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Make the `e' operand code used with raw EXTEND instructions use the
hexadecimal rather than decimal format, for consistency with what is
actually produced by code in `print_insn_mips16' dedicated to EXTEND
disassembly. Due to that special handling the operand code is only
interpreted for assembly however, which accepts either format either
way, so there is no functional change here.
opcodes/
* mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
than UINT.
gas/
* testsuite/gas/mips/mips16-extend.d: New test.
* testsuite/gas/mips/mips16-extend.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
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Fix a commit a9752fdf8398 ("[ARC] Sync cpu names with the ones accepted
by GCC.") build regression:
cc1: warnings being treated as errors
.../gas/config/tc-arc.c: In function 'arc_show_cpu_list':
.../gas/config/tc-arc.c:3452: error: declaration of 'spaces' shadows a global declaration
.../gas/../include/libiberty.h:248: error: shadowed declaration is here
make[4]: *** [tc-arc.o] Error 1
in a way following commit 91d6fa6a035c ("Add -Wshadow to the gcc command
line options used when compiling the binutils.").
gas/
* config/tc-arc.c (arc_show_cpu_list): Rename `spaces' local
variable to `space_buf'.
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Fix a commit 008a97eff0ca ("[GAS][ARM]Generate unpredictable warning for
pc used in data processing instructions with register-shifted register
operand.") build regression:
cc1: warnings being treated as errors
.../gas/config/tc-arm.c: In function 'encode_arm_shift':
.../gas/config/tc-arm.c:7439: error: declaration of 'index' shadows a global declaration
/usr/include/string.h:303: error: shadowed declaration is here
make[4]: *** [tc-arm.o] Error 1
in a way following commit 91d6fa6a035c ("Add -Wshadow to the gcc command
line options used when compiling the binutils.").
gas/
* config/tc-arm.c (encode_arm_shift): Rename `index' local
variable to `op_index'.
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config/
* acx.m4: Import from gcc.
* bootstrap-asan.mk: Likewise.
* multi.m4: Likewise.
/
* configure: Regnerate.
gas/
* configure: Regnerate.
ld/
* configure: Regnerate.
libiberty/
* configure: Regnerate.
zlib/
* configure: Regnerate.
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Replace a global `mips_opts.isa' reference in `is_opcode_valid' and use
a local copy just made in `isa'. No functional change.
gas/
* config/tc-mips.c (is_opcode_valid): Use local `isa'
consistently.
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number of spaces.
PR gas/20901
* read.c (s_space): Place an upper limit on the number of spaces
generated.
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produced by the assembler.
PR gas/20896
* testsuite/gas/mmix/err-byte1.s: Adjust expected warning messages
to account for patch to next_char_of_string.
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PR gas/20902
* read.c (next_char_of_string): Do end advance past the end of the
buffer.
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PR gas/20904
* as.h (SKIP_ALL_WHITESPACE): New macro.
* expr.c (operand): Use it.
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Add support for VCMLA and VCADD advanced SIMD complex number instructions.
The command line option is -march=armv8.3-a+fp16+simd for enabling all
instructions.
In arm-dis.c the formatting syntax was abused a bit to select between
0 vs 90 or 180 vs 270 or 90 vs 270 based on a bit value instead of
duplicating entries in the opcode table.
gas/
* config/tc-arm.c (do_vcmla, do_vcadd): Define.
(neon_scalar_for_vcmla): Define.
(enum operand_parse_code): Add OP_IROT1 and OP_IROT2.
(NEON_ENC_TAB): Add DDSI and QQSI variants.
(insns): Add vcmla and vcadd.
* testsuite/gas/arm/armv8_3-a-simd.d: New.
* testsuite/gas/arm/armv8_3-a-simd.s: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.d: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.l: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.s: New.
opcodes/
* arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
(print_insn_coprocessor): Add 'V' format for neon D or Q regs.
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gas/
2016-12-05 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textauxregister-1.d: New file.
* testsuite/gas/arc/textauxregister-1.s: Likewise.
* testsuite/gas/arc/textcondcode-err.s: Likewise.
* testsuite/gas/arc/textcoreregister-err.s: Likewise.
* config/tc-arc.c (tokenize_extregister): Return bfd_boolean,
don't check second argument of extension auxiliary register for
signess.
(arc_extcorereg): Consider the return of tokenize_extregister
function call.
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Add support for VJCVT javascript conversion instruction.
gas/
* config/tc-arm.c (arm_ext_v8_3, do_vjcvt): Define.
(insns): Add vjcvt.
* testsuite/gas/aarch64/armv8_3-a-fp.s: New.
* testsuite/gas/aarch64/armv8_3-a-fp.d: New.
* testsuite/gas/aarch64/armv8_3-a-fp-bad.s: New.
* testsuite/gas/aarch64/armv8_3-a-fp-bad.d: New.
* testsuite/gas/aarch64/armv8_3-a-fp-bad.l: New.
opcodes/
* arm-dis.c (coprocessor_opcodes): Add vjcvt.
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ARMv8.3 is an architectural extension of ARMv8. Add the
feature macro and -march=armv8.3-a gas command line option
for the ARM target.
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
gas/
* config/tc-arm.c (arm_archs): Add "armv8.3-a".
* doc/c-arm.texi (-march): Add "armv8.3-a".
include/
* opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New.
(ARM_ARCH_V8_3A): New.
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gas/
2016-12-02 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/cpu-em-err.s: New file.
* testsuite/gas/arc/cpu-em4-err.s: Likewise.
* testsuite/gas/arc/cpu-fpuda-err.s: Likewise.
* testsuite/gas/arc/cpu-hs-err.s: Likewise.
* testsuite/gas/arc/cpu-quarkse-err.s: Likewise.
* testsuite/gas/arc/noargs_a7.s: Add .cpu.
* config/tc-arc.c (ARC_CPU_TYPE_A6xx): Define.
(ARC_CPU_TYPE_A7xx): Likewise.
(ARC_CPU_TYPE_AV2EM): Likewise.
(ARC_CPU_TYPE_AV2HS): Likewise.
(cpu_types): Update list of known CPU names.
(arc_show_cpu_list): New function.
(md_show_usage): Print accepted CPU names.
(cl_features): New variable.
(arc_select_cpu): Use cl_features.
(arc_option): Allow various .cpu names.
(md_parse_option): Set cl_features.
* doc/c-arc.texi: Update -mcpu and .cpu documentation.
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* configure.ac: Add fuchsia to targets that use ELF.
* configure: Regenerated.
bfd * configure.tgt: Add support for fuchsia (OS).
gas * configure.tgt: Add support for fuchsia (OS).
ld * Makefile.am: Add dependency information for earmelf_fuchsia.c.
* Makefile.in: Regenerate.
* configure.tgt: Add support for aarch64-*-fuchsia, arm*-*-fuchsia*, and
x86_64-*-fuchsia* targets.
* emulparams/armelf_fuchsia.sh: New file.
* emulparams/armelfb_fuchsia.sh: New file.
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PR gas/20898
* app.c (do_scrub_chars): Do not attempt to unget EOF.
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created.
PR gas/20897
* subsegs.c (subsegs_print_statistics): Do nothing if no output
file was created.
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PR gas/20895
* symbols.c (resolve_symbol_value): Gracefully handle erroneous
symbolic expressions.
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gas/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (find_opcode_match): New function argument
errmsg.
(assemble_tokens): Collect and report the eventual error message
found during opcode matching process.
* testsuite/gas/arc/lpcount-err.s: New file.
* testsuite/gas/arc/add_s-err.s: Update error message.
opcode/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (insert_ra_chk): New function.
(insert_rb_chk): Likewise.
(insert_rad): Update text error message.
(insert_rcd): Likewise.
(insert_rhv2): Likewise.
(insert_r0): Likewise.
(insert_r1): Likewise.
(insert_r2): Likewise.
(insert_r3): Likewise.
(insert_sp): Likewise.
(insert_gp): Likewise.
(insert_pcl): Likewise.
(insert_blink): Likewise.
(insert_ilink1): Likewise.
(insert_ilink2): Likewise.
(insert_ras): Likewise.
(insert_rbs): Likewise.
(insert_rcs): Likewise.
(insert_simm3s): Likewise.
(insert_rrange): Likewise.
(insert_fpel): Likewise.
(insert_blinkel): Likewise.
(insert_pcel): Likewise.
(insert_nps_3bit_dst): Likewise.
(insert_nps_3bit_dst_short): Likewise.
(insert_nps_3bit_src2_short): Likewise.
(insert_nps_bitop_size_2b): Likewise.
(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
(RA_CHK): Define.
(RB): Adjust.
(RB_CHK): Define.
(RC): Adjust.
* arc-dis.c (print_insn_arc): Add LOAD and STORE class.
* arc-tbl.h (div, divu): All instructions are DIVREM class.
Change first insn argument to check for LP_COUNT usage.
(rem): Likewise.
(ld, ldd): All instructions are LOAD class. Change first insn
argument to check for LP_COUNT usage.
(st, std): All instructions are STORE class.
(mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
Change first insn argument to check for LP_COUNT usage.
(mov): All instructions are MOVE class. Change first insn
argument to check for LP_COUNT usage.
include/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
instruction classes.
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While decoding 32-bit XOP instructions, 64 bit registers names are printed.
This patch fixes this by ignoring REX_B bit in 32-bit mode.
opcodes/
PR binutils/20637
* i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
instructions.
gas/
PR binutils/20637
* testsuite/gas/i386/xop32reg.d: New file.
* testsuite/gas/i386/xop32reg.s: New file.
* testsuite/gas/i386/i386.exp: Run new test.
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* arparse.y: Fix spelling in comments.
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* config/bfin-lex.l: Fix spelling in comments.
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* testsuite/gas/all/gas.exp: Fix spelling in comments.
* testsuite/gas/cris/cris.exp: Fix spelling in comments.
* testsuite/gas/hppa/basic/basic.exp: Fix spelling in comments.
* testsuite/gas/hppa/parse/parse.exp: Fix spelling in comments.
* testsuite/gas/hppa/reloc/reloc.exp: Fix spelling in comments.
* testsuite/gas/sh/arch/arch.exp: Fix spelling in comments.
* testsuite/gas/tic4x/tic4x.exp: Fix spelling in comments.
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* testsuite/gas/arm/local_function.d: Fix spelling in comments.
* testsuite/gas/arm/req.s: Fix spelling in comments.
* testsuite/gas/arm/vfp1.s: Fix spelling in comments.
* testsuite/gas/arm/vfp1_t2.s: Fix spelling in comments.
* testsuite/gas/arm/vfp1xD.s: Fix spelling in comments.
* testsuite/gas/arm/vfp1xD_t2.s: Fix spelling in comments.
* testsuite/gas/mcore/allinsn.s: Fix spelling in comments.
* testsuite/gas/mips/24k-triple-stores-5.s: Fix spelling in comments.
* testsuite/gas/mips/delay.d: Fix spelling in comments.
* testsuite/gas/mips/nodelay.d: Fix spelling in comments.
* testsuite/gas/mips/r5900-full.s: Fix spelling in comments.
* testsuite/gas/mips/r5900.s: Fix spelling in comments.
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* as.h: Fix spelling in comments.
* config/obj-ecoff.c: Fix spelling in comments.
* config/obj-macho.c: Fix spelling in comments.
* config/tc-aarch64.c: Fix spelling in comments.
* config/tc-arc.c: Fix spelling in comments.
* config/tc-arm.c: Fix spelling in comments.
* config/tc-avr.c: Fix spelling in comments.
* config/tc-cr16.c: Fix spelling in comments.
* config/tc-epiphany.c: Fix spelling in comments.
* config/tc-frv.c: Fix spelling in comments.
* config/tc-hppa.c: Fix spelling in comments.
* config/tc-hppa.h: Fix spelling in comments.
* config/tc-i370.c: Fix spelling in comments.
* config/tc-m68hc11.c: Fix spelling in comments.
* config/tc-m68k.c: Fix spelling in comments.
* config/tc-mcore.c: Fix spelling in comments.
* config/tc-mep.c: Fix spelling in comments.
* config/tc-metag.c: Fix spelling in comments.
* config/tc-mips.c: Fix spelling in comments.
* config/tc-mn10200.c: Fix spelling in comments.
* config/tc-mn10300.c: Fix spelling in comments.
* config/tc-nds32.c: Fix spelling in comments.
* config/tc-nios2.c: Fix spelling in comments.
* config/tc-ns32k.c: Fix spelling in comments.
* config/tc-pdp11.c: Fix spelling in comments.
* config/tc-ppc.c: Fix spelling in comments.
* config/tc-riscv.c: Fix spelling in comments.
* config/tc-rx.c: Fix spelling in comments.
* config/tc-score.c: Fix spelling in comments.
* config/tc-score7.c: Fix spelling in comments.
* config/tc-sparc.c: Fix spelling in comments.
* config/tc-tic54x.c: Fix spelling in comments.
* config/tc-vax.c: Fix spelling in comments.
* config/tc-xgate.h: Fix spelling in comments.
* config/tc-xtensa.c: Fix spelling in comments.
* config/tc-z80.c: Fix spelling in comments.
* dwarf2dbg.c: Fix spelling in comments.
* input-file.h: Fix spelling in comments.
* itbl-ops.c: Fix spelling in comments.
* read.c: Fix spelling in comments.
* stabs.c: Fix spelling in comments.
* symbols.c: Fix spelling in comments.
* write.c: Fix spelling in comments.
* testsuite/gas/all/itbl-test.c: Fix spelling in comments.
* testsuite/gas/tic4x/opclasses.h: Fix spelling in comments.
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This patch fixes two problems in the SPARC assembler:
- The diagnostic message
Error: Illegal operands: Immediate value in cbcond is out of range.
is incorrectly issued for non-CBCOND instructions that feature a
simm5 immediate field, such as MPMUL, MONTMUL, etc.
- When an invalid immediate operand is used in a CBCOND
instruction, two redundant error messages are issued to the
user, the second due to a stale fixup (this happens since
commit 85024cd8bcb93f4112470ecdbd6c10fc2aea724f).
Some diagnostic tests for the CBCOND instructions are also
included in the patch.
Tested in both sparc64-linux-gnu and sparcv9-linux-gnu targets.
gas/ChangeLog:
2016-11-25 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_ip): Avoid emitting a cbcond error
messages for non-cbcond instructions.
* testsuite/gas/sparc/cbcond-diag.s: New file.
* testsuite/gas/sparc/cbcond-diag.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run cbcond-diag tests.
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gas/ChangeLog:
2016-11-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/sparc.exp (gas_64_check): Make sure the
hwcaps-bump test is run with 64-bit objects.
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gdb/ChangeLog:
* config/tc-riscv.c: Add missing break.
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bfd/
* po/BLD-POTFILES.in: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
gas/
* po/POTFILES.in: Regenerate.
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All changes are limited to comments, and no run-time behavior is
affected.
bfd/ChangeLog:
2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
* warning.m4: Fix spelling in comments.
* configure.ac: Fix spelling in comments.
* configure: Regenerate.
binutils/ChangeLog:
2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
* configure: Regenerate.
gdb/ChangeLog:
2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
* configure.ac: Fix spelling in comments.
* configure: Regenerate.
gas/ChangeLog:
2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
* configure: Regenerate.
gold/ChangeLog:
2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
* configure: Regenerate.
gprof/ChangeLog:
2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
* configure: Regenerate.
ld/ChangeLog:
2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
* configure: Regenerate.
opcodes/ChangeLog:
2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
* configure: Regenerate.
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When the assembler finds an instruction which is part of a higher
opcode architecture it bumps the current opcode architecture. For
example:
$ echo "mwait" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
However, when two instructions pertaining to the same opcode
architecture but associated to different SPARC hardware capabilities
are found in the input stream, and no GAS architecture is specified in
the command line, the assembler bangs:
$ echo "mwait; wr %g0,%g1,%mcdper" | as -bump
{standard input}: Assembler messages:
{standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
{standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr".
... and it should'nt, as WRMCDPER pertains to the same architecture
level than MWAIT.
This patch fixes this by extending the definition of sparc opcode
architectures to contain a set of hardware capabilities and making the
assembler to take these capabilities into account when updating the
set of allowed hwcaps when an architecture bump is triggered by some
instruction.
This way, hwcaps associated to architecture levels are maintained in
opcodes, while the assembler keeps the flexibiity of defining GAS
architectures including additional hwcaps (like -Asparcfmaf or the
v8plus* variants).
A test covering this failure case is included.
gas/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
opcodes/sparc-opc.c.
(sparc_arch): Clarify the new role of the hwcap_allowed and
hwcap2_allowed fields.
(sparc_arch_table): Remove HWS_* and HWS2_* instances from
hwcap_allowed and hwcap2_allowed respectively.
(md_parse_option): Include the opcode arch hwcaps when processing
-A.
(sparc_ip): Use the current opcode arch hwcaps to update
hwcap_allowed, as well of the hwcaps of the instruction triggering
the bump.
* testsuite/gas/sparc/hwcaps-bump.s: New file.
* testsuite/gas/sparc/hwcaps-bump.l: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
hwcaps-bump.
include/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
hwcaps2.
opcodes/ChangeLog:
2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (HWS_V8): Definition moved from
gas/config/tc-sparc.c.
(HWS_V9): Likewise.
(HWS_VA): Likewise.
(HWS_VB): Likewise.
(HWS_VC): Likewise.
(HWS_VD): Likewise.
(HWS_VE): Likewise.
(HWS_VV): Likewise.
(HWS_VM): Likewise.
(HWS2_VM): Likewise.
(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
existing entries.
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gas/
2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/b.d: Update test result.
opcode/
2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
* arc-tbl.h: Reorder conditional flags with delay flags for 'b'
instructions.
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VLE 16A and 16D relocs were functionally swapped.
PR 20744
include/
* opcode/ppc.h: Define VLE insns using 16A and 16D relocs.
bfd/
* elf32-ppc.h (struct ppc_elf_params): Add vle_reloc_fixup field.
* elf32-ppc.c: Include opcode/ppc.h.
(ppc_elf_howto_raw): Correct dst_mask for R_PPC_VLE_LO16A,
R_PPC_VLE_LO16D, R_PPC_VLE_HI16A, R_PPC_VLE_HI16D, R_PPC_VLE_HA16A,
R_PPC_VLE_HA16D, R_PPC_VLE_SDAREL_LO16A, R_PPC_VLE_SDAREL_LO16D,
R_PPC_VLE_SDAREL_HI16A, R_PPC_VLE_SDAREL_HI16D,
R_PPC_VLE_SDAREL_HA16A, and R_PPC_VLE_SDAREL_HA16D relocs.
(ppc_elf_link_hash_table_create): Update default_params init.
(ppc_elf_vle_split16): Correct shift and mask. Add params.
Report or fix insn/reloc mismatches.
(ppc_elf_relocate_section): Pass input_section, offset and fixup
to ppc_elf_vle_split16.
binutils/
* NEWS: Mention PowerPC VLE relocation error.
gas/
* config/tc-ppc.c: Delete VLE insn defines.
(md_assemble): Swap use_a_reloc and use_d_reloc.
* testsuite/gas/ppc/vle-reloc.d: Update.
ld/
* emultempl/ppc32elf.em (params): Update initializer. Handle
--vle-reloc-fixup command line arg.
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|
syntax).
gas/
2016-11-21 Renlin Li <renlin.li@arm.com>
PR gas/20827
* config/tc-arm.c (encode_arm_shift): Don't assert for operands not
presented.
* testsuite/gas/arm/add-shift-two.d: New.
* testsuite/gas/arm/add-shift-two.s: New.
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|
* configure.ac: Invoke ACX_PROG_CMP_IGNORE_INITIAL.
* Makefile.am (comparison): Rewrite using do_compare.
* configure: Regenerate.
* Makefile.in: Regenerate.
* doc/Makefile.in: Regenerate.
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|
gas/
2016-11-18 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/cl-warn.s: New file.
* testsuite/gas/arc/cpu-pseudop-1.d: Likewise.
* testsuite/gas/arc/cpu-pseudop-1.s: Likewise.
* testsuite/gas/arc/cpu-pseudop-2.d: Likewise.
* testsuite/gas/arc/cpu-pseudop-2.s: Likewise.
* testsuite/gas/arc/cpu-warn2.s: Likewise.
* config/tc-arc.c (selected_cpu): Initialize.
(feature_type): New struct.
(feature_list): New variable.
(arc_check_feature): New function.
(arc_select_cpu): Check for .cpu duplicates. Don't overwrite the
current cpu features. Check if a feature is available for a given
cpu.
(md_parse_option): Test if features are available for a given cpu.
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|
Add support for FCMLA and FCADD complex arithmetic SIMD instructions.
FCMLA has an indexed element variant where the index range has to be
treated specially because a complex number takes two elements and the
indexed vector size depends on the other operands.
These complex number SIMD instructions are part of ARMv8.3
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
include/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
(enum aarch64_op): Add OP_FCMLA_ELEM.
opcodes/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
(aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
(aarch64_opcode_table): Add fcmla and fcadd.
(AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
* aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
* aarch64-asm.c (aarch64_ins_imm_rotate): Define.
* aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
* aarch64-dis.c (aarch64_ext_imm_rotate): Define.
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
* aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
(operand_general_constraint_met_p): Rotate and index range check.
(aarch64_print_operand): Handle rotate operand.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
gas/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*.
* testsuite/gas/aarch64/advsimd-armv8_3.d: New.
* testsuite/gas/aarch64/advsimd-armv8_3.s: New.
* testsuite/gas/aarch64/illegal-fcmla.s: New.
* testsuite/gas/aarch64/illegal-fcmla.l: New.
* testsuite/gas/aarch64/illegal-fcmla.d: New.
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|
Add support for ARMv8.3 LDAPRB, LDAPRH and LDAPR weak release
consistency load instructions. (They are equivalent to LDARB,
LDARH and LDAR instructions other than the weaker memory ordering
requirement.)
For more details about weak release consistency see
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
opcodes/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Add ldaprb, ldaprh, ldapr tests.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Likewise.
* testsuite/gas/aarch64/illegal-ldapr.s: Likewise.
* testsuite/gas/aarch64/illegal-ldapr.d: Likewise.
* testsuite/gas/aarch64/illegal-ldapr.l: Likewise.
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|
Add support for ARMv8.3 FJCVTZS floating-point conversion
instruction.
For details about javascript floating-point conversion see
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
opcodes/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
(QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* testsuite/gas/aarch64/fp-armv8_3.s: Add fjcvtzs test.
* testsuite/gas/aarch64/fp-armv8_3.d: Likewise.
* testsuite/gas/aarch64/illegal-fjcvtzs.s: Likewise.
* testsuite/gas/aarch64/illegal-fjcvtzs.d: Likewise.
* testsuite/gas/aarch64/illegal-fjcvtzs.l: Likewise.
* testsuite/gas/aarch64/illegal-nofp-armv8_3.s: Likewise.
* testsuite/gas/aarch64/illegal-nofp-armv8_3.d: Likewise.
* testsuite/gas/aarch64/illegal-nofp-armv8_3.l: Likewise.
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|
Add support for ARMv8.3 LDRAA and LDRAB combined pointer authentication and
load instructions.
These instructions authenticate the base register and load 8 byte from it plus
a scaled 10-bit offset with optional writeback to update the base register.
A new instruction class (ldst_imm10) and operand type (AARCH64_OPND_ADDR_SIMM10)
were introduced to handle the special addressing form.
include/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
(enum aarch64_insn_class): Add ldst_imm10.
opcodes/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (QL_X1NIL): New.
(arch64_opcode_table): Add ldraa, ldrab.
(AARCH64_OPERANDS): Add "ADDR_SIMM10".
* aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
* aarch64-asm.c (aarch64_ins_addr_simm10): Define.
* aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
* aarch64-dis.c (aarch64_ext_addr_simm10): Define.
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
* aarch64-opc.c (fields): Add data for FLD_S_simm10.
(operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
(aarch64_print_operand): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas/
2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_ADDR_SIMM10.
(fix_insn): Likewise.
(warn_unpredictable_ldst): Handle ldst_imm10.
* testsuite/gas/aarch64/pac.s: Add ldraa and ldrab tests.
* testsuite/gas/aarch64/pac.d: Likewise.
* testsuite/gas/aarch64/illegal-ldraa.s: New.
* testsuite/gas/aarch64/illegal-ldraa.l: New.
* testsuite/gas/aarch64/illegal-ldraa.d: New.
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PR gas/20803
* config/tc-sparc.c (cons_fix_new_sparc): Use unaligned relocs in
the .eh_frame section.
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