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2016-05-10Enable Intel RDPID instruction.Alexander Fomin12-3/+96
This patch enables Intel RDPID instruction described in Intel64 and IA-32 Architectures Software Developer's Manual, April 2016. gas/ * config/tc-i386.c (cpu_arch): Add RDPID. * doc/c-i386.texi: Document RDPID. gas/testsuite/ * gas/i386/i386.exp: Run RDPID tests. * gas/i386/prefix.d: Adjust. * gas/i386/rdpid.s: New test. * gas/i386/rdpid.d: Ditto. * gas/i386/rdpid-intel.d: Ditto. * gas/i386/x86-64-rdpid.s: Ditto. * gas/i386/x86-64-rdpid.d: Ditto. * gas/i386/x86-64-rdpid-intel.d: Ditto. opcodes/ * i386-dis.c (prefix_table): Add RDPID instruction. * i386-gen.c (cpu_flag_init): Add RDPID flag. (cpu_flags): Add RDPID bitfield. * i386-opc.h (enum): Add RDPID element. (i386_cpu_flags): Add RDPID field. * i386-opc.tbl: Add RDPID instruction. * i386-init.h: Regenerate. * i386-tbl.h: Regenerate.
2016-05-10Use getters/setters to access ARM branch typeThomas Preud'homme2-2/+7
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ * elf32-arm.c (elf32_arm_size_stubs): Use new macros ARM_GET_SYM_BRANCH_TYPE and ARM_SET_SYM_BRANCH_TYPE to respectively get and set branch type of a symbol. (bfd_elf32_arm_process_before_allocation): Likewise. (elf32_arm_relocate_section): Likewise and fix identation along the way. (allocate_dynrelocs_for_symbol): Likewise. (elf32_arm_finish_dynamic_symbol): Likewise. (elf32_arm_swap_symbol_in): Likewise. (elf32_arm_swap_symbol_out): Likewise. gas/ * config/tc-arm.c (arm_adjust_symtab): Use ARM_SET_SYM_BRANCH_TYPE to set branch type of a symbol. gdb/ * arm-tdep.c (arm_elf_make_msymbol_special): Use ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol. include/ * arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE enumerator. (NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro. (ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise. (ARM_SYM_BRANCH_TYPE): Replace by ... (ARM_GET_SYM_BRANCH_TYPE): This and ... (ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether BFD_ASSERT is defined or not. ld/ * emultempl/armelf.em (gld${EMULATION_NAME}_finish): Use ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol. opcodes/ * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol. (print_insn): Likewise.
2016-05-10Add support for ARMv8-M Mainline with DSP extensionThomas Preud'homme12-3/+325
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ (elf32_arm_merge_eabi_attributes): Add merging logic for Tag_DSP_extension. binutils/ * readelf.c (display_arm_attribute): Add output for Tag_DSP_extension. (arm_attr_public_tags): Define DSP_extension attribute. gas/ * NEWS: Document ARMv8-M and ARMv8-M Security and DSP Extensions. * config/tc-arm.c (arm_ext_dsp): New feature for Thumb DSP instructions. (arm_extensions): Add dsp extension for ARMv8-M Mainline. (aeabi_set_public_attributes): Memorize the feature bits of the architecture selected for Tag_CPU_arch. Use it to set Tag_DSP_extension to 1 for ARMv8-M Mainline with DSP extension. (arm_convert_symbolic_attribute): Define Tag_DSP_extension. * testsuite/gas/arm/arch7em-bad.d: Rename to ... * testsuite/gas/arm/arch7em-bad-1.d: This. * testsuite/gas/arm/arch7em-bad-2.d: New file. * testsuite/gas/arm/arch7em-bad-3.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-5.d: Likewise. * testsuite/gas/arm/attr-march-armv8m.main.dsp.d: Likewise. include/ * elf/arm.h (Tag_DSP_extension): Define. ld/ * testsuite/ld-arm/arm-elf.exp (EABI attribute merging 10 (DSP)): New test. * testsuite/ld-arm/attr-merge-10b-dsp.s: New file. * testsuite/ld-arm/attr-merge-10-dsp.attr: Likewise.
2016-05-10Allow extension availability to depend on several architecture bitsThomas Preud'homme2-15/+58
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (struct arm_option_extension_value_table): Make allowed_archs an array with 2 entries. (ARM_EXT_OPT): Adapt to only fill the first entry of allowed_archs. (ARM_EXT_OPT2): New macro filling the two entries of allowed_archs. (arm_extensions): Use separate entries in allowed_archs when several archs are allowed to use an extension and change ARCH_ANY in ARM_ARCH_NONE in allowed_archs. (arm_parse_extension): Check that, for each allowed_archs entry, all bits are set in the current architecture, ignoring ARM_ANY entries. (s_arm_arch_extension): Likewise. include/ * arm.h (ARM_FSET_CPU_SUBSET): Define macro.
2016-05-10Add support for ARMv8-M security extensions instructionsThomas Preud'homme12-8/+230
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_ext_m): Add feature bit ARM_EXT2_V8M_MAIN. (arm_ext_v8m_main): New feature set for bit ARM_EXT2_V8M_MAIN. (arm_ext_v8m_m_only): New feature set for instructions in ARMv8-M not shared with a non M profile architecture. (do_rn): New function. (known_t32_only_insn): Check opcode against arm_ext_v8m_m_only rather than arm_ext_v8m. (v7m_psrs): Add ARMv8-M security extensions new special registers. (insns): Add ARMv8-M Security Extensions instructions. (aeabi_set_public_attributes): Use arm_ext_v8m_m_only instead of arm_ext_v8m_m to decide the profile and the Thumb ISA. * testsuite/gas/arm/archv8m-cmse.s: New file. * testsuite/gas/arm/archv8m-cmse-main.s: Likewise.. * testsuite/gas/arm/archv8m-cmse-msr.s: Likewise. * testsuite/gas/arm/any-cmse.d: Likewise. * testsuite/gas/arm/any-cmse-main.d: Likewise. * testsuite/gas/arm/archv8m-cmse-base.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise. * testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise. * testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise. include/ * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit. (ARM_AEXT2_V8M_MAIN): New architecture extension feature set. (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M for the high core bits. opcodes/ * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M Mainline Security Extensions instructions. (thumb_opcodes): Add entries for narrow ARMv8-M Security Extensions instructions. (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions instructions. (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions special registers.
2016-05-09opcodes,gas: sparc: fix mnemonic of faligndataiJose E. Marchesi3-2/+7
opcodes/ChangeLog: 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai. gas/ChangeLog: 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/sparc/sparc5vis4.s: Fix mnemonic of faligndatai. * testsuite/gas/sparc/sparc5vis4.d: Likewise.
2016-05-09Regenerate configureAlan Modra1-7/+10
2016-05-06[ARM][gas] Fix warnings about uninitialised uses and unused const variablesKyrylo Tkachov2-4/+16
* config/tc-arm.c (fpu_arch_vfp_v1): Mark with ATTRIBUTE_UNUSED. (fpu_arch_vfp_v3): Likewise. (fpu_arch_neon_v1): Likewise. (arm_arch_full): Likewise. (parse_neon_el_struct_list): Initialize fields of firsttype.
2016-05-04[ARC] Add SYNTAX_NOP and SYNTAX_1OP for extension instructionsClaudiu Zissulescu5-2/+49
gas/ 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (syntaxclass): Add SYNTAX_NOP and SYNTAX_1OP. (arc_extinsn): Handle new introduced syntax. * testsuite/gas/arc/textinsn1op.d: New file. * testsuite/gas/arc/textinsn1op.s: Likewise. * doc/c-arc.texi: Document SYNTAX_NOP and SYNTAX_1OP. opcodes/ 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com> * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP. (arcExtMap_genOpcode): Likewise. * arc-opc.c (arg_32bit_rc): Define new variable. (arg_32bit_u6): Likewise. (arg_32bit_limm): Likewise. include/ 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (ARC_SYNTAX_1OP): Declare (ARC_SYNTAX_NOP): Likewsie. (ARC_OP1_MUST_BE_IMM): Update defined value. (ARC_OP1_IMM_IMPLIED): Likewise. (arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
2016-05-03Assume that the GAS testsuite for the AVR is being run without -mlink-relax ↵Pitchumani Sivanupandi2-0/+6
specified. * testsuite/gas/lns/lns.exp: Add avr to list of targets using DW_LNS_fixed_advance_pc.
2016-04-27Provide xmemdup0Alan Modra2-15/+13
and some tidies in as.h * as.h (inline, __PTR_TO_INT, __INT_TO_PTR): Don't define. (xmemdup0): New inline function.
2016-04-22MIPS/GAS: Fix an ISA override not lifting ABI restrictionsMaciej W. Rozycki46-8/+775
Correct a regression introduced with commit 919731affbef ("Add MIPS .module directive") causing code like: .set mips3 dli $2, 0x9000000080000000 to fail assembly with the following error message produced: Error: number (0x9000000080000000) larger than 32 bits if built with `mips3' selected as the global ISA (e.g. `-march=mips3'). This is because a `.set' directive doing an ISA override does not lift the ABI restriction on register sizes if the ISA remains unchanged. Previously the directive always set register sizes from the ISA chosen, which is what some code expects. Restore the old semantics then. gas/ * config/tc-mips.c (code_option_type): New enum. (parse_code_option): Return status indicating option type. (s_mipsset): Update `parse_code_option' call site accordingly. Always set register sizes from the ISA with ISA overrides. (s_module): Update `parse_code_option' call site. * testsuite/gas/mips/isa-override-1.d: New test. * testsuite/gas/mips/micromips@isa-override-1.d: New test. * testsuite/gas/mips/mips1@isa-override-1.d: New test. * testsuite/gas/mips/mips2@isa-override-1.d: New test. * testsuite/gas/mips/mips32@isa-override-1.d: New test. * testsuite/gas/mips/mips32r2@isa-override-1.d: New test. * testsuite/gas/mips/mips32r3@isa-override-1.d: New test. * testsuite/gas/mips/mips32r5@isa-override-1.d: New test. * testsuite/gas/mips/mips32r6@isa-override-1.d: New test. * testsuite/gas/mips/mips64r2@isa-override-1.d: New test. * testsuite/gas/mips/mips64r3@isa-override-1.d: New test. * testsuite/gas/mips/mips64r5@isa-override-1.d: New test. * testsuite/gas/mips/mips64r6@isa-override-1.d: New test. * testsuite/gas/mips/r3000@isa-override-1.d: New test. * testsuite/gas/mips/r3900@isa-override-1.d: New test. * testsuite/gas/mips/r5900@isa-override-1.d: New test. * testsuite/gas/mips/octeon@isa-override-1.d: New test. * testsuite/gas/mips/octeon3@isa-override-1.d: New test. * testsuite/gas/mips/isa-override-2.l: New list test. * testsuite/gas/mips/mips1@isa-override-2.l: New list test. * testsuite/gas/mips/mips2@isa-override-2.l: New list test. * testsuite/gas/mips/mips32@isa-override-2.l: New list test. * testsuite/gas/mips/mips32r2@isa-override-2.l: New list test. * testsuite/gas/mips/mips32r3@isa-override-2.l: New list test. * testsuite/gas/mips/mips32r5@isa-override-2.l: New list test. * testsuite/gas/mips/mips32r6@isa-override-2.l: New list test. * testsuite/gas/mips/r3000@isa-override-2.l: New list test. * testsuite/gas/mips/r3900@isa-override-2.l: New list test. * testsuite/gas/mips/octeon3@isa-override-2.l: New list test. * testsuite/gas/mips/octeon3@isa-override-1.l: New stderr output. * testsuite/gas/mips/isa-override-1.s: New test source. * testsuite/gas/mips/r5900@isa-override-1.s: New test source. * testsuite/gas/mips/isa-override-2.s: New test source. * testsuite/gas/mips/mips1@isa-override-2.s: New test source. * testsuite/gas/mips/mips2@isa-override-2.s: New test source. * testsuite/gas/mips/mips32@isa-override-2.s: New test source. * testsuite/gas/mips/mips32r2@isa-override-2.s: New test source. * testsuite/gas/mips/mips32r3@isa-override-2.s: New test source. * testsuite/gas/mips/mips32r5@isa-override-2.s: New test source. * testsuite/gas/mips/mips32r6@isa-override-2.s: New test source. * testsuite/gas/mips/r3000@isa-override-2.s: New test source. * testsuite/gas/mips/r3900@isa-override-2.s: New test source. * testsuite/gas/mips/octeon3@isa-override-2.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-20update many old style function definitionsTrevor Saunders8-12/+20
This includes regenerating a bunch of files in opcodes/ with trunk cgen. gprof/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * basic_blocks.c: Update old style function definitions. * cg_arcs.c: Likewise. * cg_print.c: Likewise. * gen-c-prog.awk: Likewise. * gmon_io.c: Likewise. * hertz.c: Likewise. * hist.c: Likewise. * sym_ids.c: Likewise. bfd/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * cache.c: Update old style function definitions. * elf32-m68k.c: Likewise. * elf64-mmix.c: Likewise. * stab-syms.c: Likewise. opcodes/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * alpha-dis.c: Regenerate. * crx-dis.c: Likewise. * disassemble.c: Likewise. * epiphany-opc.c: Likewise. * fr30-opc.c: Likewise. * frv-opc.c: Likewise. * ip2k-opc.c: Likewise. * iq2000-opc.c: Likewise. * lm32-opc.c: Likewise. * lm32-opinst.c: Likewise. * m32c-opc.c: Likewise. * m32r-opc.c: Likewise. * m32r-opinst.c: Likewise. * mep-opc.c: Likewise. * mt-opc.c: Likewise. * or1k-opc.c: Likewise. * or1k-opinst.c: Likewise. * tic80-opc.c: Likewise. * xc16x-opc.c: Likewise. * xstormy16-opc.c: Likewise. ld/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * emultempl/scoreelf.em: Likewise. binutils/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * resres.c: Likewise. gas/ChangeLog: 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * cgen.c: Likewise. * config/tc-bfin.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-metag.c: Likewise. * config/tc-nios2.c: Likewise. * config/tc-rl78.c: Likewise.
2016-04-20gas/doc/arc: Add nps400 references into the documentationAndrew Burgess2-2/+14
Add nps400 to the list of acceptable values for the -mcpu command line switch, and to the .cpu directive. I've added an extra cross reference from -mcpu to .cpu to improve navigation of the documentation. gas/ChangeLog: * doc/c-arc.texi (ARC Options): Add nps400 to list of valus for -mcpu. Add cross reference to .cpu directive from -mcpu option. (ARC Directives): Add NPS400 to .cpu directive list.
2016-04-20[AArch64] Support RAS extension for ARMv8 onwards.Matthew Wahab8-0/+249
The RAS extension was introduced as part of the ARMv8.2 architecture where it is a required feature. It is also available as an optional feature for ARMv8 and ARMv8.1. In binutils, the RAS extension is currently enabled by default for -march=armv8.2-a but is not available for -march=armv8 or -march=armv8.1-a. This patch adds the feature extension '+ras' to enable the RAS extension for ARMv8 and ARMv8.1, it is disabled by default. gas/ 2016-04-20 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_features): Add "ras". * doc/c-aarch64.texi (AArch64 Extensions): Add "ras". * testsuite/gas/aarch64/armv8-ras-1.d: New. * testsuite/gas/aarch64/armv8-ras-1.s: New. * testsuite/gas/aarch64/illegal-ras-1.d: New. * testsuite/gas/aarch64/illegal-ras-1.s: New. Change-Id: I824fb9bc8cf846bcc03aa17a726efb1350d78b9d
2016-04-19opcodes/arc: Add yet more nps instructionsAndrew Burgess3-0/+142
Add some more arc/nps400 instructions and the associated operands. There's also a test added into the assembler. gas/ChangeLog: * testsuite/gas/arc/nps400-6.d: New file. * testsuite/gas/arc/nps400-6.s: New file. include/ChangeLog: * opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8. opcodes/ChangeLog: * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb, fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, and qcmp instructions. * arc-opc.c (insert_nps_bitop_size): Delete. (extract_nps_bitop_size): Delete. (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use. (extract_nps_qcmp_m3): Define. (extract_nps_qcmp_m2): Define. (extract_nps_qcmp_m1): Define. (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL. (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE, NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST, NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and NPS_QCMP_M3.
2016-04-19opcodes/arc: Add more nps instructionsAndrew Burgess5-0/+45
Add dctcp, dcip, dcet, and dcacl instructions. gas/ChangeLog: * testsuite/gas/arc/nps400-4.d: New file. * testsuite/gas/arc/nps400-4.s: New file. * testsuite/gas/arc/nps400-5.d: New file. * testsuite/gas/arc/nps400-5.s: New file. include/ChangeLog: * opcode/arc.h (insn_class_t): Add NET and ACL class. opcodes/ChangeLog: * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
2016-04-19.cfi_remember_state/.cfi_restore_state documentationMartin Galvan2-5/+53
* doc/as.texinfo (.cfi_remember_state, .cfi_restore_state): Improve documentation.
2016-04-17Revert "gas/arc: Make .cpu directive case-insensitive"Andrew Burgess2-8/+14
This reverts commit 9a452709fe126ea6da23a53426362e4435d2dc06. This change was committed as obvious, but it has been rightly been pointed out to me that this change is not obvious, and as such I am reverting it. gas/ChangeLog: Revert prevous change. * config/tc-arc.c (arc_option): Make .cpu directive case-sensitive again.
2016-04-16gas/arc: Make .cpu directive case-insensitiveAndrew Burgess2-8/+13
gas/ChangeLog: * config/tc-arc.c (arc_option): Make .cpu directive case-insensitive.
2016-04-16gas/arc: Support NPS400 in .cpu directiveAndrew Burgess2-0/+8
gas/ChangeLog: * config/tc-arc.c (arc_option): Allow NPS400 in .cpu directive.
2016-04-15remove pointless assignmentTrevor Saunders2-5/+8
Presumably this was supposed to be regname[sizeof (regname) - 1] but was typoed to regname[sizeof (rename) - 1]. However that should be unnecessary because sprintf should null terminate. As is this assignment is invalid ISO C because rename refers to the function rename (), and sizeof on functions is undefined. In GNU C C the size of functions is 1 so the expression is the same as regname[0]. The following call to sprintf () clearly will over right that, so the statement either has no effect or is invalid. Given that it seems safe to just remove it. While we are there correct the size of regname, and switch from snprintf to sprintf since we know the exact length of the result. gas/ChangeLog: 2016-04-15 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-mips.c (md_begin): Remove useless assignment.
2016-04-15Regenerate Makefile.in/aclocal.m4 automake 1.11.6H.J. Lu4-79/+190
bfd/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. * doc/Makefile.in: Likewise. binutils/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. * doc/Makefile.in: Likewise. gas/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. * doc/Makefile.in: Likewise. gold/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. * testsuite/Makefile.in: Likewise. gprof/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. ld/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise. opcodes/ * Makefile.in: Regenerated with automake 1.11.6. * aclocal.m4: Likewise.
2016-04-15Fix non-ELF powerpc build breakageAlan Modra2-0/+6
* config/tc-ppc.c (toc_reloc_types): Wrap in #ifdef OBJ_ELF
2016-04-15Add missing ChangeLog entry for PR gas/19909 fixH.J. Lu1-0/+10
2016-04-14make a few variables staticTrevor Saunders4-3/+9
They are only used in one file, so we might as well restrict there scope to that file, and theoretically this might slightly improve compilers ability to optimize usage of these variables. gas/ChangeLog: 2016-04-14 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-nios2.c (nios2_as_options): Make file static. * config/tc-ppc.c (toc_reloc_ypes): Likewise. * config/tc-sparc.c (native_op_table): Likewise.
2016-04-14remove some unused globalsTrevor Saunders3-2/+7
gas/ChangeLog: 2016-04-14 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-m32c.c (M32C_Macros): Remove. * config/tc-msp430.c (option_numbers): Likewise.
2016-04-14arc/nps400 : New cmem instructions and associated relocationAndrew Burgess3-0/+84
Add support for arc/nps400 cmem instructions, these load and store instructions are hard-wired to access "0x57f00000 + 16-bit-offset". Supporting this relocation required some additions to the arc relocation handling in the bfd library, as well as the standard changes required to add a new relocation type. There's a test of the new instructions in the assembler, and a test of the relocation in the linker. bfd/ChangeLog: * reloc.c: Add BFD_RELOC_ARC_NPS_CMEM16 entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf32-arc.c: Add 'opcode/arc.h' include. (struct arc_relocation_data): Add symbol_name. (arc_special_overflow_checks): New function. (arc_do_relocation): Use arc_special_overflow_checks, reindent as required, add an extra comment. (elf_arc_relocate_section): Setup symbol_name in reloc_data. gas/ChangeLog: * testsuite/gas/arc/nps400-3.d: New file. * testsuite/gas/arc/nps400-3.s: New file. include/ChangeLog: * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc. * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define. ld/ChangeLog: * testsuite/ld-arc/arc.exp: New file. * testsuite/ld-arc/nps-1.s: New file. * testsuite/ld-arc/nps-1a.d: New file. * testsuite/ld-arc/nps-1b.d: New file. * testsuite/ld-arc/nps-1b.err: New file. opcodes/ChangeLog: * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst instructions. * arc-opc.c (insert_nps_cmem_uimm16): New function. (extract_nps_cmem_uimm16): New function. (arc_operands): Add NPS_XLDST_UIMM16 operand.
2016-04-14gas/arc: Unify tests run on big/little endian arc assemblerAndrew Burgess4-3/+8
We were running a slightly different set of assembler tests on big and little endian arc targets. This commit unifies the set of tests run. gas/ChangeLog: * testsuite/gas/arc/add_s-err.s: Update target pattern. * testsuite/gas/arc/warn.s: Likewise. * testsuite/gas/elf/elf.exp: Run test for arc.
2016-04-14Fix copying Solaris binaries with objcopy.Nick Clifton3-4/+11
PR target/19938 bfd * elf-bbfd.h (struct elf_backend_data): New field: elf_strtab_flags. New field: elf_backend_set_special_section_info_and_link * elfxx-target.h (elf_backend_strtab_flags): Define if not already defined. (elf_backend_set_special_section_info_and_link): Define if not already defined. (elfNN_bed): Use elf_backend_set_special_section_info_and_link and elf_backend_strtab_flags macros to initialise fields in structure. * elf.c (_bfd_elf_make_section_from_shdr): Check for SHF_STRINGS being set even if SHF_MERGE is not set. (elf_fake_sections): Likewise. (section_match): New function. Matches two ELF sections based upon fixed characteristics. (find_link): New function. Locates a section in a BFD that matches a section in a different BFD. (_bfd_elf_copy_private_bfd_data): Copy the sh_info and sh_link fields of reserved sections. (bfd_elf_compute_section_file_positions): Set the flags for the .shstrtab section based upon the elf_strtab_flags field in the elf_backend_data structure. (swap_out_syms): Likewise for the .strtab section. * elflink.c (bfd_elf_final_link): Set the flags for the .strtab section based upon the elf_strtab_flags field in the elf_backend_data structure. * elf32-i386.c (elf32_i386_set_special_info_link): New function. (elf_backend_strtab_flags): Set to SHF_STRINGS for Solaris targets. (elf_backend_set_special_section_info_and_link): Define for Solaris targets. * elf32-sparc.c: Likewise. * elf64-x86-64.c: Likewise. binutils* testsuite/binutils-all/i386/compressed-1b.d: Allow for the string sections possibly having the SHF_STRINGS flag bit set. * testsuite/binutils-all/i386/compressed-1c.d: Likewise. * testsuite/binutils-all/readelf.s: Likewise. * testsuite/binutils-all/readelf.s-64: Likewise. * testsuite/binutils-all/x86-64/compressed-1b.d: Likewise. * testsuite/binutils-all/x86-64/compressed-1c.d: Likewise. gas * testsuite/gas/i386/ilp32/x86-64-unwind.d: Allow for the string sections possibly having the SHF_STRINGS flag bit set. * testsuite/gas/i386/x86-64-unwind.d: Likewise.
2016-04-13[ARC] Fix setting private elf flags when parsing .cpu.Claudiu Zissulescu2-3/+13
gas/ 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (mach_type_specified_p): Change type to bfd_boolean. (arc_option): Set private flags when parsing cpu pseudo-op. (md_parse_option): Set mach_type_specified_p to TRUE.
2016-04-13oops - omitted from previous delta.Nick Clifton1-0/+7
2016-04-13Fix disassembly of the V850's LD.BU instruction.Nick Clifton3-0/+33
PR target/19937 opcode * v850-opc.c (v850_opcodes): Correct masks for long versions of the LD.B and LD.BU instructions. gas * testsuite/gas/v850/pr19937.s: New test. * testsuite/gas/v850/pr19937.d: New test control file. * testsuite/gas/v850/basic.exp: Run the new test.
2016-04-13MIPS/GAS: Correct branch relaxation for weak symbolsMaciej W. Rozycki10-0/+122
Weak symbols can be preempted at link time so always choose the longer sequence in branch relaxation, according to the relaxation level chosen, so that any symbol finally used as the branch target is reachable. 2016-04-13 Maciej W. Rozycki <macro@imgtec.com> Andrew Bennett <andrew.bennett@imgtec.com> gas/ * config/tc-mips.c (relaxed_branch_length): Use the long sequence where the target is a weak symbol. (relaxed_micromips_32bit_branch_length): Likewise. (relaxed_micromips_16bit_branch_length): Likewise. * testsuite/gas/mips/branch-weak-1.d: New test. * testsuite/gas/mips/branch-weak-2.d: New test. * testsuite/gas/mips/branch-weak-3.d: New test. * testsuite/gas/mips/branch-weak-4.d: New test. * testsuite/gas/mips/branch-weak-5.d: New test. * testsuite/gas/mips/branch-weak.l: New stderr output. * testsuite/gas/mips/branch-weak.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-13MIPS/GAS: Relax branches to symbols resolved at link timeMaciej W. Rozycki15-10/+193
Where branch relaxation is enabled emit the long sequence for branches whose distance cannot be determined, i.e. to symbols that are undefined or in a different segment. These symbols are only resolved at link time and therefore the longer sequence ensures the branch target is in range, which cannot be guaranteed with a direct branch. This is the opposite to the current implementation, originally proposed here: <https://sourceware.org/ml/binutils/2002-09/msg00218.html>. The proposal was then extensively discussed before the final version was posted here: <https://sourceware.org/ml/binutils/2002-10/msg00191.html> and eventually committed: commit 4a6a3df43dbb37853a7b88b10ae97d9ec5daf987 Author: Alexandre Oliva <aoliva@redhat.com> Date: Sat Oct 12 05:23:33 2002 +0000 The case considered here was not commented in the review however and the original version remains. With branch relaxation enabled it makes more sense to do it consistently, so that all code impure with respect to branch distances can be linked. Direct branches are still produced for the cases concerned where branch relaxation is disabled, which is the default. gas/ * config/tc-mips.c (relaxed_branch_length): Use the long sequence where the distance cannot be determined. (relaxed_micromips_32bit_branch_length): Likewise. * testsuite/gas/mips/branch-extern-1.d: New test. * testsuite/gas/mips/branch-extern-2.d: New test. * testsuite/gas/mips/branch-extern-3.d: New test. * testsuite/gas/mips/branch-extern-4.d: New test. * testsuite/gas/mips/branch-extern.l: New stderr output. * testsuite/gas/mips/branch-extern.s: New test source. * testsuite/gas/mips/branch-section-1.d: New test. * testsuite/gas/mips/branch-section-2.d: New test. * testsuite/gas/mips/branch-section-3.d: New test. * testsuite/gas/mips/branch-section-4.d: New test. * testsuite/gas/mips/branch-section.l: New stderr output. * testsuite/gas/mips/branch-section.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-12Add support for .extCondCode, .extCoreRegister and .extAuxRegister.Claudiu Zissulescu16-37/+540
gas/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/textauxregister.d: New file. * testsuite/gas/arc/textauxregister.s: Likewise. * testsuite/gas/arc/textcondcode.d: Likewise. * testsuite/gas/arc/textcondcode.s: Likewise. * testsuite/gas/arc/textcoreregister.d: Likewise. * testsuite/gas/arc/textcoreregister.s: Likewise. * testsuite/gas/arc/textpseudoop.d: Likewise. * testsuite/gas/arc/textpseudoop.s: Likewise. * testsuite/gas/arc/ld2.d: Update test. * testsuite/gas/arc/st.d: Likewise. * testsuite/gas/arc/taux.d: Likewise. * doc/c-arc.texi (ARC Directives): Add .extCondCode, .extCoreRegister and .extAuxRegister documentation. * config/tc-arc.c (arc_extcorereg): New function. (md_pseudo_table): Add .extCondCode, .extCoreRegister and .extAuxRegister pseudo-ops. (extRegister_t): New type. (ext_condcode, arc_aux_hash): New global variable. (find_opcode_match): Check for extensions. (preprocess_operands): Likewise. (md_begin): Add aux registers in a hash. (assemble_insn): Update use arc_flags member. (tokenize_extregister): New function. (create_extcore_section): Likewise. * config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Increase to 10. (arc_flags): Delete code, add flgp. include/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (flag_class_t): Update. (ARC_OPCODE_NONE): Define. (ARC_OPCODE_ARCALL): Likewise. (ARC_OPCODE_ARCFPX): Likewise. (ARC_REGISTER_READONLY): Likewise. (ARC_REGISTER_WRITEONLY): Likewise. (ARC_REGISTER_NOSHORT_CUT): Likewise. (arc_aux_reg): Add cpu. opcodes/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (find_format): Check for extension flags. (print_flags): New function. (print_insn_arc): Update for .extCondCode, .extCoreRegister and .extAuxRegister. * arc-ext.c (arcExtMap_coreRegName): Use LAST_EXTENSION_CORE_REGISTER. (arcExtMap_coreReadWrite): Likewise. (dump_ARC_extmap): Update printing. * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag. (arc_aux_regs): Add cpu field. * arc-regs.h: Add cpu field, lower case name aux registers. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-12Update ARC instruction data-base.Claudiu Zissulescu5-0/+70
gas/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/noargs_a7.d: New file. * testsuite/gas/arc/noargs_a7.s: Likewise. * testsuite/gas/arc/noargs_hs.d: Likewise. * testsuite/gas/arc/noargs_hs.s: Likewise. opcode/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * arc-tbl.h: Add rtsc, sleep with no arguments. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-12Add support for .extInstruction pseudo-op.Claudiu Zissulescu12-36/+699
gas/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/textinsn-errors.d: New File. * testsuite/gas/arc/textinsn-errors.err: Likewise. * testsuite/gas/arc/textinsn-errors.s: Likewise. * testsuite/gas/arc/textinsn2op.d: Likewise. * testsuite/gas/arc/textinsn2op.s: Likewise. * testsuite/gas/arc/textinsn2op01.d: Likewise. * testsuite/gas/arc/textinsn2op01.s: Likewise. * testsuite/gas/arc/textinsn3op.d: Likewise. * testsuite/gas/arc/textinsn3op.s: Likewise. * doc/c-arc.texi (ARC Directives): Add .extInstruction documentation. * config/tc-arc.c (arcext_section): New variable. (arc_extinsn): New function. (md_pseudo_table): Add .extInstruction pseudo op. (attributes_t): New type. (suffixclass, syntaxclass, syntaxclassmod): New constant structures. (find_opcode_match): Remove arc_num_opcodes. (md_begin): Likewise. (tokenize_extinsn): New function. (arc_set_ext_seg): Likewise. (create_extinst_section): Likewise. include/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (arc_num_opcodes): Remove. (ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM) (ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND) (ARC_SUFFIX_FLAG): Define. (flags_none, flags_f, flags_cc, flags_ccf): Declare. (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. opcodes/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf): Initialize. (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. (arc_opcode arc_opcodes): Null terminate the array. (arc_num_opcodes): Remove. * arc-ext.h (INSERT_XOP): Define. (extInstruction_t): Likewise. (arcExtMap_instName): Delete. (arcExtMap_insn): New function. (arcExtMap_genOpcode): Likewise. * arc-ext.c (ExtInstruction): Remove. (create_map): Zero initialize instruction fields. (arcExtMap_instName): Remove. (arcExtMap_insn): New function. (dump_ARC_extmap): More info while debuging. (arcExtMap_genOpcode): New function. * arc-dis.c (find_format): New function. (print_insn_arc): Use find_format. (arc_get_disassembler): Enable dump_ARC_extmap only when debugging. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-12Remove unneeded AUX register symbols.Claudiu Zissulescu5-0/+414
gas/ 2016-03-31 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (preprocess_operands): Mark AUX symbol. (arc_adjust_symtab): New function. * config/tc-arc.h (ARC_FLAG_AUX): Define. (obj_adjust_symtab): Likewise. * testsuite/gas/arc/taux.d: New file. * testsuite/gas/arc/taux.s: Likewise. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-09MIPS/GAS: Sanitize `.option picX' pseudo-opMaciej W. Rozycki7-1/+56
gas/ * config/tc-mips.c (s_option): Sanitize `.option picX' pseudo-op. * testsuite/gas/mips/option-pic-1.d: New test. * testsuite/gas/mips/option-pic-2.l: New list test. * testsuite/gas/mips/option-pic-1.s: New test source. * testsuite/gas/mips/option-pic-2.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-09MIPS/GAS: Disallow `.option picX' with VxWorks PICMaciej W. Rozycki7-3/+35
gas/ * config/tc-mips.c (s_option): Reject `.option picX' if VxWorks PIC. * testsuite/gas/mips/option-pic-vxworks-1.l: New list test. * testsuite/gas/mips/option-pic-vxworks-2.l: New list test. * testsuite/gas/mips/option-pic-vxworks-1.s: New test source. * testsuite/gas/mips/option-pic-vxworks-2.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2016-04-09MIPS/GAS: Correct call formatting in `can_swap_branch_p'Maciej W. Rozycki2-5/+9
gas/ * config/tc-mips.c (can_swap_branch_p): Correct call formatting.
2016-04-09GAS: Fix a typo in `as_bad' descriptionMaciej W. Rozycki2-1/+5
gas/ * messages.c (as_bad): Fix a typo in description.
2016-04-09MIPS/GAS: Unify messages in `mips_check_options'Maciej W. Rozycki2-2/+6
gas/ * config/tc-mips.c (mips_check_options): Unify messages.
2016-04-09MIPS/GAS: Use `opts->isa' consistently in `mips_check_options'Maciej W. Rozycki2-3/+8
gas/ * config/tc-mips.c (mips_check_options): Use `opts->isa' consistently.
2016-04-08Fix regexps in PR19910 test to cope with COFF and AOUT sparc targets.Nick Clifton2-3/+10
PR target/19910 * testsuite/gas/sparc/pr19910-1.d: Adjust regexps to work with COFF and AOUT sparc targets.
2016-04-07arc/nps400: Add new instructionsAndrew Burgess4-1/+41
Add some new control instructions to the opcodes library, and a new test for these new instructions to the assembler. The new instructions use an instruction flag longer than any seen before (on arc), and so the max flag length is extended to accommodate this. gas/ChangeLog: * config/tc-arc.h (MAX_FLAG_NAME_LENGTH): Increase to 7. * testsuite/gas/arc/nps400-2.d: New file. * testsuite/gas/arc/nps400-2.s: New file. opcodes/ChangeLog: * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions. * arc-opc.c (arc_flag_operands): Add new flags. (arc_flag_classes): Add new classes.
2016-04-07gas/arc: Handle multiple arc_opcode chains for same mnemonicAndrew Burgess2-12/+69
This commit completes support for having multiple instructions with the same mnemonic in non-contiguous blocks within the arc_opcodes table. The commit adds an iterator mechanism for the arc_opcode_hash_entry structure, which is then used in find_opcode_match to consider all arc_opcode entries with the same mnemonic, even when these instructions are stored in non-contiguous blocks. I extend the comment on the arc_opcodes table to discuss how entries within the table are organised, and to mention how instructions can be split into multiple groups if needed, but that the table is still searched in table order. There should be no user visible changes after this commit. gas/ChangeLog: * config/tc-arc.c (struct arc_opcode_hash_entry_iterator): New structure. (arc_opcode_hash_entry_iterator_init): New function. (arc_opcode_hash_entry_iterator_next): New function. (find_opcode_match): Iterate over all arc_opcode entries referenced by the arc_opcode_hash_entry passed in as a parameter. opcodes/ChangeLog: * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
2016-04-07gas/arc: Additional work to support multiple arc_opcode chainsAndrew Burgess2-35/+46
Building on earlier commits, this commit moves along support for having multiple arc_opcode entries in the arc_opcodes table that have the same mnemonic (name) field, but are not stored in a contiguous block in the table. In this commit we support looking up the arc_opcode_hash_entry from the hash table, and passing this along to the find_opcode_match function, which then finds the specific arc_opcode that we're assembling. We still don't actually support the multiple chains of arc_opcode entries in this commit, but the limitation is now isolated to the find_opcode_match function. There is no user visible change after this commit. gas/ChangeLog: * config/tc-arc.c (arc_find_opcode): Now returns arc_opcode_hash_entry pointer. (find_opcode_match): Update argument type, extract arc_opcode from incoming arc_opcode_hash_entry. (find_special_case_pseudo): Update return type. (find_special_case_flag): Update return type. (find_special_case): Update return type. (assemble_tokens): Lookup arc_opcode_hash_entry based on instruction mnemonic, then use find_opcode_match to identify specific arc_opcode.
2016-04-07gas/arc: Modify structure used to hold opcodesAndrew Burgess2-10/+65
The arc assembler builds a hash table to hold references to arc_opcode entries in the arc_opcodes table. This hash assumes that each mnemonic will always appear in a contiguous blocks within the arc_opcodes table; all ADD instruction will be together, all AND instructions will likewise be together and so on. The problem with this is that as different variations of arc are added, then it is often more convenient to split instructions apart, so all the base ADD instructions are together, but, variants of ADD specific to one variation of arc are grouped with other instructions specific to that arc variant. The current data structures don't support splitting the instructions in this way. This commit is a first step towards addressing this limitation. In this commit the hash table that currently holds arc_opcode pointers directly, instead holds a pointer to a new, intermediate, data structure. This new data structure holds the pointer to the arc_opcode. In this way, we can, in the future support having the intermediate structure hold multiple pointers to different arc_opcode groups. There should be no visible functional change after this commit. gas/ChangeLog: * config/tc-arc.c (struct arc_opcode_hash_entry): New structure. (arc_find_opcode): New function. (find_special_case_pseudo): Use arc_find_opcode. (find_special_case_flag): Likewise. (assemble_tokens): Likewise. (md_begin): Build hash using struct arc_opcode_hash_entry.
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