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2020-01-10HPUX gas testsuite fixesAlan Modra3-2/+8
* testsuite/gas/elf/pr14891.s: Don't start directives in first column. * testsuite/gas/elf/pr21661.d: Don't run on hpux.
2020-01-09Fix compile time warnings about comparisons always being false.Sergey Belyashov2-89/+101
PR 25224 gas * config/tc-z80.c (emit_ld_m_rr): Use integer types when checking opcode byte values. (emit_ld_r_r): Likewise. (emit_ld_rr_m): Likewise. (emit_ld_rr_nn): Likewise. opcodes * z80-dis.c (ld_ii_ii): Use character constant when checking opcode byte value.
2020-01-09x86: refine when to trigger optimizationsJan Beulich2-10/+15
Checking just the base opcode without also checking this isn't a VEX encoding, and without there being other insn properties avoiding a match once respective VEX/XOP/EXEX-encoded insns would appear, is at least dangerous. Add respective checks. At the same time there's no real need to check the extension opcode to be None for the 0xA8 form - there's nothing it can be confused with, and non-VEX-and-alike forms also can't appear.
2020-01-09x86-64: assert sane internal state for REX conversionsJan Beulich2-1/+8
For the comments about "hi" registers to be really applicable, RegRex may not be set on the respective registers. Assert this is the case.
2020-01-09x86: consistently convert to byte registers for TEST w/ imm optimizationJan Beulich2-11/+15
Commit ac0ab1842d ("i386: Also check R12-R15 registers when optimizing testq to testb") didn't go quite far enough: In order to avoid confusing other code registers would better be converted to byte ones uniformly.
2020-01-09x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMDJan Beulich7-0/+60
The disassembler change is such that in default mode we'd disassemble the insns (for there not ebing any conflicts), but when AMD64 mode was explicitly requested, we'd show them as "(bad)".
2020-01-08Document the fact that the assembler's alignment pseudo-ops can be issued ↵Nick Clifton2-9/+20
without any argumemtns. PR 25284 * doc/as.texi (Align): Document the fact that all arguments can be omitted. (Balign): Likewise. (P2align): Likewise.
2020-01-08Make the assembler generate an error if there is an attempt to define a ↵Nick Clifton6-0/+34
section with the same name as an already defined symbol. PR 14891 * config/obj-elf.c (obj_elf_section): Fail if the section name is already defined as a different symbol type. * testsuite/gas/elf/pr14891.s: New test source file. * testsuite/gas/elf/pr14891.d: New test driver. * testsuite/gas/elf/pr14891.s: New test expected error output. * testsuite/gas/elf/elf.exp: Run the new test.
2020-01-08ubsan: z8k: index 10 out of bounds for type 'unsigned int const[10]'Alan Modra2-2/+7
The fix is the additional ARRAY_SIZE test, the rest just tidies variable types rather than adding a cast to avoid warnings. opcodes/ * z8k-dis.c: Include libiberty.h (instr_data_s): Make max_fetched unsigned. (z8k_lookup_instr): Make nibl_index and tabl_index unsigned. Don't exceed byte_info bounds. (output_instr): Make num_bytes unsigned. (unpack_instr): Likewise for nibl_count and loop. * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and idx unsigned. * z8k-opc.h: Regenerate. gas/ * config/tc-z8k.c (md_begin): Make idx unsigned. (get_specific): Likewise for this_index.
2020-01-07[ARC] Improve parsing instruction operands.Claudiu Zissulescu2-91/+117
We use gas' expression function to parse the operands of an instruction in a generic way. There are situations when we have labels and registers having the same name as well as the substraction sign doesn't always stands for the arithmetical operation but for the register range (e.g. enter instruction). This patch improves parsing symbols found in a instruction operand, cleans up code and avoids using default or undefined variables. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (parse_reloc_symbol): New function. (tokenize_arguments): Clean up, use parse_reloc_symbol function. (md_operand): Set X_md to absent. (arc_parse_name): Check for X_md.
2020-01-03Allow individual targets to decide if string escapes should be allowed. ↵Sergey Belyashov7-9/+22
Disable for PPC and Z80. PR 25311 * as.h (TC_STRING_ESCAPES): Provide a default definition. * app.c (do_scrub_chars): Use TC_STRING_ESCAPES instead of NO_STRING_ESCAPES. * read.c (next_char_of_string): Likewise. * config/tc-ppc.h (TC_STRING_ESCAPES): Define. * config/tc-z80.h (TC_STRING_ESCAPES): Define.
2020-01-03Updated Swedish translation for the GAS subdirectory.Nick Clifton2-408/+185
2020-01-03Arm64: correct address index operands for LD1RO{H,W,D}Jan Beulich3-24/+29
Just like their LD1RQ{H,W,D} counterparts, as per the specification the index registers get scaled by element size.
2020-01-03Arm64: correct {su,us}dot SIMD encodingsJan Beulich3-12/+34
According to the specification these permit the Q bit to control the vector length operated on, and hence this bit should not already be set in the opcode table entries (it rather needs setting dynamically). Note how the test case output did also not match its input. Besides correcting the test case also extend it to cover both forms.
2020-01-03Arm64: correct uzp{1,2} mnemonicsJan Beulich3-8/+13
According to the specification, and in line with the pre-existing predicate forms, the mnemonics do not include an 'i'.
2020-01-03Arm64: correct 64-bit element fmmla encodingJan Beulich3-3/+8
There's just one bit of difference to the 32-bit element form, as per the documentation.
2020-01-02Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. ↵Sergey Belyashov69-3430/+15547
Add an ELF based target for these as well. PR 25224 bfd * Makefile.am: Add z80-elf target support. * configure.ac: Likewise. * targets.c: Likewise. * config.bfd: Add z80-elf target support and new arches: ez80 and z180. * elf32-z80.c: New file. * archures.c: Add new z80 architectures: eZ80 and Z180. * coffcode.h: Likewise. * cpu-z80.c: Likewise. * bfd-in2.h: Likewise plus additional Z80 relocations. * coff-z80.c: Add new relocations for Z80 target and local label check. gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support for assembler code generated by SDCC. Add new relocation types. Add z80-elf target support. * config/tc-z80.h: Add z80-elf target support. Enable dollar local labels. Local labels starts from ".L". * testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict. * testsuite/gas/all/fwdexp.s: Likewise. * testsuite/gas/z80/suffix.d: Fix failure on ELF target. * testsuite/gas/z80/z80.exp: Add new tests * testsuite/gas/z80/dollar.d: New file. * testsuite/gas/z80/dollar.s: New file. * testsuite/gas/z80/ez80_adl_all.d: New file. * testsuite/gas/z80/ez80_adl_all.s: New file. * testsuite/gas/z80/ez80_adl_suf.d: New file. * testsuite/gas/z80/ez80_isuf.s: New file. * testsuite/gas/z80/ez80_z80_all.d: New file. * testsuite/gas/z80/ez80_z80_all.s: New file. * testsuite/gas/z80/ez80_z80_suf.d: New file. * testsuite/gas/z80/r800_extra.d: New file. * testsuite/gas/z80/r800_extra.s: New file. * testsuite/gas/z80/r800_ii8.d: New file. * testsuite/gas/z80/r800_z80_doc.d: New file. * testsuite/gas/z80/z180.d: New file. * testsuite/gas/z80/z180.s: New file. * testsuite/gas/z80/z180_z80_doc.d: New file. * testsuite/gas/z80/z80_doc.d: New file. * testsuite/gas/z80/z80_doc.s: New file. * testsuite/gas/z80/z80_ii8.d: New file. * testsuite/gas/z80/z80_ii8.s: New file. * testsuite/gas/z80/z80_in_f_c.d: New file. * testsuite/gas/z80/z80_in_f_c.s: New file. * testsuite/gas/z80/z80_op_ii_ld.d: New file. * testsuite/gas/z80/z80_op_ii_ld.s: New file. * testsuite/gas/z80/z80_out_c_0.d: New file. * testsuite/gas/z80/z80_out_c_0.s: New file. * testsuite/gas/z80/z80_reloc.d: New file. * testsuite/gas/z80/z80_reloc.s: New file. * testsuite/gas/z80/z80_sli.d: New file. * testsuite/gas/z80/z80_sli.s: New file. ld * Makefile.am: Add new target z80-elf * configure.tgt: Likewise. * emultempl/z80.em: Add support for eZ80 and Z180 architectures. * emulparams/elf32z80.sh: New file. * emultempl/z80elf.em: Likewise. * testsuite/ld-z80/arch_ez80_adl.d: Likewise. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180.d: Likewise. * testsuite/ld-z80/labels.s: Likewise. * testsuite/ld-z80/relocs.s: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/z80.exp: Likewise. opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
2020-01-02[ARM][gas] fix build breakage with gcc-10 by using correct enum typeSzabolcs Nagy2-1/+6
Fixes ../../gas/config/tc-arm.c: In function 'parse_reg_list': ../../gas/config/tc-arm.c:1946:35: error: implicit conversion from 'enum reg_list_els' to 'enum arm_reg_type' [-Werror=enum-conversion] 1946 | reg = arm_reg_parse (&str, REGLIST_RN); | ^~~~~~~~~~ gas/ChangeLog: * config/tc-arm.c (parse_reg_list): Use REG_TYPE_RN instead of REGLIST_RN.
2020-01-01Re: Update year range in copyright notice of binutils filesAlan Modra1-0/+4
Add the ChangeLog entry.
2020-01-01Update year range in copyright notice of binutils filesAlan Modra567-570/+570
2020-01-01ChangeLog rotationAlan Modra2-4872/+4886
2019-12-27x86: adjust ignored prefix warning for branchesJan Beulich5-14/+27
There's no reason to not also issue them in Intel syntax mode, and it can be quite helpful to mention the actual insn (after all there can be multiple on a single line).
2019-12-27x86-64: correct / adjust prefix emissionJan Beulich10-63/+72
First and foremost REX must come last. Next JumpInterSegment branches can't possibly have a REX prefix, as they're consistently CpuNo64. And finally make BND prefix handling in output_branch() consistent with that of other prefixes in the same function, and make its placement among prefixes consistent with output_jump() (which, oddly enough, still isn't the supposedly canonical order specified by the *_PREFIX definitions).
2019-12-27x86-64: fix Intel64 handling of branch with data16 prefixJan Beulich6-24/+71
The expectation of x86-64-branch-3 for "call" / "jmp" with an obvious direct destination to translate to an indirect _far_ branch is plain wrong. The operand size prefix should have no effect at all on the interpretation of the operand. The main underlying issue here is that the Intel64 templates of the direct branches don't include Disp16, yet various assumptions exist that it would always be there when there's also Disp32/Disp32S, toggled by the operand size prefix (which is being ignored by direct branches in Intel64 mode). Along these lines it was also wrong to base the displacement width decision solely on the operand size prefix: REX.W cancels this effect and hence needs taking into consideration, too. A disassembler change is needed here as well: XBEGIN was wrongly treated the same as direct CALL/JMP, which isn't the case - the operand size prefix does affect displacement size there, it's merely ignored when it comes to updating [ER]IP.
2019-12-27x86: consolidate Disp<NN> handling a littleJan Beulich4-46/+65
In memory operand addressing, which forms of displacement are permitted besides Disp8 is pretty clearly limited - outside of 64-bit mode, Disp16 or Disp32 only, depending on address size (MPX being special in not allowing Disp16), - in 64-bit mode, Disp32s or Disp64 without address size override, and solely Disp32 with one. Adjust assembler and i386-gen to match this, observing that templates already get adjusted before trying to match them against input depending on the presence of an address size prefix. This adjustment logic gets extended to all cases, as certain DispNN values should also be dropped when there's no such prefix. In fact behavior of the assembler, perhaps besides the exact diagnostics wording, should not differ between there being templates applicable to 64-bit and non-64-bit at the same time, or there being fully separate sets of templates, with their DispNN settings already reduced accordingly. This adjustment logic further gets guarded such that there wouldn't be and Disp<N> conversion based on address size prefix when this prefix doesn't control the width of the displacement (on branches other than absolute ones). These adjustments then also allow folding two MOV templates, which had been split between 64-bit and non-64-bits variants so far. Once in this area also - drop the bogus DispNN from JumpByte templates, leaving just the correct Disp8 there (compensated by i386_finalize_displacement() now setting Disp8 on their operands), - add the missing Disp32S to XBEGIN. Note that the changes make it necessary to temporarily mark a test as XFAIL; this will get taken care of by a subsequent patch. The failing parts are entirely bogus and will get replaced.
2019-12-17Remove tic80 supportAlan Modra2-1/+5
This is one way of fixing ubsan bug reports, just delete the code. The assembler support was removed back in 2005 along with other non-BFD assemblers, but somehow the remainder of the port stayed in. bfd/ * coff-tic80.c: Delete file. * cpu-tic80.c: Delete file. * archures.c: Remove tic80 support. * coffcode.h: Likewise. * coffswap.h: Likewise. * targets.c: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * Makefile.am: Likewise. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. binutils/ * testsuite/binutils-all/objcopy.exp: Remove tic80 support. * testsuite/binutils-all/objdump.exp: Likewise. gas/ * doc/as.texi: Remove mention of tic80. include/ * coff/tic80.h: Delete file. * opcode/tic80.h: Delete file. ld/ * emulparams/tic80coff.sh: Delete file. * scripttempl/tic80coff.sc: Delete file. * configure.tgt: Remove tic80 support. * Makefile.am: Likewise. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. opcodes/ * tic80-dis.c: Delete file. * tic80-opc.c: Delete file. * disassemble.c: Remove tic80 support. * disassemble.h: Likewise. * Makefile.am: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2019-12-12i386: Also check R12-R15 registers when optimizing testq to testbH.J. Lu5-3/+25
Similar to SP, BP, SI and DI registers, R12-R15 registers must use REX prefix for the low byte register when optimizing test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 PR gas/25274 * config/tc-i386.c (optimize_encoding): Also check R12-R15 registers for "test $imm7, %r64/%r32/%r16 -> test $imm7, %r8" optimization. * testsuite/gas/i386/x86-64-optimize-3.s: Add tests for test with r12. * testsuite/gas/i386/x86-64-optimize-3.d: Updated. * testsuite/gas/i386/x86-64-optimize-3b.d: Likewise.
2019-12-12i386: Add tests for -malign-branch-boundary and -malign-branchH.J. Lu55-0/+2616
Add tests for -malign-branch-boundary, -malign-branch and -mbranches-within-32B-boundaries. gas/ * testsuite/gas/i386/align-branch-1.s: New file. * testsuite/gas/i386/align-branch-1a.d: Likewise. * testsuite/gas/i386/align-branch-1b.d: Likewise. * testsuite/gas/i386/align-branch-1c.d: Likewise. * testsuite/gas/i386/align-branch-1d.d: Likewise. * testsuite/gas/i386/align-branch-1e.d: Likewise. * testsuite/gas/i386/align-branch-1f.d: Likewise. * testsuite/gas/i386/align-branch-1g.d: Likewise. * testsuite/gas/i386/align-branch-1h.d: Likewise. * testsuite/gas/i386/align-branch-2.s: Likewise. * testsuite/gas/i386/align-branch-2a.d: Likewise. * testsuite/gas/i386/align-branch-2b.d: Likewise. * testsuite/gas/i386/align-branch-2c.d: Likewise. * testsuite/gas/i386/align-branch-3.d: Likewise. * testsuite/gas/i386/align-branch-3.s: Likewise. * testsuite/gas/i386/align-branch-4.s: Likewise. * testsuite/gas/i386/align-branch-4a.d: Likewise. * testsuite/gas/i386/align-branch-4b.d: Likewise. * testsuite/gas/i386/align-branch-5.d: Likewise. * testsuite/gas/i386/align-branch-5.s: Likewise. * testsuite/gas/i386/align-branch-6.d: Likewise. * testsuite/gas/i386/align-branch-6.s: Likewise. * testsuite/gas/i386/align-branch-7.d: Likewise. * testsuite/gas/i386/align-branch-7.s: Likewise. * testsuite/gas/i386/align-branch-8.d: Likewise. * testsuite/gas/i386/align-branch-8.s: Likewise. * testsuite/gas/i386/x86-64-align-branch-1.s: Likewise. * testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1e.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1f.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1h.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-2.s: Likewise. * testsuite/gas/i386/x86-64-align-branch-2a.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-2b.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-2c.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-3.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-3.s: Likewise. * testsuite/gas/i386/x86-64-align-branch-4.s: Likewise. * testsuite/gas/i386/x86-64-align-branch-4a.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-4b.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-5.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-6.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-7.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-7.s: Likewise. * testsuite/gas/i386/x86-64-align-branch-8.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-8.s: Likewise. * testsuite/gas/i386/i386.exp: Run new tests. ld/ * testsuite/ld-i386/align-branch-1.d: New file. * testsuite/ld-i386/align-branch-1.s: Likewise. * testsuite/ld-x86-64/align-branch-1.d: Likewise. * testsuite/ld-x86-64/align-branch-1.3: Likewise. * testsuite/ld-i386/i386.exp: Run the new test. * testsuite/ld-x86-64/x86-64.exp: Likewise.
2019-12-12i386: Add -mbranches-within-32B-boundariesH.J. Lu3-0/+31
Add -mbranches-within-32B-boundaries to enable -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5 * config/tc-i386.c (OPTION_MBRANCHES_WITH_32B_BOUNDARIES): New. (md_longopts): Add -mbranches-within-32B-boundaries. (md_parse_option): Handle -mbranches-within-32B-boundaries. (md_show_usage): Add -mbranches-within-32B-boundaries.
2019-12-12i386: Align branches within a fixed boundaryH.J. Lu4-3/+1160
Add 3 command-line options to align branches within a fixed boundary with segment prefixes or NOPs: 1. -malign-branch-boundary=NUM aligns branches within NUM byte boundary. 2. -malign-branch=TYPE[+TYPE...] specifies types of branches to align. The supported branches are: a. Conditional jump. b. Fused conditional jump. c. Unconditional jump. d. Call. e. Ret. f. Indirect jump and call. 3. -malign-branch-prefix-size=NUM aligns branches with NUM segment prefixes per instruction. 3 new rs_machine_dependent frag types are added: 1. BRANCH_PADDING. The variable size frag to insert NOP before branch. 2. BRANCH_PREFIX. The variable size frag to insert segment prefixes to an instruction. The choices of prefixes are: a. Use the existing segment prefix if there is one. b. Use CS segment prefix in 64-bit mode. c. In 32-bit mode, use SS segment prefix with ESP/EBP base register and use DS segment prefix without ESP/EBP base register. 3. FUSED_JCC_PADDING. The variable size frag to insert NOP before fused conditional jump. The new rs_machine_dependent frags aren't inserted if the previous item is a prefix or a constant directive, which may be used to hardcode an instruction, since there is no clear instruction boundary. Segment prefixes and NOP padding are disabled before relaxable TLS relocations and tls_get_addr calls to keep TLS instruction sequence unchanged. md_estimate_size_before_relax() and i386_generic_table_relax_frag() are used to handled BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. i386_generic_table_relax_frag() grows or shrinks sizes of segment prefix and NOP to align the next branch frag: 1. First try to add segment prefixes to instructions before a branch. 2. If there is no sufficient room to add segment prefixes, NOP will be inserted before a branch. * config/tc-i386.c (_i386_insn): Add has_gotpc_tls_reloc. (tls_get_addr): New. (last_insn): New. (align_branch_power): New. (align_branch_kind): New. (align_branch_bit): New. (align_branch): New. (MAX_FUSED_JCC_PADDING_SIZE): New. (align_branch_prefix_size): New. (BRANCH_PADDING): New. (BRANCH_PREFIX): New. (FUSED_JCC_PADDING): New. (i386_generate_nops): Support BRANCH_PADDING and FUSED_JCC_PADDING. (md_begin): Abort if align_branch_prefix_size < MAX_FUSED_JCC_PADDING_SIZE. (md_assemble): Set last_insn. (maybe_fused_with_jcc_p): New. (add_fused_jcc_padding_frag_p): New. (add_branch_prefix_frag_p): New. (add_branch_padding_frag_p): New. (output_insn): Generate a BRANCH_PADDING, FUSED_JCC_PADDING or BRANCH_PREFIX frag and terminate each frag to align branches. (output_disp): Set i.has_gotpc_tls_reloc to TRUE for GOTPC and relaxable TLS relocations. (output_imm): Likewise. (i386_next_non_empty_frag): New. (i386_next_jcc_frag): New. (i386_classify_machine_dependent_frag): New. (i386_branch_padding_size): New. (i386_generic_table_relax_frag): New. (md_estimate_size_before_relax): Handle COND_JUMP_PADDING, FUSED_JCC_PADDING and COND_JUMP_PREFIX frags. (md_convert_frag): Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. (OPTION_MALIGN_BRANCH_BOUNDARY): New. (OPTION_MALIGN_BRANCH_PREFIX_SIZE): New. (OPTION_MALIGN_BRANCH): New. (md_longopts): Add -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_parse_option): Handle -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (md_show_usage): Display -malign-branch-boundary=, -malign-branch-prefix-size= and -malign-branch=. (i386_target_format): Set tls_get_addr. (i386_cons_align): New. * config/tc-i386.h (i386_cons_align): New. (md_cons_align): New. (i386_generic_table_relax_frag): New. (md_generic_table_relax_frag): New. (i386_tc_frag_data): Add u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. (TC_FRAG_INIT): Initialize u, padding_address, length, max_prefix_length, prefix_length, default_prefix, cmp_size, classified and branch_type. * doc/c-i386.texi: Document -malign-branch-boundary=, -malign-branch= and -malign-branch-prefix-size=.
2019-12-12gas: Add md_generic_table_relax_fragH.J. Lu3-1/+18
Add md_generic_table_relax_frag for TC_GENERIC_RELAX_TABLE targets so that a backend can extend relax_frag beyond TC_GENERIC_RELAX_TABLE. * write.c (md_generic_table_relax_frag): New. Defined to relax_frag if not defined. (relax_segment): Call md_generic_table_relax_frag instead of relax_frag.
2019-12-12gas signed overflow fixesAlan Modra11-52/+68
* config/tc-aarch64.c (get_aarch64_insn): Avoid signed overflow. * config/tc-metag.c (parse_dalu): Likewise. * config/tc-tic4x.c (md_pcrel_from): Likewise. * config/tc-tic6x.c (tic6x_output_unwinding): Likewise. * config/tc-csky.c (parse_fexp): Use an unsigned char temp buffer. Don't use register keyword. Avoid signed overflow and remove now unneccesary char masks. Formatting. * config/tc-ia64.c (operand_match): Don't use shifts to sign extend. * config/tc-mep.c (mep_apply_fix): Likewise. * config/tc-pru.c (md_apply_fix): Likewise. * config/tc-riscv.c (load_const): Likewise. * config/tc-nios2.c (md_apply_fix): Likewise. Don't potentially truncate fixup before right shift. Tidy BFD_RELOC_NIOS2_HIADJ16 calculation.
2019-12-12obj-evax.c tidyAlan Modra2-29/+35
This started out as fixing decode_16, which used a char to index a 256 byte decodings array. When char is signed that could result in an out of bounds array access. The rest of the patch is for consistency and just general cleanup. * config/obj-evax.c (crc32, encode_32, encode_16, decode_16): Remove unnecessary prototypes. (number_of_codings): Delete, use ARRAY_SIZE instead throughout. (codings, decodings): Make arrays of unsigned char. (crc32): Use unsigned variables. Delete unnecessary mask. (encode_32, encode_16): Return unsigned char*, and make static buffer an unsigned char array. (decode_16): Make arg an unsigned char*. Remove useless casts. (shorten_identifier): Use unsigned char crc_chars. (is_truncated_identifier): Make ptr an unsigned char*.
2019-12-11[gas][arm] Add -mwarn-restrict-itAndre Vieira10-8/+29
Add a -m{no-}warn-restrict-it option to control IT related warnings in ARMv8-A and ARMv8-R. This is disabled by default. Committed on behalf of Wilco Dijkstra. gas/ChangeLog: 2019-12-11 Wilco Dijkstra <wdijkstr@arm.com> * config/tc-arm.c (warn_on_restrict_it): Add new variable. (it_fsm_post_encode): Check warn_on_restrict_it. (arm_option_table): Add -mwarn-restrict-it/-mno-warn-restrict-it. * testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: Add -mwarn-restrict-it. * testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: Likewise. * testsuite/gas/arm/armv8-a-bad.d: Likewise. * testsuite/gas/arm/armv8-a-it-bad.d: Likewise. * testsuite/gas/arm/armv8-r-bad.d: Likewise. * testsuite/gas/arm/armv8-r-it-bad.d: Likewise. * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: Likewise. * testsuite/gas/arm/udf.d: Likewise.
2019-12-11x86: further refine SSE check (SSE4a, SHA, GFNI)Jan Beulich7-25/+88
In ("x86: extend SSE check to PCLMULQDQ, AES, and GFNI insns") I went both a little too far and not quite far enough: - GFNI insns also have AVX512 variants, which also shouldn't get diagnosed, - SSE4a insns should get diagnosed just like SSE4.x ones, - SHA insns should get diagnosed just like PCLMULQDQ or AES ones.
2019-12-10[gas][arm] Set context table for '.arch_extension'Andre Vieira4-0/+20
This patch fixes .arch_extension behaviour. Currently, context table for '.arch_extension' is only set while "-march" processing, but it is not set while .arch processing, so following code is rejected .syntax unified .thumb .arch armv8.1-m.main .arch_extension mve.fp unless -march=armv8.1-m.main is given. Committing on behalf of Vladimir Murzin gas/ChangeLog: 2019-12-10 Vladimir Murzin <vladimir.murzin@arm.com> * config/tc-arm.c (s_arm_arch): Set selected_ctx_ext_table. * testsuite/gas/arm/mve-arch-ext.s: New. * testsuite/gas/arm/mve-arch-ext.d: New.
2019-12-09x86/Intel: fold "xmmword" with "oword"Jan Beulich2-11/+18
These are full aliases of one another, so there's no real need to use distinct O_md* values for them.
2019-12-09x86/Intel: support "mmword ptr"Jan Beulich7-5/+23
This is an alias of "qword ptr", commonly used with MMX insns. At this occasion also test (alongside the newly supported "mmword") - "zmmword" used as expression, - PADDB with "oword ptr" (aliasing "xmmword ptr").
2019-12-09x86/Intel: fix "near ptr" / "far ptr" handlingJan Beulich4-3/+24
Commit dc2be329b950 ("i386: Only check suffix in instruction mnemonic") broke rejecting of these for floating point insns. Fix this by setting the "byte" operand attribute, which will now (again) cause an error. Furthermore the diagnostic for the "far ptr" case in general and for the "near ptr" case in the non-float cases became "invalid instruction suffix" instead of the intended "operand size mismatch". Fix this by also setting the "tbyte" operand attribute (no insn template accepts both byte and tbyte operands).
2019-12-09x86/Intel: drop pointless suffix setting for "tbyte ptr"Jan Beulich2-10/+11
There are extremely few insns accepting "tbyte ptr" operand, so the "tbyte" operand flag checking done by match_operand_size() is already sufficient; the setting of the suffix has become meaningless anyway with dc2be329b950 ("i386: Only check suffix in instruction mnemonic"). Fold the code with that setting the "byte" operand flag to force an error (no insn at all accepts both "byte ptr" and tbyte ptr" operands, except for AnySize ones where the two (conflicting) recorded types don't matter (operand_size_match() doesn't call match_operand_size() in this case).
2019-12-09x86/Intel: drop pointless suffix setting for "fword ptr"Jan Beulich2-2/+5
No floating point insn accepts an "fword ptr" operand, so the "fword" operand flag checking done by match_mem_size() is already sufficient; the setting of the suffix has become meaningless anyway with dc2be329b950 ("i386: Only check suffix in instruction mnemonic").
2019-12-09x86/Intel: drop pointless special casing of LxSJan Beulich2-6/+6
LDS et al don't accept "word ptr" operands anyway, as per their insn templates. Hence there's no need to special case this here; the check has become dysfunctional anyway by dc2be329b950 ("i386: Only check suffix in instruction mnemonic").
2019-12-08aarch64*-*-*ilp32 gas testsAlan Modra14-36/+50
The new pac_negate_ra_state test adds yet another failure on aarch64 ipl32 targets. This patch fixes that particular problem and a few more that are trivial to fix. * testsuite/gas/aarch64/bfloat16.d: Match 32-bit and 64-bit output. * testsuite/gas/aarch64/dgh.d: Likewise. * testsuite/gas/aarch64/f32mm.d: Likewise. * testsuite/gas/aarch64/f64mm.d: Likewise. * testsuite/gas/aarch64/i8mm.d: Likewise. * testsuite/gas/aarch64/pac_ab_key.d: Likewise. * testsuite/gas/aarch64/pac_negate_ra_state.d: Likewise. * testsuite/gas/aarch64/reloc-prel_g0.d: Likewise. * testsuite/gas/aarch64/reloc-prel_g0_nc.d: Likewise. * testsuite/gas/aarch64/reloc-prel_g1.d: Likewise. * testsuite/gas/aarch64/sve-bfloat-movprfx.d: Likewise. * testsuite/gas/aarch64/sve-movprfx-mm.d: Likewise. * testsuite/gas/aarch64/sve2.d: Likewise.
2019-12-06[gas] Implement .cfi_negate_ra_state directiveKyrylo Tkachov4-0/+53
This patch implements the .cfi_negate_ra_state to be consistent with LLVM (https://reviews.llvm.org/D50136). The relevant DWARF code DW_CFA_AARCH64_negate_ra_state is multiplexed on top of DW_CFA_GNU_window_save, as per https://gcc.gnu.org/ml/gcc-patches/2017-08/msg00753.html I believe this is the simplest patch implementing this and is needed to allow users to build, for example, the Linux kernel with Armv8.3-A pointer authentication support with Clang while using gas as the assembler, which is a common usecase. gas/ 2019-12-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * dw2gencfi.c (cfi_pseudo_table): Add cfi_negate_ra_state. * testsuite/gas/aarch64/pac_negate_ra_state.s: New file. * testsuite/gas/aarch64/pac_negate_ra_state.d: Likewise.
2019-12-05Arm64: simplify Crypto arch extension handlingJan Beulich2-3/+6
This, at the assembler level, is just a "brace" feature covering both AES and SHA2. Hence there's no need for it to have a separate feature flag, freeing up a bit for future re-use. Along these lines there are also a number of dead definitions/variables in the opcode table file.
2019-12-05Arm64: correct "sha3" arch-extension directive handlingJan Beulich7-45/+49
SHA2 is a prereq to SHA3, not part of it aiui. Hence disabling the latter should not also disable the former. In the course of adding respective tests also do away with the duplication of crypto.d's contents in crypto-directive.d.
2019-12-04x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifierJan Beulich9-8/+90
Since we accept these without suffix / operand size specifier, we should also do so with one. (The fact that we unilaterally accept these, other than far branches, rather than limiting them to Intel64 mode, will be taken care of later on.) Also take the opportunity and make sure "lfs <reg>, tbyte ptr <mem>" et al get rejected outside of 64-bit mode. This became broken by dc2be329b950 ("i386: Only check suffix in instruction mnemonic"). Furthermore cover lgdt et al in the Intel syntax handling as well, which continued to work after said commit just by coincidence.
2019-12-04x86-64/Intel: fix CALL/JMP with dword operandJan Beulich4-6/+31
While dc2be329b950 ("i386: Only check suffix in instruction mnemonic") has made the assembler accept these in the first place (they were wrongly rejected before), the generated code was still wrong in that it lacked an operand size override. (In 64-bit code, other than in 16- and 32-bit ones, CALL and JMP with memory operands are all entirely unambiguous: No operand size can have two meanings.)
2019-12-04x86: consolidate tracking of MMX register useJan Beulich2-9/+8
Just like for XMM/YMM/ZMM don't key this to any Cpu* flags. Instead include the two special insns (not having register operands) explicitly.
2019-12-04x86/Intel: extend MOVDIRI testingJan Beulich7-0/+23
Test also memory operands with operand size specifier, which was broken prior to dc2be329b950 ("i386: Only check suffix in instruction mnemonic"), due to the template not permitting any suffixes. Note that this uncovered a disassembler issue, which is being fixed here as well.
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