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2019-04-15[binutils, ARM, 16/16] Add support to VLDR and VSTR of system registersAndre Vieira6-4/+225
2019-04-15[binutils, ARM, 15/16] Add support for VSCCLRMAndre Vieira6-14/+158
2019-04-15[binutils, ARM, 13/16] Add support for CLRMAndre Vieira7-29/+150
2019-04-15[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Ma...Andre Vieira7-0/+189
2019-04-15[binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M MainlineAndre Vieira4-0/+121
2019-04-15[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_...Andre Vieira2-0/+42
2019-04-15[binutils, ARM, 9/16] New BFL instruction for Armv8.1-M MainlineAndre Vieira9-0/+102
2019-04-15[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18Andre Vieira2-0/+42
2019-04-15[binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M MainlineAndre Vieira7-0/+69
2019-04-15[binutils, ARM, 6/16] New BF instruction for Armv8.1-M MainlineAndre Vieira9-0/+142
2019-04-15[binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM...Andre Vieira2-0/+42
2019-04-15[binutils, ARM, 4/16] BF insns infrastructure with array of relocs in struct ...Andre Vieira2-271/+310
2019-04-15[binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real fo...Andre Vieira2-0/+64
2019-04-15[GAS, ARM, 2/16] Add CLI extension support for Armv8.1-M MainlineAndre Vieira6-4/+585
2019-04-15[binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLIAndre Vieira3-45/+68
2019-04-13[MIPS] Add i6500 CPU and fix i6400 default ASEsMatthew Fortune6-1/+63
2019-04-13[MIPS] Apply ASE information for the selected processorMatthew Fortune4-7/+51
2019-04-12GAS: S12Z: Remove definition of macro TC_M68K.John Darrington2-3/+4
2019-04-12GAS: tc-s12z.c: int -> bfd_booleanJohn Darrington2-206/+210
2019-04-11xtensa: gas: add relaxations testsMax Filippov13-0/+179
2019-04-11xtensa: gas: convert tests to run_dump_testsMax Filippov13-105/+63
2019-04-11xtensa: gas: clean up literal management codeMax Filippov2-60/+65
2019-04-11xtensa: gas: put .literal_position at section startMax Filippov5-25/+34
2019-04-11[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das6-33/+45
2019-04-11[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instructionSudakshina Das5-0/+39
2019-04-10Disable R_X86_64_PLT32 generation as branch marker on Solaris/x86Rainer Orth21-0/+426
2019-04-10te-cloudabi.hAlan Modra5-6/+41
2019-04-09[MIPS] Add RDHWR with the SEL field for MIPS R6.Robert Suchanek4-0/+71
2019-04-08x86: Define GNU_PROPERTY_X86_ISA_1_AVX512_BF16H.J. Lu5-2/+13
2019-04-08x86: Remove i386-*-kaos* and i386-*-chaos targetsH.J. Lu3-4/+6
2019-04-05x86: Add assembler -mx86-used-note=yes testH.J. Lu5-0/+59
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo16-1/+499
2019-04-05PowerPC conditional branch testAlan Modra9-0/+421
2019-04-05PowerPC disassembler: Don't emit trailing spacesAlan Modra13-56/+71
2019-04-04Add extended mnemonics for bctar. Fix setting of 'at' branch hints.Peter Bergner5-24/+286
2019-04-03gas: use literals/const16 for xtensa loop relaxationMax Filippov3-142/+65
2019-04-01[GAS, Arm] CLI with architecture sensitive extensionsAndre Vieira41-46/+2843
2019-03-28PR24390, Don't decode mtfsb field as a cr fieldAlan Modra3-8/+14
2019-03-21Remove strip_underscore from struct emulationAlan Modra3-6/+7
2019-03-21Teach a few targets to resolve BFD_RELOC_8Alan Modra6-46/+38
2019-03-19x86: Correct EVEX vector load/store optimizationH.J. Lu15-145/+196
2019-03-19x86: Correct EVEX to 128-bit EVEX optimizationH.J. Lu6-33/+200
2019-03-19ix86: Disable AVX512F when disabling AVX2H.J. Lu20-258/+276
2019-03-18Use temp_ilp and restore_ilp in more placesAlan Modra4-11/+8
2019-03-18Fix MRI mode testsuite failuresAlan Modra2-7/+8
2019-03-18x86: Pass -O0 to assembler for some testsH.J. Lu11-6/+23
2019-03-18x86: Optimize EVEX vector load/store instructionsH.J. Lu29-1/+974
2019-03-18x86: Encode 256-bit/512-bit VEX/EVEX insns with 128-bit VEXH.J. Lu6-15/+206
2019-03-17x86: Set optimize to INT_MAX for -OsH.J. Lu6-1/+30
2019-03-17x86: Correctly optimize EVEX to 128-bit VEX/EVEXH.J. Lu12-29/+470
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