aboutsummaryrefslogtreecommitdiff
path: root/gas
AgeCommit message (Collapse)AuthorFilesLines
2010-01-042010-01-04 Daniel Gutson <dgutson@codesourcery.com>Daniel Gutson5-51/+68
gas/ * config/tc-arm.c (do_neon_logic): Accept imm value in the third operand too. (operand_parse_code): OP_RNDQ_IMVNb renamed to OP_RNDQ_Ibig. (parse_operands): OP_NILO case removed, applied renaming. (insns): Neon shape changed for some logic instructions. gas/testsuite/ * gas/arm/neon-logic.d: New test case. * gas/arm/neon-logic.s: New file.
2010-01-042010-01-04 Daniel Gutson <dgutson@codesourcery.com>Daniel Gutson6-0/+59
gas/ * config/tc-arm.c (do_neon_ldx_stx): Added validation for vector load/store insns. gas/testsuite/ * gas/arm/neon-addressing-bad.d: New test case. * gas/arm/neon-addressing-bad.s: New file. * gas/arm/neon-addressing-bad.l: New file.
2010-01-04bfd/Alan Modra2-3/+8
* archures.c: Add bfd_mach_ppc_e500mc64. * bfd-in2.h: Regenerate. * cpu-powerpc.c (bfd_powerpc_archs): Add entry for bfd_mach_ppc_e500mc64. gas/ * config/tc-ppc.c (md_show_usage): Document -me500mc64. opcodes/ * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
2010-01-042010-01-03 Daniel Gutson <dgutson@codesourcery.com>Daniel Gutson6-69/+170
gas/ * config/tc-arm.c (struct arm_it): New flag 'is_neon'. (NEON_ENC_*): Macros renamed to _NEON_ENC_*. (NEON_ENCODE): New macro. (check_neon_suffixes): New macro. (do_vfp_cond_or_thumb): Set the 'is_neon' flag. (do_vfp_nsyn_opcode): Likewise. (do_vfp_nsyn_nmul): Use the new 'NEON_ENCODE' macro. (do_vfp_nsyn_cmp): Likewise. (do_neon_shl_imm): Likewise. (do_neon_qshl_imm): Likewise. (neon_dyadic_misc): Likewise. (do_neon_mac_maybe_scalar): Likewise. (do_neon_qdmulh): Likewise. (do_neon_qmovn): Likewise. (do_neon_qmovun): Likewise. (do_neon_movn): Likewise. (neon_mac_reg_scalar_long): Likewise. (do_neon_vmull): Likewise. (do_neon_trn): Likewise. (do_neon_ldx_stx): Likewise. (neon_dp_fixup): Changed signature and set the flag. (neon_three_same): Call the above with new signature. (neon_two_same): Likewise. (neon_imm_shift): Likewise. (neon_mul_mac): Likewise. (do_neon_abs_neg): Likewise. (neon_mixed_length): Likewise. (do_neon_ext): Likewise. (do_neon_mov): Likewise. (do_neon_tbl_tbx): Likewise. (do_neon_logic): Likewise, and use the new 'NEON_ENCODE' macro. (neon_compare): Likewise. (do_neon_shll): Likewise. (do_neon_cvt): Likewise. (do_neon_mvn): Likewise. (do_neon_dup): Likewise. (md_assemble): Call check_neon_suffixes (). gas/testsuite/ * gas/arm/neon-suffix-bad.d: New test case. * gas/arm/neon-suffix-bad.s: New file. * gas/arm/neon-suffix-bad.l: New file.
2010-01-01Move 2009 binutils ChangeLog to ChangeLog-2009.H.J. Lu4-4668/+4686
2009-12-282009-12-28 Daniel Gutson <dgutson@codesourcery.com>Daniel Gutson2-0/+20
* doc/c-arm.texi: Document NEON alignment specifiers.
2009-12-21Fix Thumb2 bl range options.Ramana Radhakrishnan2-32/+52
2009-12-21 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> Richard Earnshaw <richard.earnshaw@arm.com> * config/tc-arm.c (encode_thumb2_b_bl_offset): New. Refactored from md_apply_fix. (md_apply_fix): Fixup range checks for Thumb2 version of unconditional calls. Call encode_thumb2_b_bl_offset for unconditional branches / function calls.
2009-12-19 * gas/xc16x/xc16x.exp (*): Add missing " in timeout cases.Doug Evans2-41/+45
2009-12-19Replace VexNDS, VexNDD and VexLWP with VexVVVV.H.J. Lu2-14/+18
gas/ 2009-12-19 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_operands): Check vexvvvv instead of vexnds and vexndd. (build_modrm_byte): Check vexvvvv instead of vexnds, vexndd and vexlwp. opcodes/ 2009-12-19 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove VexNDS, VexNDD and VexLWP. Add VexVVVV. * i386-opc.h (VexNDS): Removed. (VexNDD): Likewise. (VexLWP): Likewise. (VEXXDS): New. (VEXNDD): Likewise. (VEXLWP): Likewise. (VexVVVV): Likewise. (i386_opcode_modifier): Remove vexnds, vexndd and vexlwp. Add vexvvvv. * i386-opc.tbl: Replace VexNDS with VexVVVV=1, VexNDD with VexVVVV=2 and VexLWP with VexVVVV=3. * i386-tbl.h: Regenerated.
2009-12-19 * gas/mips/eret-2.s: Add an instruction to fill a branch delayMaciej W. Rozycki3-1/+8
slot. * gas/mips/eret-2.d: Adjust accordingly.
2009-12-19 gas/Maciej W. Rozycki6-2/+48
* config/tc-mips.c (s_mips_ent): Also set BSF_FUNCTION for ".aent". gas/testsuite/ * gas/mips/aent.d: New test. * gas/mips/aent.s: Source for the new test. * gas/mips/mips.exp: Run it.
2009-12-182009-12-18 Steve Ellcey <sje@cup.hp.com>Steve Ellcey2-10/+14
* config/tc-hppa.c: Change access to access_ctr.
2009-12-17 PR binutils/10924Nick Clifton5-29/+47
* config/tc-arm.c (do_ldstv4): Do not allow r15 as the destination register. (do_mrs): Likewise. (do_mul): Likewise. * arm-dis.c: Add support for %<>ru and %<>rU formats to enforce unique register numbers. Extend support for %<>R format to thumb32 and coprocessor instructions. * gas/arm/unpredictable.s: Add more unpredictable instructions. * gas/arm/unpredictable.d: Add expected disassemblies.
2009-12-16Remove ByteOkIntel.H.J. Lu2-7/+22
gas/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_suffix): Set i.suffix to 0 in Intel syntax if size is ignored and b/l/w suffixes are illegal. (check_byte_reg): Remove byteokintel check. opcodes/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove ByteOkIntel. * i386-opc.h (ByteOkIntel): Removed. (i386_opcode_modifier): Remove byteokintel. * i386-opc.tbl: Remove ByteOkIntel. * i386-tbl.h: Regenerated.
2009-12-16Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode.H.J. Lu2-17/+25
gas/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_vex_prefix): Replace vex0f, vex0f38, vex0f3a, xop08, xop09 and xop0a with vexopcode. opcodes/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A. Add VexOpcode. * i386-opc.h (Vex0F): Removed. (Vex0F38): Likewise. (Vex0F3A): Likewise. (VexOpcode): New. (VEX0F): Likewise. (VEX0F38): Likewise. (VEX0F3A): Likewise. (XOP08): Defined as a macro. (XOP09): Likewise. (XOP0A): Likewise. (i386_opcode_modifier): Remove vex0f, vex0f38, vex0f3a, xop08, xop09 and xop0a. Add vexopcode. * i386-opc.tbl: Replace Vex0F with VexOpcode=0, Vex0F38 with VexOpcode=1, Vex0F3A with VexOpcode=2, XOP08 with VexOpcode=3, XOP09 with VexOpcode=4 and XOP0A with VexOpcode=5. * i386-tbl.h: Regenerated.
2009-12-16Replace VEX2SOURCES with XOP2SOURCES.H.J. Lu2-1/+6
gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_modrm_byte): Check XOP2SOURCES instead VEX2SOURCES. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (VEX2SOURCES): Renamed to ... (XOP2SOURCES): This.
2009-12-16Replace Vex2Sources and Vex3Sources with VexSources.H.J. Lu2-6/+13
gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_operands): Check vexsources instead of vex3sources. (build_modrm_byte): Check vexsources instead of vex2sources and vex3sources. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove Vex3Sources and Vex2Sources. Add VexSources. * i386-opc.h ()Vex2Sources: Removed. (Vex3Sources): Likewise. (VEX2SOURCES): New. (VEX3SOURCES): Likewise. (VexSources): Likewise. (i386_opcode_modifier): Remove vex2sources and vex3sources. Add vexsources. * i386-opc.tbl: Replace Vex2Sources with VexSources=1 and Vex3Sourceswith VexSources=2. * i386-tbl.h: Regenerated.
2009-12-16Remove VexW0 and VexW1. Add VexW.H.J. Lu2-5/+11
gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_vex_prefix): Replace vexw0/vexw1 with vexw. (build_modrm_byte): Likewise. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove VexW0 and VexW1. Add VexW. * i386-opc.h (VexW0): Removed. (VexW1): Likewise. (VEXW0): New. (VEXW1): Likewise. (VexW): Likewise. (i386_opcode_modifier): Remove vexw0 and vexw1. Add vexw. * i386-opc.tbl: Replace VexW0 with VexW=1 and VexW1 with Vex=2. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2009-12-162009-12-15 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu5-0/+28
* as.h (mempcpy): New. * configure.in: Check if mempcpy is declared. * configure: Regenerated. * config.in: Likewise.
2009-12-15Define VEX128 and VEX256.H.J. Lu2-1/+5
gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_vex_prefix): Use VEX256. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (VEX128): New. (VEX256): Likewise.
2009-12-14 PR binutils/10924Nick Clifton3-0/+169
* arm-dis.c (arm_opcodes): Specify %R in cases where using r15 results in unpredictable behaviour. (print_insn_arm): Handle %R. * gas/arm/unpredictable.s: New test case - checks the disassembly of instructions with unpredictable behaviour. * gas/arm/unpredictable.d: New file - expected disassembly.
2009-12-14Fix PR number typo.Nick Clifton1-1/+1
2009-12-14 PR gas/11089Nick Clifton2-3/+9
* config/tc-rx.c (rx_equ): Rename 'expr' to 'expression' in order to avoid shadowing a global symbol of the same name.
2009-12-14 * config/tc-microblaze.c (md_assemble): Rename 'imm' to 'immed' inNick Clifton2-67/+72
order to avoid shadowing global variable of the same name.
2009-12-112009-12-11 Quentin Neill <quentin.neill@amd.com>Sebastian Pop5-0/+15
gas/testsuite/ * gas/i386/fma4.d: Add test cases. * gas/i386/fma4.s: Add test cases. * gas/i386/x86-64-fma4.d: Add test cases. * gas/i386/x86-64-fma4.s: Add test cases. opcodes/ * i386-dis.c (get_vex_imm8): Extend logic to apply in all cases, to avoid fetching ahead for the immediate bytes when OP_E_memory has already been called. Fix indentation.
2009-12-11 * config/tc-arm.c (arm_init_frag): Set thumb MODE_RECORDED flag forAndrew Jenner2-3/+7
non-elf. (arm_handle_align): Re-enable assert for non-elf.
2009-12-11Add -Wshadow to the gcc command line options used when compiling the binutils.Nick Clifton44-890/+933
Fix up all warnings generated by the addition of this switch.
2009-12-102009-12-09 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-152/+226
* config/tc-i386.c (arch_entry): Add len and skip. (cpu_arch): Use STRING_COMMA_LEN. (MESSAGE_TEMPLATE): New. (show_arch): Likewise. (md_show_usage): Use show_arch.
2009-12-08Call symbol_same_p to check to if 2 symbols are the same.H.J. Lu7-2/+50
gas/ 2009-12-07 H.J. Lu <hongjiu.lu@intel.com> PR gas/11037 * expr.c (resolve_expression): Call symbol_same_p to check if 2 symbols are the same. * symbols.c (symbol_same_p): New. * symbols.h (symbol_same_p): Likewise. gas/testsuite/ 2009-12-07 H.J. Lu <hongjiu.lu@intel.com> PR gas/11037 * gas/i386/intelpic.s: Add testcases. * gas/i386/intelpic.d: Updated.
2009-12-04Support fxsave64 and fxrstor64.H.J. Lu6-4/+157
gas/testsuite/ 2009-12-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run x86-64-fxsave and x86-64-fxsave-intel. * gas/i386/rex.d: Updated for fxsave64. * gas/i386/x86-64-fxsave-intel.d: New. * gas/i386/x86-64-fxsave.d: Likewise. * gas/i386/x86-64-fxsave.s: Likewise. opcodes/ 2009-12-03 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (FXSAVE_Fixup): New. (FXSAVE): Likewise. (mod_table): Use FXSAVE on fxsave and fxrstor. * i386-opc.tbl: Add fxsave64 and fxrstor64. * i386-tbl.h: Regenerated.
2009-12-02 PR gas/11013Nick Clifton5-12/+44
* arm-dis.c (thumb32_opc): Adjust disassembly of QADD, QDADD, QSUB and QDSUB. * gas/arm/arch7em.d: Update expected disassembly. * gas/arm/thumb32.d: Likewise. * config/tc-arm.c (do_t_simd2): New function. (insns): Use do_t_simd2 for QADD, QDADD, QSUB and QDSUB.
2009-11-30config:Joseph Myers2-14/+23
* largefile.m4 (ACX_LARGEFILE): Require AC_CANONICAL_HOST and AC_CANONICAL_TARGET. bfd: * configure: Regenerate. binutils: * configure: Regenerate. gas: * configure: Regenerate. gdb: * configure: Regenerate. gprof: * configure: Regenerate. ld: * configure: Regenerate.
2009-11-30 PR gas/11032Nick Clifton2-3/+9
* config/tc-arm.c (relax_adr): Cope with a frag with no symbol.
2009-11-252009-11-17 Quentin Neill <quentin.neill@amd.com>Sebastian Pop4-9/+22
Sebastian Pop <sebastian.pop@amd.com> gas/testsuite/ * gas/i386/x86-64-fma4.d: Add new patterns. * gas/i386/x86-64-fma4.s: Same. * gas/i386/x86-64-xop.d: Adjusted. opcodes/ * i386-dis.c (get_vex_imm8): Increase bytes_before_imm when decoding the second source operand from the immediate byte. (OP_EX_VexW): Pass an extra integer to identify the second and third source arguments.
2009-11-19Allow lock on cmpxch16b.H.J. Lu4-0/+12
gas/testsuite/ 2009-11-19 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/lock-1.s: Add cmpxchg16b test. * gas/i386/lock-1-intel.d: Updated. * gas/i386/lock-1.d: Likewise. opcodes/ 2009-11-19 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add IsLockable to cmpxch16b. * i386-tbl.h: Regenerated.
2009-11-19 PR binutils/10924Nick Clifton7-29/+41
* gas/arm/arch4t-eabi.d: Restore previous expected dissambly of instructions using Immediate Offset addressing with an offset of zero. * gas/arm/arch4t.d: Likewise. * gas/arm/arm7t.d: Likewise. * gas/arm/xscale.d: Likewise. * gas/arm/wince-inst.d: Remove 'p' suffix from cmp, cmn, teq and tst instructions. PR binutils/10924 * arm-dis.c (print_insn_arm): Do not print an offset of zero when decoding Immediaate Offset addressing.
2009-11-19gas/Jan Beulich2-0/+6
2009-11-19 Jan Beulich <jbeulich@novell.com> * read.c (pseudo_set): Also call copy_symbol_attributes() for undefined target symbol.
2009-11-192009-11-18 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop2-84/+88
opcodes/ PR binutils/10973 * i386-dis.c (get_vex_imm8): Do not increment codep. Avoid incrementing bytes_before_imm when OP_E_memory has already forwarded the codep pointer. (OP_EX_VexW): Increment codep to skip mod/rm byte. gas/testsuite/ * gas/i386/x86-64-xop.d: Update patterns.
2009-11-182009-11-18 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop9-301/+16
gas/ * config/tc-i386.c (cpu_arch): Remove cvt16. (md_show_usage): Same. * doc/c-i386.texi: Same. gas/testsuite/ * gas/i386/cvt16.d: Removed. * gas/i386/cvt16.s: Removed. * gas/i386/x86-64-cvt16.d: Removed. * gas/i386/x86-64-cvt16.s: Removed. * gas/i386/i386.exp: Remove cvt16 and x86-64-cvt16 tests. opcodes/ * i386-dis.c (VEX_LEN_XOP_08_A0): Removed. (VEX_LEN_XOP_08_A1): Removed. (xop_table): Remove entries for VEX_LEN_XOP_08_A0 and VEX_LEN_XOP_08_A1. (vex_len_table): Same. * i386-gen.c (CPU_CVT16_FLAGS): Removed. (cpu_flags): Remove field for CpuCVT16. * i386-opc.h (CpuCVT16): Removed. (i386_cpu_flags): Remove bitfield cpucvt16. (i386-opc.tbl): Remove CVT16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
2009-11-18Remove suffix on fxsave.H.J. Lu2-9/+13
2009-11-18 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/rex.d: Remove suffix on fxsave.
2009-11-182009-11-18 Paul Brook <paul@codesourcery.com>Paul Brook2-1/+7
gas/ * config/tc-arm.c (arm_fpus): Add fpv4-sp-d16. (aeabi_set_public_attributes): Correctly mark VFPv3xD. include/opcode/ * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
2009-11-18bfd/Alan Modra2-2/+14
* bfd-in.h (_bfd_elf_ppc_at_tls_transform): Declare. * bfd-in2.h: Regenerate. * elf64-ppc.c (ppc64_elf_relocate_section): Move code for R_PPC64_TLS insn optimisation to.. * elf32-ppc.c (_bfd_elf_ppc_at_tls_transform): ..here. New function. (ppc_elf_relocate_section): Use it. gas/ * config/tc-ppc.c (md_assemble): Report error on invalid @tls operands and opcode.
2009-11-182009-11-17 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop14-8/+5360
Quentin Neill <quentin.neill@amd.com> gas/ * config/tc-i386.c (cpu_arch): Added .xop and .cvt16. (build_vex_prefix): Handle xop08. (md_assemble): Don't special case the constant 3 for insns using MODRM. (build_modrm_byte): Handle vex2sources. (md_show_usage): Add xop and cvt16. * doc/c-i386.texi: Document fma4, xop, and cvt16. gas/testsuite/ * gas/i386/i386.exp: Run xop and cvt16 in 32-bit mode. Run x86-64-xop and x86-64-cvt16 in 64-bit mode. * gas/i386/lwp.d: Update name of the testcase. * gas/i386/x86-64-xop.d: New. * gas/i386/x86-64-xop.s: New. * gas/i386/xop.d: New. * gas/i386/xop.s: New. * gas/i386/cvt16.d: New. * gas/i386/cvt16.s: New. opcodes/ * i386-dis.c (OP_Vex_2src_1): New. (OP_Vex_2src_2): New. (Vex_2src_1): New. (Vex_2src_2): New. (XOP_08): Added. (VEX_LEN_XOP_08_A0): Added. (VEX_LEN_XOP_08_A1): Added. (VEX_LEN_XOP_09_80): Added. (VEX_LEN_XOP_09_81): Added. (xop_table): Added an entry for XOP_08. Handle xop instructions. (vex_len_table): Added entries for VEX_LEN_XOP_08_A0, VEX_LEN_XOP_08_A1, VEX_LEN_XOP_09_80, VEX_LEN_XOP_09_81. (get_valid_dis386): Handle XOP_08. (OP_Vex_2src): New. * i386-gen.c (cpu_flag_init): Add CPU_XOP_FLAGS and CPU_CVT16_FLAGS. (cpu_flags): Add CpuXOP and CpuCVT16. (opcode_modifiers): Add XOP08, Vex2Sources. * i386-opc.h (CpuXOP): Added. (CpuCVT16): Added. (i386_cpu_flags): Add cpuxop and cpucvt16. (XOP08): Added. (Vex2Sources): Added. (i386_opcode_modifier): Add xop08, vex2sources. * i386-opc.tbl: Add entries for XOP and CVT16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
2009-11-17 * gas/arm/vfma1.d: Only run on ELF based targets.Nick Clifton8-34/+50
PR binutils/10924 * gas/arm/arch4t-eabi.d: Update expected disassembly. * gas/arm/arch4t.d: Likewise. * gas/arm/archv6t2.d: Likewise. * gas/arm/arm7t.d: Likewise. * gas/arm/inst.d: Likewise. * gas/arm/xscale.d: Likewise. PR binutils/10924 * arm-dis.c (arm_opcodes): Add patterns to match undefined LDRB instruction variants. Add pattern for MRS variant that was being confused with CMP. (arm_decode_shift): Place error message in a comment. (print_insn_arm): Note that writing back to the PC is unpredictable. Only print 'p' variants of cmp/cmn/teq/tst instructions if decoding for pre-V6 architectures.
2009-11-172009-11-17 Paul Brook <paul@codesourcery.com>Paul Brook9-13/+502
Daniel Jacobowitz <dan@codesourcery.com> gas/ * doc/c-arm.texi: Document .arch armv7e-m. * config/tc-arm.c (arm_ext_v6_dsp, arm_ext_v7m): New. (insns): Put Thumb versions of v5TExP instructions into arm_ext_v5exp also. Move some Thumb variants from arm_ext_v6_notm to arm_ext_v6_dsp. (arm_archs): Add armv7e-m architecture. (aeabi_set_public_attributes): Handle -march=armv7e-m. gas/testsuite/ * gas/arm/attr-march-armv7em.d: New test. * gas/arm/arch7em-bad.d: New test. * gas/arm/arch7em-bad.l: New test. * gas/arm/arch7em.d: New test. * gas/arm/arch7em.s: New test. include/elf/ * arm.h (TAG_CPU_ARCH_V7E_M): Define. include/opcode/ * arm.h (ARM_EXT_V6_DSP): Define. (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP. (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define. binutils/ * readelf.c (arm_attr_tag_CPU_arch): Add v7E-M. bfd/ * elf32-arm.c (using_thumb_only, arch_has_arm_nop, arch_has_thumb2_nop): Handle TAG_CPU_ARCH_V7E_M. (tag_cpu_arch_combine): Ditto. Correct MAX_TAG_CPU_ARCH test.
2009-11-17 * gas/rx/macros.inc (creg): Remove cpen.Nick Clifton6-87/+85
* gas/rx/mvfc.d: Remove expected uses of cpen register. * gas/rx/mvtc.d: Likewise. * gas/rx/popc.d: Likewise. * gas/rx/pushc.d: Likewise.
2009-11-16 * config/tc-arm.c (parse_operands): Encode APSR_nzcv as r15.Nick Clifton5-3/+122
(do_vmrs): New function. (do_vmsr): New function. (insns): Add vmrs and vmsr. * gas/arm/vfp1xD.s: Add vmrs and vmsr instructions. * gas/arm/vfp1xD.d: Update expected disassembly.
2009-11-14Check destination operand for lockable instructions.H.J. Lu13-156/+269
gas/ 2009-11-13 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (md_assemble): Check destination operand for lockable instructions. gas/testsuite/ 2009-11-13 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/lock-1-intel.d: Updated. * gas/i386/lock-1.d: Likewise. * gas/i386/lock-1.s: Likewise. * gas/i386/lockbad-1.l: Likewise. * gas/i386/lockbad-1.s: Likewise. * gas/i386/x86-64-lock-1-intel.d: Likewise. * gas/i386/x86-64-lock-1.d: Likewise. * gas/i386/x86-64-lock-1.s: Likewise. * gas/i386/x86-64-lockbad-1.l: Likewise. * gas/i386/x86-64-lockbad-1.s: Likewise.
2009-11-142009-11-13 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-1/+6
* config/tc-i386.c (_i386_insn): Don't use bit field on swap_operand.
2009-11-13Check rex_ignored.H.J. Lu3-0/+9
gas/testsuite/ 2009-11-13 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/rex.s: Add a test for VEX insn. * gas/i386/rex.d: Updated. opcodes/ 2009-11-13 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (print_insn): Check rex_ignored.
generated by cgit v1.1 at 2025-02-10 15:32:30 +0000