Age | Commit message (Collapse) | Author | Files | Lines |
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an undefined symbol is used in an expression.
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* doc/Makefile.in (internals.info): New target.
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against weak symbols.
Fixing RW failures.
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addresses like .+6.
Fixing more problems with new relaxing code.
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fixup at the right address within the frag.
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to an absolute value, instead increment it as needed.
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* config/tc-v850.c: Fix some indention problems.
(md_relax_table): Define for D9->D99 branch displacement
relaxing.
(md_convert_frag): Do something useful instead of aborting.
(md_estimate_size_before_relax): Likewise.
(md_assemble): Note if the matching instruction has a relaxable
operand. If it does, allocate frag with frag_var and don't
do any fixups.
So we can do 9bit displacement to 22bit displacement relaxing.
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* read.c (read_a_source_file): New hook md_cleanup().
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expression symbol for a complex fixup.
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hacks to improve parsing of complex hi, lo, zda, etc
expressions.
(md_assemble): Don't demand and eat a trailing ')' after finding
a v850 relocation prefix. Sign extend the constant in a
BFD_RELOC_LO16 expression. Do eat a trailing ')' after a complete
operand.
(parse_cons_expression_v850): Don't eat a trailing ')' after
finding a v850 relocation prefix.
Trying to get nec's sample code to assemble. Why oh why didn't JT try
to assemble any of their code...
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(TC_CONS_FIX_NEW): Likewise.
* config/tc-v850.c (parse_cons_expression_v850): New function.
(cons_fix_new_v850): Likewise.
So we can handle ".hword lo(_foo)".
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Fixing more tda stuff.
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for an unknown relocation type.
PR 10944.
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4 bytes of space.
Something off the todo list.
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differently for movea & sst/sld insns.
Working on tda for the v850.
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* config/obj-multi.h (obj_frob_file_after_relocs): Define.
* config/obj-ecoff.c (ecoff_format_ops): Initialize new
frob_file_after_relocs field.
* config/obj-elf.c (elf_format_ops): Likewise.
* config/tc-mips.c: Undefine obj_frob_file_after_relocs before
including obj-elf.h.
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specially if not ELF.
(md_apply_fix): Handle BFD_RELOC_64.
(tc_gen_reloc): Handle BFD_RELOC_64.
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relative reloc when BFD_ASSEMBLER and OBJ_AOUT (more ugly gas
reloc hacking).
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Don't check S_GET_OTHER.
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register with l.s or s.s.
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.type pseudo-op.
(obj_aout_type): New static function.
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and sdaoff expressions.
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* gas/v850/basic.exp: Run them.
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TC_V850 and OBJ_ELF.
* config/tc-v850.h (tc_fix_adjustable): Don't adjust any
pc-relative fixups.
Fixing more failures in the g++ testsuite.
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(md_pcrel_from_section): New function.
* config/tc-v850.h (MD_PCREL_FROM_SECTION): Define.
So we don't screw up pc-relative jumps/calls from one section
into another section within the same .o file.
Fixes global ctors/dtors to work with DECL_ONE_ONLY stuff.
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a constant with &~.
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assembler now always builds a symbol table, which means that
objdump will no longer report `No symbols in FILE'. Change the
expected output accordingly.
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* config/obj-elf.c (elf_frob_file): Move ECOFF debug processing to ...
(elf_frob_file_after_relocs): ... here. New function.
* config/obj-elf.h (obj_from_file_after_relocs): New macro.
* write.c (write_object_file): Call *frob_after_relocs after the
call to write_relocs.
* config/tc-alpha.c: Use new BFD_RELOC_ALPHA_ELF_LITERAL reloc.
* config/tc-alpha.c (load_expression): Don't SET_VALUE on the section
symbol, as this messes up linking. Instead, expand the recursive call
inline and change up the appropriate bits to get the 0x8000 offset
in the reloc addend.
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two symbols in the same segment to be adjusted.
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with a single 8bit or 16bit immediate operand.
We should correctly assemble just about everything except opcodes with:
multiple immediate operands,
3 register operands,
really weird stuff
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to mn10300_insert_operand based on the opcode format.
(mn10300_insert_operand): Accept and use extra shift count
parameter.
Matsushita
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* configure: Rebuild.
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formats rather than hard-coded constants.
Minor cleanup.
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instructions. Add missing test in do_mov1.
* gas/mn10300/mov1.s: Add missing test.
We should now assemble just about anything without any
immediate operands.
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are 7 bytes long. Write out instructions in big-endian format.
Matsushita.
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* gas/mn10300/{extend.s logical.s, loop.s, mov1.s}: Likewise.
* gas/mn10300/{mov2.s, mov3.s, mov4.s, movbu.s}: Likewise.
* gas/mn10300/{movhu.s, movm.s, muldiv.s, other.s}: Likewise.
* gas/mn10300/{shift.s, sub.s}: Likewise.
* gas/mn10300/basic.exp: Run them.
Beginnings of gas testsuite for mn10300. Matsushita.
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that all instructions are parsed correctly.
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(xmalloc, xrealloc): Don't declare.
* as.c: Don't include libiberty.h.
* expr.c, read.c, stabs.c, config/obj-coff.c: Likewise.
* config/tc-mips.c: Likewise.
* messages.c: Likewise.
(xstrerror): Don't declare.
* xmalloc.c: Remove.
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(system_registers, cc_names): Likewise.
(address_registers, data_registers, other_registers): New register
arrays.
(register_name, system_register_name, cc_name): Remove.
(mn10300_reloc_prefix): Likewise.
(data_register_name): New function.
(address_register_name, other_register_name): Likewise.
(md_assemble): Rough cut at parsing operands. Remove lots of
unwanted code.
(md_apply_fix3): Disable for now.
Checkpointing today's Matsushita work.
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<schwab@issan.informatik.uni-dortmund.de>
* config/tc-m68k.c (select_control_regs): New function, extracted
out of m68k_init_after_args.
(m68k_init_after_args): Use it.
(mri_chip): Use it here as well to update set of allowed control
regs for movec.
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(obj_elf_section): Add the section symbol to the symbol table.
* config/obj-elf.h (obj_begin): Define.
(elf_begin): Declare.
* as.c (perform_an_assembly_pass): Call obj_begin if it is
defined.
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from a PC relative reloc if TC_M68K.
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.uaxword available even if not OBJ_ELF.
(md_atof): Remove unused local variable wordP.
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with a single generic configuration. So break them up into two different
configurations. See the individual ChangeLogs for additional detail.
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