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2021-03-30x86: drop seg_entryJan Beulich3-45/+46
2021-03-30x86: drop REGNAM_{AL,AX,EAX}Jan Beulich3-3/+17
2021-03-30x86: adjust st(<N>) parsingJan Beulich2-6/+29
2021-03-30x86: integrate rc_op into struct _i386_insnJan Beulich2-43/+50
2021-03-30x86: integrate broadcast_op into struct _i386_insnJan Beulich2-43/+52
2021-03-30x86: integrate mask_op into struct _i386_insnJan Beulich2-55/+69
2021-03-30x86: make swap_2_operands() have unsigned parametersJan Beulich2-12/+25
2021-03-29x86: VPSADBW's source operands are also commutativeJan Beulich4-2/+10
2021-03-29x86: derive opcode encoding space attribute from base opcodeJan Beulich3-120/+173
2021-03-29TRUE/FALSE simplificationAlan Modra17-82/+59
2021-03-29gas int vs bfd_boolean fixesAlan Modra7-65/+83
2021-03-26x86-64: don't accept supposedly disabled MOVQ formsJan Beulich4-0/+31
2021-03-25[NIOS2] Fix disassembly of br.n instruction.Hafiz Abid Qadeer3-0/+19
2021-03-25x86: fix CMPXCHG8B special case when disallowing q suffix outside of 64-bit modeJan Beulich2-1/+5
2021-03-25x86: flag bad S/G insn operand combinationsJan Beulich12-176/+90
2021-03-25x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clearJan Beulich3-1/+11
2021-03-25x86: fix AMD Zen3 insnsJan Beulich8-28/+97
2021-03-25x86-64: limit breakage from gcc movdir64b et al workaroundJan Beulich16-35/+178
2021-03-25PR27647 PowerPC extended conditional branch mnemonicsAlan Modra3-8/+14
2021-03-24x86: derive opcode length from opcode valueJan Beulich2-16/+46
2021-03-24x86: derive mandatory prefix attribute from base opcodeJan Beulich3-73/+63
2021-03-24x86: don't use opcode_length to identify pseudo prefixesJan Beulich2-2/+8
2021-03-23x86: re-number PREFIX_0X<nn>Jan Beulich2-1/+5
2021-03-23x86: re-order two fields of struct insn_templateJan Beulich1-0/+6
2021-03-23x86: split opcode prefix and opcode space representationJan Beulich2-48/+33
2021-03-23x86: don't open-code PREFIX_NONEJan Beulich2-11/+12
2021-03-23x86: unbreak certain MPX insn operand formsJan Beulich5-27/+55
2021-03-22Add startswith function and use it instead of CONST_STRNEQ.Martin Liska3-5/+11
2021-03-19gas/app.c don't throw away spaces before slashAlan Modra2-1/+4
2021-03-182021-03-18 Christian Groessler <chris@groessler.org>Christian Groessler2-16/+31
2021-03-16RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructionsKuan-Lin Chen6-0/+170
2021-03-12aarch64: Add few missing system registersPrzemyslaw Wirkus6-0/+59
2021-03-12aix: implement TLS relocation for gas and ldClément Chigot3-45/+226
2021-03-12aix: implement R_TOCU and R_TOCL relocationsClément Chigot2-8/+163
2021-03-10x86/Intel: correct AVX512 S/G disassemblyJan Beulich7-930/+939
2021-03-10x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Jan Beulich8-16/+2372
2021-03-09x86: fold some prefix related attributes into a single oneJan Beulich2-9/+19
2021-03-09x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich12-7/+36
2021-02-26Correct an error message in the ARM assembler.Nick Clifton5-1/+31
2021-02-24PR23691, gas .y files vs. automatic make dependenciesAlan Modra8-216/+125
2021-02-19Fix compile time warnings when building riscv assembler.Nick Clifton2-3/+8
2021-02-19RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu5-175/+228
2021-02-18RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu2-24/+126
2021-02-17h8300 complains about new section defined without attributesAlan Modra2-0/+5
2021-02-16gas: Allow SHF_GNU_RETAIN on all sectionsH.J. Lu7-6/+66
2021-02-16x86: CVTPI2PD has special behaviorJan Beulich15-93/+164
2021-02-16x86: honor template rather than actual operands when updating i.xstateJan Beulich5-8/+16
2021-02-16x86: record register use for SIMD insns without respective explicit operandsJan Beulich9-0/+60
2021-02-16x86: make common property tests commonJan Beulich11-108/+24
2021-02-16x86: make 16-bit ENQCMD test actually test ENQCMDJan Beulich3-12/+23
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