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AgeCommit message (Expand)AuthorFilesLines
2021-07-01opcodes: constify & scope microblaze opcodesMike Frysinger2-2/+7
2021-07-01opcodes: constify aarch64_opcode_tablesMike Frysinger2-3/+9
2021-06-24gas: update csect alignment for PPC prefixed instructions on XCOFFClément Chigot2-0/+10
2021-06-22picojava assembler and disassembler fixesAlan Modra4-173/+159
2021-06-19ubsan errors when 32-bit bfdAlan Modra2-3/+7
2021-06-19ppc raw test failure when 32-bit bfdAlan Modra3-2/+7
2021-06-18gas: fold symbol table entries generated for .startof.() / .sizeof.()Jan Beulich5-8/+71
2021-06-17Fix an assertion failure in the AArch64 assembler triggered by incorrect inst...Nick Clifton5-3/+24
2021-06-17gas: handle csect in bss section for XCOFFClément Chigot2-3/+14
2021-06-17gas: ensure sections contents is zero for BFD_RELOC_PPC*_TLSM on XCOFF.Clément Chigot6-5/+107
2021-06-16gas: fix hex float parsing from .dcb.? directivesJan Beulich3-71/+75
2021-06-16gas: fix overflow diagnosticsJan Beulich6-10/+72
2021-06-15x86: bring "gas --help" output for --32 etc in sync with realityJan Beulich3-4/+15
2021-06-15x86: simplify .dispNN settingJan Beulich2-51/+24
2021-06-15x86: slightly simplify offset_in_range()Jan Beulich2-2/+7
2021-06-15x86: harmonize disp with imm handlingJan Beulich5-23/+79
2021-06-15x86: make offset_in_range()'s warning contents useful (again)Jan Beulich2-6/+7
2021-06-15x86: off-by-1 in offset_in_range()Jan Beulich7-1/+89
2021-06-15x86: permit parenthesized expressions again as addressing scale factorJan Beulich5-2/+26
2021-06-14gas: fold three as_warn() in emit_expr_with_reloc()Jan Beulich2-12/+6
2021-06-14gas: drop TC_ADDRESS_BYTES conditionalsJan Beulich3-5/+8
2021-06-11x86: Always define TC_PARSE_CONS_EXPRESSIONH.J. Lu3-3/+12
2021-06-11RISC-V: Update the riscv_opts.[rvc|rve] in the riscv_set_arch.Nelson Chu2-10/+14
2021-06-10arm: avoid "shadowing" of glibc function nameJan Beulich2-16/+24
2021-06-10arm: fix array-out-of-bounds upon register parsing errorJan Beulich2-1/+6
2021-06-10x86: suppress LEA optimization in a specific 16-bit caseJan Beulich5-3/+69
2021-06-08x86: cover a.out in recently added testsJan Beulich4-41/+47
2021-06-08x86: minor improvements to optimize_imm() (part II)Jan Beulich2-3/+7
2021-06-08x86: minor improvements to optimize_disp() (part II)Jan Beulich2-7/+10
2021-06-08x86-64: avoid bogus warnings with 32-bit addressingJan Beulich9-0/+89
2021-06-08x86: minor improvements to optimize_disp() (part I)Jan Beulich2-11/+18
2021-06-07x86: honor quoted figure braces in i386_att_operand()Jan Beulich4-8/+43
2021-06-07x86: better respect quotes in parse_operands()Jan Beulich4-14/+40
2021-06-07x86: allow unary operators to start a memory operandJan Beulich5-14/+40
2021-06-07x86: make symbol quotation check consistent in i386_att_operand()Jan Beulich5-7/+44
2021-06-07x86: correct absolute branch check with segment overrideJan Beulich2-9/+14
2021-06-07x86/Intel: drop unnecessary bracket matching from parse_operands()Jan Beulich2-13/+8
2021-06-07x86: remove pointless 2nd parameter from check_VecOperations()Jan Beulich3-6/+11
2021-06-07x86: immediate operands don't allow for vector operationsJan Beulich2-10/+4
2021-06-07ix86: wrap constantsJan Beulich6-6/+165
2021-06-03PR1202, mcore disassembler: wrong address looptAlan Modra2-1/+6
2021-05-29PowerPC table driven -Mraw disassemblyAlan Modra4-0/+121
2021-05-29MIPS/GAS/testsuite: Add C0, C1, C2, C3 opcode testsMaciej W. Rozycki54-0/+7580
2021-05-29MIPS/GAS/testsuite: Run RFE test across all ISAsMaciej W. Rozycki8-7/+39
2021-05-29MIPS/GAS/testsuite: Run coprocessor tests across all ISAsMaciej W. Rozycki96-467/+1646
2021-05-29MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membershipMaciej W. Rozycki3-2/+53
2021-05-29MIPS/GAS/testsuite: Add tests for coprocessor branch instructionsMaciej W. Rozycki16-0/+215
2021-05-29MIPS/opcodes: Disassemble the RFE instructionMaciej W. Rozycki4-0/+26
2021-05-29MIPS/opcodes: Add legacy CP1 control register namesMaciej W. Rozycki9-29/+47
2021-05-29MIPS/GAS/testsuite: Add tests for coprocessor access instructionsMaciej W. Rozycki27-0/+2180
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