| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-01-23 | MIPS/GAS: Remove a stale OPTION_COMPAT_ARCH_BASE option marker | Maciej W. Rozycki | 2 | -1/+5 |
| 2018-01-23 | Enable Intel PCONFIG instruction. | Igor Tsimbalist | 10 | -1/+74 |
| 2018-01-23 | Enable Intel WBNOINVD instruction. | Igor Tsimbalist | 10 | -0/+74 |
| 2018-01-23 | MIPS/GAS: Correct `as --help' always reporting `o32' as the default ABI | Maciej W. Rozycki | 2 | -3/+13 |
| 2018-01-23 | MIPS/GAS: Add missing `-mmips16e2'/`-mno-mips16e2' help text | Maciej W. Rozycki | 2 | -0/+8 |
| 2018-01-22 | GAS/doc: Correct `.set nomips16e2' directive description syntax | Maciej W. Rozycki | 2 | -2/+7 |
| 2018-01-22 | Fix the RX assembler so that it can handle escaped double quote characters, i... | Oleg Endo | 5 | -2/+30 |
| 2018-01-19 | [gas/ARM] Remove spurious comments | Thomas Preud'homme | 2 | -2/+5 |
| 2018-01-17 | RISC-V: Fix bug in prior addi/c.nop patch. | Jim Wilson | 2 | -0/+15 |
| 2018-01-17 | Replace CET bit with IBT and SHSTK bits. | Igor Tsimbalist | 12 | -6/+69 |
| 2018-01-16 | Update translations for various binutils components. | Nick Clifton | 2 | -2448/+2647 |
| 2018-01-15 | RISC-V: Add support for addi that compresses to c.nop. | Jim Wilson | 3 | -2/+9 |
| 2018-01-15 | [ARM] Add new macro for Thumb-only opcodes | Thomas Preud'homme | 2 | -9/+27 |
| 2018-01-15 | [ARM] Enable conditional Armv8-M instructions | Thomas Preud'homme | 3 | -11/+27 |
| 2018-01-15 | [ARM] No IT usage deprecation for ARMv8-M | Thomas Preud'homme | 7 | -54/+70 |
| 2018-01-15 | Update Ukranian translations for bfd, binutils, gas, gold, ld and opcodes | Nick Clifton | 2 | -2446/+2678 |
| 2018-01-13 | Update pot files | Nick Clifton | 2 | -2430/+2597 |
| 2018-01-13 | Bump version number to 2.30.51 | Nick Clifton | 2 | -10/+14 |
| 2018-01-13 | Add note about 2.30 branch creation to changelogs | Nick Clifton | 1 | -0/+1 |
| 2018-01-13 | Add 2.30 markers to NEWS files. | Nick Clifton | 2 | -0/+6 |
| 2018-01-12 | Fix compile time warning building aout targeted architectures. | Gunther Nikl | 2 | -3/+10 |
| 2018-01-11 | Remove VL variants for 4FMAPS and 4VNNIW insns. | Igor Tsimbalist | 20 | -1030/+36 |
| 2018-01-11 | gas tc-arm.c warning fix | Alan Modra | 2 | -1/+6 |
| 2018-01-10 | x86: fix Disp8 handling for scalar AVX512_4FMAPS insns | Jan Beulich | 13 | -381/+402 |
| 2018-01-10 | x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variants | Jan Beulich | 7 | -0/+46 |
| 2018-01-09 | RISC-V: Disassemble x0 based addresses as 0. | Jim Wilson | 3 | -0/+21 |
| 2018-01-09 | [Arm] Add CSDB instruction | James Greenhalgh | 6 | -0/+44 |
| 2018-01-09 | Add support for the AArch64's CSDB instruction. | James Greenhalgh | 2 | -1/+6 |
| 2018-01-08 | x86: Properly encode vmovd with 64-bit memeory | H.J. Lu | 5 | -0/+145 |
| 2018-01-08 | Add a description of the X86_64 assembler's .largcomm pseudo-op. | Nick Clifton | 2 | -1/+16 |
| 2018-01-04 | RISC-V: Add 2 missing privileged registers. | Jim Wilson | 3 | -24/+33 |
| 2018-01-03 | Update year range in copyright notice of binutils files | Alan Modra | 578 | -580/+584 |
| 2018-01-03 | ChangeLog rotation | Alan Modra | 2 | -4407/+4421 |
| 2018-01-02 | Fix typo in do_mrs function in ARM assembler. | Nick Clifton | 2 | -1/+7 |
| 2017-12-28 | RISC-V: Add missing privileged spec registers. | Jim Wilson | 3 | -0/+522 |
| 2017-12-20 | RISC-V: Add compressed instruction hints, and a few misc cleanups. | Jim Wilson | 14 | -0/+110 |
| 2017-12-19 | Correct disassembly of dot product instructions. | Tamar Christina | 3 | -434/+446 |
| 2017-12-19 | Add support for V_4B so we can properly reject it. | Tamar Christina | 5 | -3/+35 |
| 2017-12-18 | Resolve PR 22493 - the encoding to be used when pushing the stack pointer ont... | Nick Clifton | 2 | -0/+11 |
| 2017-12-18 | x86: fold certain AVX and AVX2 templates | Jan Beulich | 2 | -38/+52 |
| 2017-12-18 | x86: fold RegXMM/RegYMM/RegZMM into RegSIMD | Jan Beulich | 4 | -125/+146 |
| 2017-12-18 | x86: drop FloatReg and FloatAcc | Jan Beulich | 2 | -11/+18 |
| 2017-12-18 | x86: replace Reg8, Reg16, Reg32, and Reg64 | Jan Beulich | 3 | -133/+138 |
| 2017-12-17 | x86: Check pseudo prefix without instruction | H.J. Lu | 5 | -0/+32 |
| 2017-12-15 | x86: correct operand type checks | Jan Beulich | 2 | -4/+9 |
| 2017-12-15 | x86: correct abort check | Jan Beulich | 2 | -2/+7 |
| 2017-12-14 | Update the address of the FSF in the copyright notice of files which were usi... | Nick Clifton | 8 | -21/+31 |
| 2017-12-13 | Add missing RISC-V fsrmi and fsflagsi instructions. | Jim Wilson | 3 | -0/+22 |
| 2017-12-13 | This patch enables disassembler_needs_relocs for PRU. It is needed to print c... | Dimitar Dimitrov | 3 | -0/+21 |
| 2017-12-12 | Don't mask X_add_number containing a register number | Alan Modra | 2 | -1/+6 |
