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2015-02-06gas: fix a few omissions in .cfi_label handlingJan Beulich2-1/+12
While actually starting to use that new directive, I noticed a few oversights of the original commit. gas/ 2015-02-06 Jan Beulich <jbeulich@suse.com> * dw2gencfi.c (select_cie_for_fde): Also bail on CFI_label. (cfi_change_reg_numbers): Also do nothing for CFI_label. (cfi_pseudo_table): Also handle .cfi_label when not supporting CFI directives.
2015-02-05Fix msp430 build with gcc-5Alan Modra2-2/+7
gcc-5 correctly complains "loop exit may only be reached after undefined behavior". I was going to correct this by checking the index before dereferencing the array rather than the other way around, but then I noticed it is possible for extract_cmd to write the terminating zero one past the end of "cmd". Fixing that means no index check is needed in md_assemble. * config/tc-msp430.c (md_assemble): Correct size passed to extract_cmd. Remove index check.
2015-02-04[AArch64] Add support for Cortex-A72Jiong Wang3-0/+8
2015-02-04 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_cpus): Add support for Cortex-A72. * doc/c-aarch64.texi (-mcpu=): Add "cortex-a72".
2015-02-04Fix encoding of "addw ax, [hl]" and "subw ax, [hl]".Nick Clifton2-1/+6
* config/rl78-parse.y (addsubw): Fix encoding of [HL] variant of these instructions.
2015-02-03[AARCH64] Document .arch and .arch_extension directiveJiong Wang2-0/+23
2015-02-03 Renlin Li <renlin.li@arm.com> gas/ * doc/c-aarch64.texi (.arch): Document the directive. (.arch_extension): Likewise.
2015-02-03Fix use of uninitialised memory by the RL78 port of GAS.Nick Clifton2-0/+7
* config/tc-rl78.h (TC_PARSE_CONS_EXPRESSION): Define.
2015-01-29NDS32: Set branch instruction to relaxable.Kuan-Lin Chen2-166/+277
Relaxable fragments can be relaxed when there are alignment requirements. Besides, insert a dummy fragment in the final to make sure that all alignment is traversed. Finally, convert these fragments in md_convert_frag with relax_table.
2015-01-28FT32 initial supportAlan Modra11-0/+1395
FT32 is a new 32-bit RISC core developed by FTDI for embedded applications. * configure.ac: Add FT32 support. * configure: Regenerate. bfd/ * Makefile.am: Add FT32 files. * archures.c (enum bfd_architecture): Add bfd_arch_ft32. (bfd_mach_ft32): Define. (bfd_ft32_arch): Declare. (bfd_archures_list): Add bfd_ft32_arch. * config.bfd: Handle FT32. * configure.ac: Likewise. * cpu-ft32.c: New file. * elf32-ft32.c: New file. * reloc.c (BFD_RELOC_FT32_10, BFD_RELOC_FT32_20, BFD_RELOC_FT32_17, BFD_RELOC_FT32_18): Define. * targets.c (_bfd_target_vector): Add ft32_elf32_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * Makefile.in: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. binutils/ * readelf.c: Add FT32 support. gas/ * Makefile.am: Add FT32 files. * config/tc-ft32.c: New file. * config/tc-ft32.h: New file. * configure.tgt: Add FT32 support. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. gas/testsuite/ * gas/ft32/ft32.exp: New file. * gas/ft32/insn.d: New file. * gas/ft32/insn.s: New file. include/ * dis-asm.h (print_insn_ft32): Declare. include/elf/ * common.h (EM_FT32): Define. * ft32.h: New file. include/opcode/ * ft32.h: New file. ld/ * Makefile.am: Add FT32 files. * configure.tgt: Handle FT32 target. * emulparams/elf32ft32.sh: New file. * scripttempl/ft32.sc: New file. * Makefile.in: Regenerate. opcodes/ * Makefile.am: Add FT32 files. * configure.ac: Handle FT32. * disassemble.c (disassembler): Call print_insn_ft32. * ft32-dis.c: New file. * ft32-opc.c: New file. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2015-01-27NDS32/gas: Limit the format of pseudo instruction la.Kuan-Lin Chen2-1/+15
2015-01-27NDS32/gas: Fix md_parse_name hook.Kuan-Lin Chen2-0/+12
2015-01-19Extend .reloc to accept some BFD_RELOCsAlan Modra7-1/+47
Tests that bfd_perform_reloc doesn't freak over a NONE reloc at end of section. gas/ * read.c (s_reloc): Match BFD_RELOC_NONE, BFD_RELOC{8,16,32,64}. * write.c (get_frag_for_reloc): Allow match just past end of frag. gas/testsuite/ * gas/all/none.s, * gas/all/none.d: New test. * gas/all/gas.exp: Run it.
2015-01-16S/390: Add support for IBM z13.Andreas Krebbel16-152/+1254
- 32 128 bit vector registers (overlapping with the existing 16 64 bit floating point registers) - vector double instructions - vector integer instructions - scalar vector instructions (allowing to have more floating point registers for scalar operations) - vector string instructions gas/ChangeLog: * config/tc-s390.c (struct pd_reg): Remove. (pre_defined_registers): Remove. (REG_NAME_CNT): Remove. (reg_name_search): Calculate the register number instead of doing a lookup. (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new reg_name_search signature. (s390_parse_cpu): Support the new arch string z13. (s390_insert_operand): Support for vector registers with the extra field for the fifth bit of each vector register operand. (md_gather_operand): Adjust to the new handling of optional parameters. * doc/as.texinfo: Document the z13 cpu string. gas/testsuite/ChangeLog: * gas/s390/esa-g5.d: Add a variant without the optional operand. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z10.d: For variants with a zero optional argument it is not dumped by objdump anymore. * gas/s390/zarch-zEC12.d: Likewise. * gas/s390/zarch-z13.d: New file. * gas/s390/zarch-z13.s: New file. * gas/s390/s390.exp: Run the test for the z13 files. include/opcode/ChangeLog: * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. ld/testsuite/ChangeLog: * ld-s390/tlsbin.dd: The nopr register operand is optional and not printed if 0 anymore. opcodes/ChangeLog: * s390-dis.c (s390_extract_operand): Support vector register operands. (s390_print_insn_with_opcode): Support new operands types and add new handling of optional operands. * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove and include opcode/s390.h instead. (struct op_struct): New field `flags'. (insertOpcode, insertExpandedMnemonic): New parameter `flags'. (dumpTable): Dump flags. (main): Parse flags from the s390-opc.txt file. Add z13 as cpu string. * s390-opc.c: Add new operands types, instruction formats, and instruction masks. (s390_opformats): Add new formats for .insn. * s390-opc.txt: Add new instructions.
2015-01-13[ARM] vcmp/vcmpe should accept #0x0 as an operandJiong Wang6-9/+38
gas/ 2015-01-13 Matthew Wahab <matthew.wahab@arm.com> * config/tc-arm.c (parse_ifimm_zero): Accept #0x0 as a synonym for #0, restoring previous behaviour. gas/testsuite/ 2015-01-13 Matthew Wahab <matthew.wahab@arm.com> * gas/arm/ual-vcmp.s: Add vcmp, vcmpe with #0x0 operand. * gas/ual/vcmp.d: Update expected output. * gas/ual/vcmp-zero-bad.l: Likewise
2015-01-12gas: allow labeling of CFI instructionsJan Beulich9-2/+130
When runtime patching code (like e.g. done by the Linux kernel) there may be cases where the set of stack frame alterations differs between unpatched and patched code. Consequently the corresponding unwind data needs patching too. Locating the right places within an FDE, however, is rather cumbersome without a way to insert labels in the resulting section. Hence this patch introduces a new directive, .cfi_label. Note that with the way CFI data gets emitted currently (at the end of the assembly process) this can't support local FB- and dollar-labels. gas/ 2015-01-12 Jan Beulich <jbeulich@suse.com> * gas/dw2gencfi.c (cfi_add_label, dot_cfi_label): New. (cfi_pseudo_table): Add "cfi_label". (output_cfi_insn): Handle CFI_label. (select_cie_for_fde): Als terminate CIE when encountering CFI_label. * dw2gencfi.h (cfi_add_label): Declare. (struct cfi_insn_data): New member "sym_name". (CFI_label): New. * read.c (read_symbol_name): Drop "static". * read.h (read_symbol_name): Declare. gas/testsuite/ 2015-01-12 Jan Beulich <jbeulich@suse.com> gas/cfi/cfi-label.d, gas/cfi/cfi-label.s: New. gas/cfi/cfi.exp: Run new tests.
2015-01-12arm: properly range check immediate operands of VSHL and VQSHLJan Beulich5-3/+59
These two, other than VQSHLU, didn't have their immediates properly range checked so far. (Re-sending unchanged from the original v2 due to never having got an answer to https://sourceware.org/ml/binutils/2013-04/msg00121.html.) gas/ 2015-01-12 Jan Beulich <jbeulich@suse.com> * gas/config/tc-arm.c (do_neon_shl_imm): Check immediate range. (do_neon_qshl_imm): Likewise. gas/testsuite/ 2015-01-12 Jan Beulich <jbeulich@suse.com> * gas/arm/neon-addressing-bad.s: Add test for invalid VSHL, VQSHL, and VQSHLU immediates. * gas/arm/neon-addressing-bad.l: Update accordingly.
2015-01-12Assorted compiler warning fixesAlan Modra2-2/+6
The C standard doesn't guarantee a function pointer can be cast to void* and vice versa. binutils/ * prdbg.c (print_debugging_info): Don't use void* for function pointer param. * budbg.h (print_debugging_info): Update prototype. gas/ * read.c (s_altmacro, s_reloc): Make definition static.
2015-01-10gas/avr: Prevent incorrect overflow errors for diff fixups.Andrew Burgess5-0/+42
When fixups are converted to a difference type within md_apply_fix, we previously left the contents of VALP (the value that was initially computed within write.c:fixup_segment) unchanged. This is harmless, except that this value is used within write.c:fixup_segment once we return from md_apply_fix to perform an overflow check. In some cases, the value computed in write.c:fixup_segment is so wrong that an overflow error can be triggered. These errors are incorrect. This patch avoids the overflow errors by adjusting the value in write.c:fixup_segment using the VALP pointer in md_apply_fix. A test for this issue is included. gas/ChangeLog: * config/tc-avr.c (md_apply_fix): Update the contents of VALP for diff fixups. gas/testsuite/ChangeLog: * gas/avr/large-debug-line-table.d: New file. * gas/avr/large-debug-line-table.s: New file.
2015-01-09This patch adds the necessary support to the assembler to allow wiringPhilipp Tomsich3-1/+20
the X-Gene scheduling description up in the respective GCC backend. * config/tc-arm.c (arm_cpus): Add support for APM X-Gene 1 and X-Gene 2. * doc/c-arm.texi (ARM Options): Mention xgene1 and xgene2.
2015-01-07arm: fix extension feature disablingJan Beulich2-15/+33
Using e.g. .arch_extension simd .arch_extension nocrypto so far results in SIMD support getting disabled, which I can't see being the purpose of the "no"-prefixed variants of architecture extension specifications. Of course it is questionable whether the current, counter intuitive behavior needs to be retained, and the new behavior perhaps be made work through e.g. a newly recognized "no-" prefix. gas/ 2015-01-07 Jan Beulich <jbeulich@suse.com> * gas/config/tc-arm.c (struct arm_option_extension_value_table): Split field "value" into fields "merge_value" and "clear_value". (arm_extensions): Adjust initializer accordingly.
2015-01-02Regenerate Makeile.in file for copyright updateAlan Modra2-2/+2
2015-01-02Correct printed year in copyright noticesAlan Modra2-1/+5
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra544-3734/+3769
2014-12-27Limit moxie sto/ldo offsets to 16 bitsAnthony Green2-8/+13
2014-12-25Don't pass unadorned zeros to varargs functionsYaakov Selkowitz2-2/+7
PR gas/17753 * config/tc-mep.c (md_begin): Specify types of vararg literals.
2014-12-24AVR: Document linker relaxation related options.Andrew Burgess2-0/+15
Adds documentation describing the -mlink-relax and -mno-link-relax command line options. gas/ChangeLog: * doc/c-avr.texi: Document -mlink-relax and -mno-link-relax.
2014-12-24AVR: Assembler now prepares for linker relaxation by default.Andrew Burgess6-11/+40
Have the assembler prepare for linker relaxation by default. This means that users will be able to make use of linker relaxation without having to adjust the assembler flags, this can make life easier when compiling libraries. Having this on by default in the assembler should make no difference to the assembler code produced, however, some of the debug information will be slightly less compressed. A few tests needed to be updated as a result of this change as they relied on linker relaxation support being off by default. I've tightened up the definition of which sections can be relaxed on AVR as part of this commit, the assembler used to think that all non-debugging sections could be relaxed, when in reality only code sections can be relaxed for AVR. The previous definition was not dangerous, just over cautious. The new tighter definition allows an extra test (gas/testsuite/gas/all/forward.d) to continue to pass. gas/ChangeLog: * config/tc-avr.c (struct avr_opt_s): Change link_relax to no_link_relax, extend comment. (enum options): Add new OPTION_NO_LINK_RELAX. (md_longopts): Add entry for -mno-link-relax. (md_parse_option): Handle OPTION_NO_LINK_RELAX, and update OPTION_LINK_RELAX. (md_begin): Initialise linkrelax from no_link_relax. (md_show_usage): Include -mno-link-relax option. (relaxable_section): Only allocatable code sections can be relaxed. * config/tc-avr.h (TC_LINKRELAX_FIXUP): Define. gas/testsuite/ChangeLog: * gas/all/gas.exp: Test will not pass on AVR due to linker relaxation support. * gas/avr/noreloc_withoutrelax.d: Add -mno-link-relax option. * gas/avr/link-relax-elf-flag-clear.d: Likewise. ld/testsuite/ChangeLog: * ld/testsuite/ld-avr/relax-elf-flags-02.d: Add -mno-link-relax option. * ld/testsuite/ld-avr/relax-elf-flags-03.d: Likewise. * ld/testsuite/ld-avr/relax-elf-flags-04.d: Likewise. * ld/testsuite/ld-avr/relax-elf-flags-05.d: Likewise. * ld/testsuite/ld-avr/relax-elf-flags-06.d: Likewise.
2014-12-23AVR: Only set link-relax elf flag when appropriate.Andrew Burgess7-1/+48
The AVR target uses a bit in the elf header flags to indicate if the object was assembled ready for linker relaxation. Previously this flag was always set, even when the object was not assembled ready for linker relaxation. This patch moves setting of the flag into the assembler, and sets it only when the assembler is preparing the file for linker relaxation. bfd/ChangeLog: * elf32-avr.c (bfd_elf_avr_final_write_processing): Don't set EF_AVR_LINKRELAX_PREPARED unconditionally. gas/ChangeLog: * config/tc-avr.c: Add include for elf/avr.h. (avr_elf_final_processing): New function. * config/tc-avr.h (elf_tc_final_processing): Define. (avr_elf_final_processing): Declare gas/testsuite/ChangeLog: * gas/avr/link-relax-elf-flag-clear.d: New file. * gas/avr/link-relax-elf-flag-set.d: New file. * gas/avr/link-relax-elf-flag.s: New file.
2014-12-23This patch add support for cpu marvell-whitney.Nick Clifton2-0/+7
* gas/config/tc-arm.c (arm_cpus): Add core marvell-whitney.
2014-12-23Updated translations for the gas and gprof tools.Nick Clifton3-3690/+6309
* po/es.po: Updated Esperanto translation. * po/fr.po: Updated French translation. * po/uk.po: Updated Ukrainian translation.
2014-12-19Rework the alignment check for BFD_RELOC_MIPS_18_PCREL_S3.Matthew Fortune9-26/+93
gas/ * config/tc-mips.c (md_apply_fix): Apply alignment check to the symbol and offset rather than *valP for BFD_RELOC_MIPS_18_PCREL_S3. Also update the error message for BFD_RELOC_MIPS_19_PCREL_S2. gas/testsuite/ * gas/mips/r6-64.s: Remove .align directives from LDPC instructions and add further tests for LDPC. * gas/mips/r6-64-n32.d: remove the NOPs from LDPC expected output and update for new tests. * gas/mips/r6-64-n64.d: Likewise. * gas/mips/ldpc-unalign.l: New file. * gas/mips/ldpc-unalign.s: Likewise. * gas/mips/mips.exp: Run ldpc-unalign test.
2014-12-19Fix octeon3 tests for targets with default abi != n32Matthew Fortune2-13/+17
gas/testsuite/ * gas/mips/octeon3.d: Switch to use numeric register names.
2014-12-16Fix octeon3 testsuite falloutMatthew Fortune7-6/+15
gas/testsuite/ * gas/mips/attr-gnu-4-5.d: Ignore ASEs. * gas/mips/attr-gnu-4-6.d: Likewise. * gas/mips/attr-gnu-4-7.d: Likewise. * gas/mips/attr-none-o32-fp64-nooddspreg.d: Likewise. * gas/mips/attr-none-o32-fp64.d: Likewise. * gas/mips/attr-none-o32-fpxx.d: Likewise.
2014-12-16Add in a JALRC alias and fix the NAL instruction.Matthew Fortune5-0/+19
opcodes/ * mips-opc.c (mips_builtin_opcodes): Add JALRC alias for JIALC. Remove the operand from NAL. gas/testsuite/ * gas/mips/r6.s: Test JALRC and NAL * gas/mips/r6-n32.d: Add expected output for JALRC and NAL. * gas/mips/r6-n64.d: Likewise. * gas/mips/r6.d: Likewise.
2014-12-14Mention --compress-debug-sections default in NEWSH.J. Lu2-0/+5
* NEWS: Mention --compress-debug-sections is on by default for Linux/x86.
2014-12-14Compress debug sections for Linux/x86 by defaultH.J. Lu2-0/+10
* config/tc-i386.c (flag_compress_debug): Default to compress debug sections for Linux.
2014-12-13PowerPC register numbers in DWARFAlan Modra4-3/+45
This makes gas .cfi output to .debug_frame match register numbering emitted by gcc. md_reg_eh_frame_to_debug_frame follows the ABI, targets not using it, notably Linux, don't. * config/tc-ppc.h (md_reg_eh_frame_to_debug_frame): Match current gcc behaviour. * config/te-aix.h: New file. * configure.tgt: Use em=aix for powerpc-aix.
2014-12-09Ensure zero termination of tic4x insn bufferChen Gang2-3/+10
* config/tc-tic4x.c (md_assemble): Ensure insn->name is zero terminated. Simplify concatenation of parallel insn.
2014-12-06Add Visium support to gasEric Botcazou36-31/+3824
gas/ * configure.tgt: Add Visium support. * Makefile.am (TARGET_CPU_CFILES): Move config/tc-vax.c around and add config/tc-visium.c. (TARGET_CPU_HFILES): Move config/tc-vax.h around and add config/tc-visium.h. * Makefile.in: Regenerate. * config/tc-visium.c: New file. * config/tc-visium.h: Likewise. * po/POTFILES.in: Regenerate. gas/testsuite/ * gas/elf/elf.exp: Skip ifunc-1 for Visium. * gas/visium/: New directory.
2014-11-30Power4 should treat mftb as extended mfspr mnemonicAlan Modra3-3/+8
On further reading of ISA manual it appears gas should have been treating mftb and mftbu as extended mnemonics for mfspr, for ISA 2.03 and later. opcodes/ * ppc-opc.c (powerpc_opcodes): Make mftb* generate mfspr for power4 and later. gas/testsuite/ * gas/ppc/a2.d: Update for mftb change. * gas/ppc/476.d: Likewise.
2014-11-28Remove broken nios2 assembler dwim support.Sandra Loosemore7-159/+29
2014-11-28 Sandra Loosemore <sandra@codesourcery.com> include/opcode/ * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete. (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete. (NIOS2_INSN_OPTARG): Renumber. opcodes/ * nios2-opc.c (nios2_r1_opcodes): Remove deleted attributes from descriptors. gas/ * config/tc-nios2.c (can_evaluate_expr, get_expr_value): Delete. (output_addi, output_andi, output_ori, output_xori): Delete. (md_assemble): Remove calls to deleted functions. gas/testsuite/ * gas/nios2/nios2.exp: Make "movi" a list test. * gas/nios2/movi.s: Adjust comments, add another case. * gas/nios2/movi.l: New. * gas/nios2/movi.d: Delete.
2014-11-26Fix trampolines search code for conditional branchesMax Filippov5-4/+29
For conditional branches that need more than one trampoline to reach its target assembler couldn't always find suitable trampoline because post-loop condition check was placed inside the loop, resulting in premature loop termination. Move check outside the loop. This fixes the following build errors seen when assembling huge files produced by gcc: Error: jump target out of range; no usable trampoline found Error: operand 1 of 'j' has out of range value '307307' 2014-11-25 Max Filippov <jcmvbkbc@gmail.com> gas/ * config/tc-xtensa.c (search_trampolines): Move post-loop condition check outside the search loop. gas/testsuite/ * gas/xtensa/trampoline.d: Add expected output for branches. * gas/xtensa/trampoline.s: Add test case for branches.
2014-11-24Update libtool.m4 from GCC trunkH.J. Lu2-2/+6
* libtool.m4: Updated from GCC trunk. bfd/ * configure: Regenerated. binutils/ * configure: Regenerated. gas/ * configure: Regenerated. gprof/ * configure: Regenerated. ld/ * configure: Regenerated. opcodes/ * configure: Regenerated.
2014-11-21Calculate ARM arch attribute after relaxationTerry Guo6-4/+41
gas/ 2014-11-21 Terry Guo <terry.guo@arm.com> * config/tc-arm.c (md_assemble): Do not consider relaxation. (md_convert_frag): Test and set target arch attribute accordingly. (aeabi_set_attribute_string): Turn it into a global function. * config/tc-arm.h (md_post_relax_hook): Enable it for ARM target. (aeabi_set_public_attributes): Declare it. gas/testsuite/ 2014-11-21 Terry Guo <terry.guo@arm.com> * gas/arm/attr-arch-assumption.d: New file. * gas/arm/attr-arch-assumption.s: Likewise. ld/testsuite/ 2014-11-21 Terry Guo <terry.guo@arm.com> * ld-arm/tls-longplt-lib.s: Require ARMv6T2. * ld-arm/tls-longplt.s: Likewise. * ld-arm/tls-longplt-lib.d: Updated. * ld-arm/tls-longplt.d: Likewise.
2014-11-21Support ARM Cortex-M7Terry Guo8-4/+240
include/ChangeLog: 2014-11-21 Terry Guo <terry.guo@arm.com> * opcode/arm.h (FPU_VFP_EXT_ARMV8xD): New macro. (FPU_VFP_V5D16): Likewise. (FPU_VFP_V5_SP_D16): Likewise. (FPU_ARCH_VFP_V5D16): Likewise. (FPU_ARCH_VFP_V5_SP_D16): Likewise. bfd/ChangeLog: 2014-11-21 Terry Guo <terry.guo@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Support FPv5. binutils/ChangeLog: 2014-11-21 Terry Guo <terry.guo@arm.com> * readelf.c (arm_attr_tag_FP_arch): Extended to support FPv5. gas/ChangeLog: 2014-11-21 Terry Guo <terry.guo@arm.com> * config/tc-arm.c (fpu_vfp_ext_armv8xd): New. (arm_cpus): Support cortex-m7. (arm_fpus): Support fpv5-sp-d16 and fpv5-d16. (do_vfp_nsyn_cvt_fpv8): Generate error when use D register for S register only target like FPv5-SP-D16. (do_neon_cvttb_1): Likewise. (do_vfp_nsyn_fpv8): Likewise. (do_vrint_1): Likewise. (aeabi_set_public_attributes): Set proper FP arch for FPv5. * doc/c-arm.texi: Document new cpu and fpu names for cortex-m7. gas/testsuite/ChangeLog: 2014-11-21 Terry Guo <terry.guo@arm.com> * gas/arm/armv7e-m+fpv5-d16.s: New. * gas/arm/armv7e-m+fpv5-d16.d: Likewise. * gas/arm/armv7e-m+fpv5-sp-d16.s: Likewise. * gas/arm/armv7e-m+fpv5-sp-d16.d: Likewise. ld/testsuite/ChangeLog: 2014-11-21 Terry Guo <terry.guo@arm.com> * ld-arm/attr-merge-vfp-4-sp.s: New test source file. * ld-arm/attr-merge-vfp-5-sp.s: Likewise. * ld-arm/attr-merge-vfp-5.s: Likewise. * ld-arm/attr-merge-vfp-8.d: New test. * ld-arm/attr-merge-vfp-8r.d: Likewise. * ld-arm/attr-merge-vfp-9.d: Likewise. * ld-arm/attr-merge-vfp-9r.d: Likewise. * ld-arm/attr-merge-vfp-10.d: Likewise. * ld-arm/attr-merge-vfp-10r.d: Likewise. * ld-arm/attr-merge-vfp-11.d: Likewise. * ld-arm/attr-merge-vfp-11r.d: Likewise. * ld-arm/attr-merge-vfp-12.d: Likewise. * ld-arm/attr-merge-vfp-12r.d: Likewise. * ld-arm/attr-merge-vfp-13.d: Likewise. * ld-arm/attr-merge-vfp-13r.d: Likewise. * ld-arm/attr-merge-vfp-14.d: Likewise. * ld-arm/attr-merge-vfp-14r.d: Likewise. * ld-arm/arm-elf.exp: Run the new tests.
2014-11-20* config/tc-arm.c (rotate_left): Avoid undefined behaviour when N = 0.Richard Earnshaw2-1/+6
2014-11-20[AArch64] Fix mis-detection of unpredictable load/store operations with FP regs.Richard Earnshaw3-11/+25
* config/tc-aarch64.c (warn_unpredictable_ldst): Check that transfer registers are in the GP register set. Adjust warnings. Use correct field member for address register. * testsuite/gas/aarch64/diagnostic.l: Update.
2014-11-19[AArch64] Warn on load pair to same registerJiong Wang5-0/+68
2014-11-19 Ryan Mansfield <rmansfield@qnx.com> * config/tc-aarch64.c (md_assemble): Call warn_unpredictable_ldst. (warn_unpredictable_ldst): New. 2014-11-19 Ryan Mansfield <rmansfield@qnx.com> * gas/aarch64/diagnostic.s: Add new warnings test patterns. * gas/aarch64/diagnostic.l: Update expected diagnostic output.
2014-11-18Add -z bndplt to generate BND prefix in PLT entriesIgor Zamyatin6-64/+58
This patch adds "-z bndplt" option Linux/x86-64 linker to generate BND prefix in PLT entries. It also updated Linux/x86-64 assembler not to generate R_X86_64_PLT32_BND nor R_X86_64_PC32_BND relocations. bfd/ 2014-11-18 Igor Zamyatin <igor.zamyatin@intel.com> * elf64-x86-64.c (elf_x86_64_check_relocs): Enable MPX PLT only for -z bndplt. gas/ 2014-11-18 Igor Zamyatin <igor.zamyatin@intel.com> * config/tc-i386-intel.c (i386_operator): Remove last argument from lex_got call. * config/tc-i386.c (reloc): Remove bnd_prefix from parameters' list. Return always BFD_RELOC_32_PCREL. * (output_branch): Remove condition for BFD_RELOC_X86_64_PC32_BND. * (output_jump): Update call to reloc accordingly. * (output_interseg_jump): Likewise. * (output_disp): Likewise. * (output_imm): Likewise. * (x86_cons_fix_new): Likewise. * (lex_got): Remove bnd_prefix from parameters' list in macro and declarations. Don't use BFD_RELOC_X86_64_PLT32_BND. * (x86_cons): Update call to lex_got accordingly. * (i386_immediate): Likewise. * (i386_displacement): Likewise. * (md_apply_fix): Don't use BFD_RELOC_X86_64_PLT32_BND nor BFD_RELOC_X86_64_PC32_BND. * (tc_gen_reloc): Likewise. include/ 2014-11-18 Igor Zamyatin <igor.zamyatin@intel.com> * bfdlink.h (struct bfd_link_info): Add bndplt. ld/ 2014-11-18 Igor Zamyatin <igor.zamyatin@intel.com> * emulparams/elf_x86_64.sh (BNDPLT): Set to yes for x86_64. * emultempl/elf32.em (gld${EMULATION_NAME}_handle_option): Handle "-z bndplt" if BNDPLT is yes. (gld${EMULATION_NAME}_list_options): Add "-z bndplt" entry. * ld.texinfo: Add description for bndplt. ld/testsuite/ 2014-11-18 Igor Zamyatin <igor.zamyatin@intel.com> * testsuite/ld-x86-64/bnd-ifunc-1.d: Add bndplt option. * testsuite/ld-x86-64/bnd-ifunc-2.d: Likewise. * testsuite/ld-x86-64/bnd-plt-1.d: Likewise. Update dissassembly sections. * testsuite/ld-x86-64/mpx.exp: Handle mpx3 and mpx4 tests. * testsuite/ld-x86-64/mpx1a.rd: Remove _BND from relocation name. * testsuite/ld-x86-64/mpx1c.rd: Likewise. * testsuite/ld-x86-64/mpx2a.rd: Likewise. * testsuite/ld-x86-64/mpx2c.rd: Likewise. * testsuite/ld-x86-64/mpx3.dd: New file. * testsuite/ld-x86-64/mpx3a.s: Likewise. * testsuite/ld-x86-64/mpx3b.s: Likewise. * testsuite/ld-x86-64/mpx4.dd: Likewise. * testsuite/ld-x86-64/mpx4a.s: Likewise. * testsuite/ld-x86-64/mpx4b.s: Likewise.
2014-11-18aarch64: allow adding/removing just feature flags via .arch_extensionJan Beulich7-12/+111
Rather than requiring to always also set/change the base architecture, allow just en-/disabling of architecture extensions, matching what ARM has.
2014-11-18[AArch64] Add xgene2.Philipp Tomsich3-1/+9
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