Age | Commit message (Collapse) | Author | Files | Lines |
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* po/gas.pot: Regenerated.
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(TC_FORCE_RELOCATION): Define.
(d10v_force_relocation): Declare.
* config/tc-d10v.c (tc_gen_reloc): Handle Vtable relocs.
(md_apply_fix3): Handle Vtable relocs.
(d10v_fix_adjustable): New.
(d10v_force_relocation): New.
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symbols
are ignored.
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* po/gas.pot: Regenerated.
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* configure.in: Add fr30-*-*.
* config/tc-fr30.c: New file.
* Makefile.in: Regenerated.
* config.in: Regenerated.
* configure: Regenerated.
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* config/tc-fr30.c: New file.
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are 16 bit insns.
PR 18135.
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* gas/m32r/wrongsize.s: New testcase.
PR 18135.
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* gas/m32r/m32r.exp: Run it.
* gas/m32r/fslotx.[sd]: New testcase.
* gas/m32r/m32rx.exp: Run it.
* gas/m32r/m32rx.[sd]: Update.
PR 18134.
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* app.c (do_scrub_begin): Set characters above 127 to be symbol
characters.
(do_scrub_chars): Add some casts to unsigned char to avoid
unwanted sign extension.
* read.c (lex_type): Set characters about 127 to be symbol
characters.
* config/tc-i386.c (md_begin): Set identifier_chars and
operand_chars for values above 127.
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* configure.in: detect cygwin* instead of cygwin32*
* configure: regenerate
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(append_insn): Account for the tx39's multiply behavior.
* mips.h (INSN_MULT): Added.
* mips-opc.c (IS_M): Added.
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WEAK handling.
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start-sanitize-r5900
Fri Oct 23 13:01:24 EDT 1998 Frank Ch. Eigler <fche@cygnus.com>
* gas/mips/vu0.[sd]: Update tests for VRNEXT and VRGET
instructions, to match corrected operand synatx.
end-sanitize-r5900
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MIPS_STABS_ELF is specified.
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* gas/i386/i386.exp: Run AMD insn test.
* gas/i386/amd.s: New test.
* gas/i386/amd.d: New test results.
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* doc/c-i386.texi: Replace occurences of "opcode" with
"instruction mnemonic", "instruction", or "mnemonic" when
referring to the name of an instruction. Use "opcode" when
referring to the sequence of machine bytes.
* config/tc-i386.c (opcode_chars): Rename to mnemonic_chars.
(is_opcode_char): Rename to is_mnemonic_char.
(md_assemble and i386_operand): Correct error messages from
"opcode" to "instruction mnemonic"
Rename throughout opcode[] -> mnemonic[], opp -> mnem_p,
MAX_OPCODE_SIZE -> MAX_MNEM_SIZE,
DWORD_OPCODE_SUFFIX -> DWORD_MNEM_SUFFIX,
WORD_OPCODE_SUFFIX -> WORD_MNEM_SUFFIX,
BYTE_OPCODE_SUFFIX -> BYTE_MNEM_SUFFIX,
SHORT_OPCODE_SUFFIX -> SHORT_MNEM_SUFFIX
LONG_OPCODE_SUFFIX -> LONG_MNEM_SUFFIX
* config/tc-i386.h (*_MNEM_SUFFIX): Rename from *_OPCODE_SUFFIX.
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* config/tc-i386.c (i386_operand): Check for garbage after
register name.
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for BFD_ASSEMBLER to only change value when COFF if TE_PE.
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* config/tc-sh.c (sh_force_relocation): Handle VT relocs.
(md_apply_fix): Likewise.
(tc_gen_reloc): Likewise.
(sh_fix_adjustable): New.
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* cgen.h (gas_cgen_finish_insn): Update prototype.
* config/tc-m32r.c (m32r_insn): CGEN_INT_INSN -> CGEN_INT_INSN_P.
cgen_insn_t -> CGEN_INSN_INT.
(make_parallel): Update handling of CGEN_INT_INSN_P.
(assemble_parallel_insn): Ditto.
(target_make_parallel): New function.
(md_assemble): Use it.
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converted into lower case.
pr17413
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(gas_cgen_tc_gen_reloc): Likewise.
* config/tc-m32r.h (obj_fix_adjustable): Define.
* config/tc-m32r.c (m32r_fix_adjustable): New.
(m32r_force_relocation): Handle VTABLE relocs.
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parsing.
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both set bits in the PSW as side effects.
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associated symbol.
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(elf32_sparc_force_relocation): Declare.
* tc-sparc.c (md_apply_fix3): Handle vtable relocs.
(tc_gen_reloc): Handle vtable relocs.
(elf32_sparc_force_relocation): New.
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* config/tc-v850.h (obj_fix_adjustable): Define.
(TC_FORCE_RELOCATION): Define.
(v850_force_relocation): Declare.
* config/tc-v850.c (tc_gen_reloc): Use offset instead
of fx_addnumber for VTABLE reloc addends.
(md_apply_fix3): Handle VTABLE relocs.
(v850_fix_adjustable): New.
(v850_force_relocation): New.
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(pa_ip): Do not automatically promote into pa2.0 mode.
(pa_level): Handle ".level 2.0".
start-sanitize-cygnus
(struct pa_it): New field "trunc".
(pa_parse_fp_cnv_format): New function.
(pa_parse_ftest_gfx_completer): New function.
(pa_ip): Handle various new letters for PA2.0 support.
end-sanitize-cygnus
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* config/tc-i386.c (md_assemble): Handle AMD_3DNOW_OPCODE.
* config/tc-i386.h (template.extension_opcode): Change to
unsigned int to allow full range of 8-bit opcode suffixes.
(None): Redefine as 0xffff.
From Jeff B Epler <jepler@usgs.gov>
* doc/c-i386.texi (i386-SIMD): New section.
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* read.h: Declare it.
* config/tc-alpha.c (s_alpha_mask, s_alpha_frame): Use it.
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a register name
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at assembly time.
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operand that should not be a register.
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