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2014-12-27Limit moxie sto/ldo offsets to 16 bitsAnthony Green2-8/+13
2014-12-25Don't pass unadorned zeros to varargs functionsYaakov Selkowitz2-2/+7
PR gas/17753 * config/tc-mep.c (md_begin): Specify types of vararg literals.
2014-12-24AVR: Document linker relaxation related options.Andrew Burgess2-0/+15
Adds documentation describing the -mlink-relax and -mno-link-relax command line options. gas/ChangeLog: * doc/c-avr.texi: Document -mlink-relax and -mno-link-relax.
2014-12-24AVR: Assembler now prepares for linker relaxation by default.Andrew Burgess6-11/+40
Have the assembler prepare for linker relaxation by default. This means that users will be able to make use of linker relaxation without having to adjust the assembler flags, this can make life easier when compiling libraries. Having this on by default in the assembler should make no difference to the assembler code produced, however, some of the debug information will be slightly less compressed. A few tests needed to be updated as a result of this change as they relied on linker relaxation support being off by default. I've tightened up the definition of which sections can be relaxed on AVR as part of this commit, the assembler used to think that all non-debugging sections could be relaxed, when in reality only code sections can be relaxed for AVR. The previous definition was not dangerous, just over cautious. The new tighter definition allows an extra test (gas/testsuite/gas/all/forward.d) to continue to pass. gas/ChangeLog: * config/tc-avr.c (struct avr_opt_s): Change link_relax to no_link_relax, extend comment. (enum options): Add new OPTION_NO_LINK_RELAX. (md_longopts): Add entry for -mno-link-relax. (md_parse_option): Handle OPTION_NO_LINK_RELAX, and update OPTION_LINK_RELAX. (md_begin): Initialise linkrelax from no_link_relax. (md_show_usage): Include -mno-link-relax option. (relaxable_section): Only allocatable code sections can be relaxed. * config/tc-avr.h (TC_LINKRELAX_FIXUP): Define. gas/testsuite/ChangeLog: * gas/all/gas.exp: Test will not pass on AVR due to linker relaxation support. * gas/avr/noreloc_withoutrelax.d: Add -mno-link-relax option. * gas/avr/link-relax-elf-flag-clear.d: Likewise. ld/testsuite/ChangeLog: * ld/testsuite/ld-avr/relax-elf-flags-02.d: Add -mno-link-relax option. * ld/testsuite/ld-avr/relax-elf-flags-03.d: Likewise. * ld/testsuite/ld-avr/relax-elf-flags-04.d: Likewise. * ld/testsuite/ld-avr/relax-elf-flags-05.d: Likewise. * ld/testsuite/ld-avr/relax-elf-flags-06.d: Likewise.
2014-12-23AVR: Only set link-relax elf flag when appropriate.Andrew Burgess7-1/+48
The AVR target uses a bit in the elf header flags to indicate if the object was assembled ready for linker relaxation. Previously this flag was always set, even when the object was not assembled ready for linker relaxation. This patch moves setting of the flag into the assembler, and sets it only when the assembler is preparing the file for linker relaxation. bfd/ChangeLog: * elf32-avr.c (bfd_elf_avr_final_write_processing): Don't set EF_AVR_LINKRELAX_PREPARED unconditionally. gas/ChangeLog: * config/tc-avr.c: Add include for elf/avr.h. (avr_elf_final_processing): New function. * config/tc-avr.h (elf_tc_final_processing): Define. (avr_elf_final_processing): Declare gas/testsuite/ChangeLog: * gas/avr/link-relax-elf-flag-clear.d: New file. * gas/avr/link-relax-elf-flag-set.d: New file. * gas/avr/link-relax-elf-flag.s: New file.
2014-12-23This patch add support for cpu marvell-whitney.Nick Clifton2-0/+7
* gas/config/tc-arm.c (arm_cpus): Add core marvell-whitney.
2014-12-23Updated translations for the gas and gprof tools.Nick Clifton3-3690/+6309
* po/es.po: Updated Esperanto translation. * po/fr.po: Updated French translation. * po/uk.po: Updated Ukrainian translation.
2014-12-19Rework the alignment check for BFD_RELOC_MIPS_18_PCREL_S3.Matthew Fortune9-26/+93
gas/ * config/tc-mips.c (md_apply_fix): Apply alignment check to the symbol and offset rather than *valP for BFD_RELOC_MIPS_18_PCREL_S3. Also update the error message for BFD_RELOC_MIPS_19_PCREL_S2. gas/testsuite/ * gas/mips/r6-64.s: Remove .align directives from LDPC instructions and add further tests for LDPC. * gas/mips/r6-64-n32.d: remove the NOPs from LDPC expected output and update for new tests. * gas/mips/r6-64-n64.d: Likewise. * gas/mips/ldpc-unalign.l: New file. * gas/mips/ldpc-unalign.s: Likewise. * gas/mips/mips.exp: Run ldpc-unalign test.
2014-12-19Fix octeon3 tests for targets with default abi != n32Matthew Fortune2-13/+17
gas/testsuite/ * gas/mips/octeon3.d: Switch to use numeric register names.
2014-12-16Fix octeon3 testsuite falloutMatthew Fortune7-6/+15
gas/testsuite/ * gas/mips/attr-gnu-4-5.d: Ignore ASEs. * gas/mips/attr-gnu-4-6.d: Likewise. * gas/mips/attr-gnu-4-7.d: Likewise. * gas/mips/attr-none-o32-fp64-nooddspreg.d: Likewise. * gas/mips/attr-none-o32-fp64.d: Likewise. * gas/mips/attr-none-o32-fpxx.d: Likewise.
2014-12-16Add in a JALRC alias and fix the NAL instruction.Matthew Fortune5-0/+19
opcodes/ * mips-opc.c (mips_builtin_opcodes): Add JALRC alias for JIALC. Remove the operand from NAL. gas/testsuite/ * gas/mips/r6.s: Test JALRC and NAL * gas/mips/r6-n32.d: Add expected output for JALRC and NAL. * gas/mips/r6-n64.d: Likewise. * gas/mips/r6.d: Likewise.
2014-12-14Mention --compress-debug-sections default in NEWSH.J. Lu2-0/+5
* NEWS: Mention --compress-debug-sections is on by default for Linux/x86.
2014-12-14Compress debug sections for Linux/x86 by defaultH.J. Lu2-0/+10
* config/tc-i386.c (flag_compress_debug): Default to compress debug sections for Linux.
2014-12-13PowerPC register numbers in DWARFAlan Modra4-3/+45
This makes gas .cfi output to .debug_frame match register numbering emitted by gcc. md_reg_eh_frame_to_debug_frame follows the ABI, targets not using it, notably Linux, don't. * config/tc-ppc.h (md_reg_eh_frame_to_debug_frame): Match current gcc behaviour. * config/te-aix.h: New file. * configure.tgt: Use em=aix for powerpc-aix.
2014-12-09Ensure zero termination of tic4x insn bufferChen Gang2-3/+10
* config/tc-tic4x.c (md_assemble): Ensure insn->name is zero terminated. Simplify concatenation of parallel insn.
2014-12-06Add Visium support to gasEric Botcazou36-31/+3824
gas/ * configure.tgt: Add Visium support. * Makefile.am (TARGET_CPU_CFILES): Move config/tc-vax.c around and add config/tc-visium.c. (TARGET_CPU_HFILES): Move config/tc-vax.h around and add config/tc-visium.h. * Makefile.in: Regenerate. * config/tc-visium.c: New file. * config/tc-visium.h: Likewise. * po/POTFILES.in: Regenerate. gas/testsuite/ * gas/elf/elf.exp: Skip ifunc-1 for Visium. * gas/visium/: New directory.
2014-11-30Power4 should treat mftb as extended mfspr mnemonicAlan Modra3-3/+8
On further reading of ISA manual it appears gas should have been treating mftb and mftbu as extended mnemonics for mfspr, for ISA 2.03 and later. opcodes/ * ppc-opc.c (powerpc_opcodes): Make mftb* generate mfspr for power4 and later. gas/testsuite/ * gas/ppc/a2.d: Update for mftb change. * gas/ppc/476.d: Likewise.
2014-11-28Remove broken nios2 assembler dwim support.Sandra Loosemore7-159/+29
2014-11-28 Sandra Loosemore <sandra@codesourcery.com> include/opcode/ * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete. (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete. (NIOS2_INSN_OPTARG): Renumber. opcodes/ * nios2-opc.c (nios2_r1_opcodes): Remove deleted attributes from descriptors. gas/ * config/tc-nios2.c (can_evaluate_expr, get_expr_value): Delete. (output_addi, output_andi, output_ori, output_xori): Delete. (md_assemble): Remove calls to deleted functions. gas/testsuite/ * gas/nios2/nios2.exp: Make "movi" a list test. * gas/nios2/movi.s: Adjust comments, add another case. * gas/nios2/movi.l: New. * gas/nios2/movi.d: Delete.
2014-11-26Fix trampolines search code for conditional branchesMax Filippov5-4/+29
For conditional branches that need more than one trampoline to reach its target assembler couldn't always find suitable trampoline because post-loop condition check was placed inside the loop, resulting in premature loop termination. Move check outside the loop. This fixes the following build errors seen when assembling huge files produced by gcc: Error: jump target out of range; no usable trampoline found Error: operand 1 of 'j' has out of range value '307307' 2014-11-25 Max Filippov <jcmvbkbc@gmail.com> gas/ * config/tc-xtensa.c (search_trampolines): Move post-loop condition check outside the search loop. gas/testsuite/ * gas/xtensa/trampoline.d: Add expected output for branches. * gas/xtensa/trampoline.s: Add test case for branches.
2014-11-24Update libtool.m4 from GCC trunkH.J. Lu2-2/+6
* libtool.m4: Updated from GCC trunk. bfd/ * configure: Regenerated. binutils/ * configure: Regenerated. gas/ * configure: Regenerated. gprof/ * configure: Regenerated. ld/ * configure: Regenerated. opcodes/ * configure: Regenerated.
2014-11-21Calculate ARM arch attribute after relaxationTerry Guo6-4/+41
gas/ 2014-11-21 Terry Guo <terry.guo@arm.com> * config/tc-arm.c (md_assemble): Do not consider relaxation. (md_convert_frag): Test and set target arch attribute accordingly. (aeabi_set_attribute_string): Turn it into a global function. * config/tc-arm.h (md_post_relax_hook): Enable it for ARM target. (aeabi_set_public_attributes): Declare it. gas/testsuite/ 2014-11-21 Terry Guo <terry.guo@arm.com> * gas/arm/attr-arch-assumption.d: New file. * gas/arm/attr-arch-assumption.s: Likewise. ld/testsuite/ 2014-11-21 Terry Guo <terry.guo@arm.com> * ld-arm/tls-longplt-lib.s: Require ARMv6T2. * ld-arm/tls-longplt.s: Likewise. * ld-arm/tls-longplt-lib.d: Updated. * ld-arm/tls-longplt.d: Likewise.
2014-11-21Support ARM Cortex-M7Terry Guo8-4/+240
include/ChangeLog: 2014-11-21 Terry Guo <terry.guo@arm.com> * opcode/arm.h (FPU_VFP_EXT_ARMV8xD): New macro. (FPU_VFP_V5D16): Likewise. (FPU_VFP_V5_SP_D16): Likewise. (FPU_ARCH_VFP_V5D16): Likewise. (FPU_ARCH_VFP_V5_SP_D16): Likewise. bfd/ChangeLog: 2014-11-21 Terry Guo <terry.guo@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Support FPv5. binutils/ChangeLog: 2014-11-21 Terry Guo <terry.guo@arm.com> * readelf.c (arm_attr_tag_FP_arch): Extended to support FPv5. gas/ChangeLog: 2014-11-21 Terry Guo <terry.guo@arm.com> * config/tc-arm.c (fpu_vfp_ext_armv8xd): New. (arm_cpus): Support cortex-m7. (arm_fpus): Support fpv5-sp-d16 and fpv5-d16. (do_vfp_nsyn_cvt_fpv8): Generate error when use D register for S register only target like FPv5-SP-D16. (do_neon_cvttb_1): Likewise. (do_vfp_nsyn_fpv8): Likewise. (do_vrint_1): Likewise. (aeabi_set_public_attributes): Set proper FP arch for FPv5. * doc/c-arm.texi: Document new cpu and fpu names for cortex-m7. gas/testsuite/ChangeLog: 2014-11-21 Terry Guo <terry.guo@arm.com> * gas/arm/armv7e-m+fpv5-d16.s: New. * gas/arm/armv7e-m+fpv5-d16.d: Likewise. * gas/arm/armv7e-m+fpv5-sp-d16.s: Likewise. * gas/arm/armv7e-m+fpv5-sp-d16.d: Likewise. ld/testsuite/ChangeLog: 2014-11-21 Terry Guo <terry.guo@arm.com> * ld-arm/attr-merge-vfp-4-sp.s: New test source file. * ld-arm/attr-merge-vfp-5-sp.s: Likewise. * ld-arm/attr-merge-vfp-5.s: Likewise. * ld-arm/attr-merge-vfp-8.d: New test. * ld-arm/attr-merge-vfp-8r.d: Likewise. * ld-arm/attr-merge-vfp-9.d: Likewise. * ld-arm/attr-merge-vfp-9r.d: Likewise. * ld-arm/attr-merge-vfp-10.d: Likewise. * ld-arm/attr-merge-vfp-10r.d: Likewise. * ld-arm/attr-merge-vfp-11.d: Likewise. * ld-arm/attr-merge-vfp-11r.d: Likewise. * ld-arm/attr-merge-vfp-12.d: Likewise. * ld-arm/attr-merge-vfp-12r.d: Likewise. * ld-arm/attr-merge-vfp-13.d: Likewise. * ld-arm/attr-merge-vfp-13r.d: Likewise. * ld-arm/attr-merge-vfp-14.d: Likewise. * ld-arm/attr-merge-vfp-14r.d: Likewise. * ld-arm/arm-elf.exp: Run the new tests.
2014-11-20* config/tc-arm.c (rotate_left): Avoid undefined behaviour when N = 0.Richard Earnshaw2-1/+6
2014-11-20[AArch64] Fix mis-detection of unpredictable load/store operations with FP regs.Richard Earnshaw3-11/+25
* config/tc-aarch64.c (warn_unpredictable_ldst): Check that transfer registers are in the GP register set. Adjust warnings. Use correct field member for address register. * testsuite/gas/aarch64/diagnostic.l: Update.
2014-11-19[AArch64] Warn on load pair to same registerJiong Wang5-0/+68
2014-11-19 Ryan Mansfield <rmansfield@qnx.com> * config/tc-aarch64.c (md_assemble): Call warn_unpredictable_ldst. (warn_unpredictable_ldst): New. 2014-11-19 Ryan Mansfield <rmansfield@qnx.com> * gas/aarch64/diagnostic.s: Add new warnings test patterns. * gas/aarch64/diagnostic.l: Update expected diagnostic output.
2014-11-18Add -z bndplt to generate BND prefix in PLT entriesIgor Zamyatin6-64/+58
This patch adds "-z bndplt" option Linux/x86-64 linker to generate BND prefix in PLT entries. It also updated Linux/x86-64 assembler not to generate R_X86_64_PLT32_BND nor R_X86_64_PC32_BND relocations. bfd/ 2014-11-18 Igor Zamyatin <igor.zamyatin@intel.com> * elf64-x86-64.c (elf_x86_64_check_relocs): Enable MPX PLT only for -z bndplt. gas/ 2014-11-18 Igor Zamyatin <igor.zamyatin@intel.com> * config/tc-i386-intel.c (i386_operator): Remove last argument from lex_got call. * config/tc-i386.c (reloc): Remove bnd_prefix from parameters' list. Return always BFD_RELOC_32_PCREL. * (output_branch): Remove condition for BFD_RELOC_X86_64_PC32_BND. * (output_jump): Update call to reloc accordingly. * (output_interseg_jump): Likewise. * (output_disp): Likewise. * (output_imm): Likewise. * (x86_cons_fix_new): Likewise. * (lex_got): Remove bnd_prefix from parameters' list in macro and declarations. Don't use BFD_RELOC_X86_64_PLT32_BND. * (x86_cons): Update call to lex_got accordingly. * (i386_immediate): Likewise. * (i386_displacement): Likewise. * (md_apply_fix): Don't use BFD_RELOC_X86_64_PLT32_BND nor BFD_RELOC_X86_64_PC32_BND. * (tc_gen_reloc): Likewise. include/ 2014-11-18 Igor Zamyatin <igor.zamyatin@intel.com> * bfdlink.h (struct bfd_link_info): Add bndplt. ld/ 2014-11-18 Igor Zamyatin <igor.zamyatin@intel.com> * emulparams/elf_x86_64.sh (BNDPLT): Set to yes for x86_64. * emultempl/elf32.em (gld${EMULATION_NAME}_handle_option): Handle "-z bndplt" if BNDPLT is yes. (gld${EMULATION_NAME}_list_options): Add "-z bndplt" entry. * ld.texinfo: Add description for bndplt. ld/testsuite/ 2014-11-18 Igor Zamyatin <igor.zamyatin@intel.com> * testsuite/ld-x86-64/bnd-ifunc-1.d: Add bndplt option. * testsuite/ld-x86-64/bnd-ifunc-2.d: Likewise. * testsuite/ld-x86-64/bnd-plt-1.d: Likewise. Update dissassembly sections. * testsuite/ld-x86-64/mpx.exp: Handle mpx3 and mpx4 tests. * testsuite/ld-x86-64/mpx1a.rd: Remove _BND from relocation name. * testsuite/ld-x86-64/mpx1c.rd: Likewise. * testsuite/ld-x86-64/mpx2a.rd: Likewise. * testsuite/ld-x86-64/mpx2c.rd: Likewise. * testsuite/ld-x86-64/mpx3.dd: New file. * testsuite/ld-x86-64/mpx3a.s: Likewise. * testsuite/ld-x86-64/mpx3b.s: Likewise. * testsuite/ld-x86-64/mpx4.dd: Likewise. * testsuite/ld-x86-64/mpx4a.s: Likewise. * testsuite/ld-x86-64/mpx4b.s: Likewise.
2014-11-18aarch64: allow adding/removing just feature flags via .arch_extensionJan Beulich7-12/+111
Rather than requiring to always also set/change the base architecture, allow just en-/disabling of architecture extensions, matching what ARM has.
2014-11-18[AArch64] Add xgene2.Philipp Tomsich3-1/+9
2014-11-18[AArch64] Add xgene1.Philipp Tomsich3-1/+10
The name xgene1 superceeds xgene-1. We retain support for the original xgene-1 for compatibility but drop it from documentation.
2014-11-17Add AVX512VBMI instructionsIlya Tocar17-1/+1585
gas/ * config/tc-i386.c (cpu_arch): Add .avx512vbmi. * doc/c-i386.texi: Document it. opcodes/ * i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb, vpmultishiftqb. * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2. * i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS. (cpu_flags): Add CpuAVX512VBMI. * i386-opc.h (enum): Add CpuAVX512VBMI. (i386_cpu_flags): Add cpuavx512vbmi. * i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b, vpermt2b. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. /gas/testsuite/ * gas/i386/i386.exp: Run new tests. * gas/i386/avx512vbmi-intel.d: New file. * gas/i386/avx512vbmi.d: Likewise. * gas/i386/avx512vbmi.s: Likewise. * gas/i386/avx512vbmi_vl-intel.d: Likewise. * gas/i386/avx512vbmi_vl.d: Likewise. * gas/i386/avx512vbmi_vl.s: Likewise. * gas/i386/x86-64-avx512vbmi-intel.d: Likewise. * gas/i386/x86-64-avx512vbmi.d: Likewise. * gas/i386/x86-64-avx512vbmi.s: Likewise. * gas/i386/x86-64-avx512vbmi_vl-intel.d: Likewise. * gas/i386/x86-64-avx512vbmi_vl.d: Likewise. * gas/i386/x86-64-avx512vbmi_vl.s: Likewise.
2014-11-17Add AVX512IFMA instructionsIlya Tocar17-1/+1141
gas/ * config/tc-i386.c (cpu_arch): Add .avx512ifma. * doc/c-i386.texi: Document it. opcodes/ * i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq. * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4, PREFIX_EVEX_0F38B5. * i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS. (cpu_flags): Add CpuAVX512IFMA. * i386-opc.h (enum): Add CpuAVX512IFMA. (i386_cpu_flags): Add cpuavx512ifma. * i386-opc.tbl: Add vpmadd52huq, vpmadd52luq. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. /gas/testsuite/ * gas/i386/i386.exp: Run new tests. * gas/i386/avx512ifma-intel.d: New file. * gas/i386/avx512ifma.d: Likewise. * gas/i386/avx512ifma.s: Likewise. * gas/i386/avx512ifma_vl-intel.d: Likewise. * gas/i386/avx512ifma_vl.d: Likewise. * gas/i386/avx512ifma_vl.s: Likewise. * gas/i386/x86-64-avx512ifma-intel.d: Likewise. * gas/i386/x86-64-avx512ifma.d: Likewise. * gas/i386/x86-64-avx512ifma.s: Likewise. * gas/i386/x86-64-avx512ifma_vl-intel.d: Likewise. * gas/i386/x86-64-avx512ifma_vl.d: Likewise. * gas/i386/x86-64-avx512ifma_vl.s: Likewise.
2014-11-17Add pcommit instructionIlya Tocar11-2/+99
gas/ * config/tc-i386.c (cpu_arch): Add .pcommit. * doc/c-i386.texi: Document it. /opcodes * i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7. (prefix_table): Add pcommit. * i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS. (cpu_flags): Add CpuPCOMMIT. * i386-opc.h (enum): Add CpuPCOMMIT. (i386_cpu_flags): Add cpupcommit. * i386-opc.tbl: Add pcommit. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. /gas/testsuite/ * gas/i386/i386.exp: Run new tests. * gas/i386/pcommit-intel.d: New file. * gas/i386/pcommit.d: Likewise. * gas/i386/pcommit.s: Likewise. * gas/i386/x86-64-pcommit-intel.d: Likewise. * gas/i386/x86-64-pcommit.d: Likewise. * gas/i386/x86-64-pcommit.s: Likewise.
2014-11-17Add clwb instructionIlya Tocar11-0/+111
gas/ * config/tc-i386.c (cpu_arch): Add .clwb. * doc/c-i386.texi: Document it. opcodes/ * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6. (prefix_table): Add clwb. * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS. (cpu_flags): Add CpuCLWB. * i386-opc.h (enum): Add CpuCLWB. (i386_cpu_flags): Add cpuclwb. * i386-opc.tbl: Add clwb. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. gas/testsuite/ * gas/i386/i386.exp: Run new tests. * gas/i386/clwb-intel.d: New file. * gas/i386/clwb.d: Likewise. * gas/i386/clwb.s: Likewise. * gas/i386/x86-64-clwb-intel.d: Likewise. * gas/i386/x86-64-clwb.d: Likewise. * gas/i386/x86-64-clwb.s: Likewise.
2014-11-14Correct x86 assembler manualH.J. Lu3-23/+30
* config/tc-i386.c (cpu_arch): Re-arrange avx512* and xsave* items. * doc/c-i386.texi: Re-arrange avx512* and xsave*. Add clflushopt and se1. Remove duplicated entries.
2014-11-14[AArch64] Enable CRC feature in GAS for cortex-a53 and cortex-a57.Marcus Shawcroft2-3/+10
2014-11-13Add assembler support for @gotpltH.J. Lu6-0/+44
Obsolete R_X86_64_GOTPLT64 and treat it the same as R_X86_64_GOT64. bfd/ PR gas/17598 * elf64-x86-64.c (elf_x86_64_check_relocs): Treat R_X86_64_GOTPLT64 the same as R_X86_64_GOT64. (elf_x86_64_relocate_section): Likewise. gas/ PR gas/17598 * config/tc-i386.c (reloc): Support BFD_RELOC_X86_64_GOTPLT64. gas/testsuite/ PR gas/17598 * gas/i386/reloc64.s: Add @gotplt check. * gas/i386/reloc64.d: Updated. * gas/i386/reloc64.l: Likewise. ld/testsuite/ PR gas/17598 * ld-x86-64/x86-64.exp: Run gotplt1. * ld-x86-64/gotplt1.d: New file. * ld-x86-64/gotplt1.s: Likewise.
2014-11-13More fixes for memory access violations whilst scanning corrupt binaries.Nick Clifton2-0/+7
PR binutils/17512 * config/obj-coff.c (coff_obj_symbol_new_hook): Set the is_sym field. * coffcode.h (coff_ptr_struct): Add is_sym field. (coff_new_section_hook): Set the is_sym field. (coff_pointerize_aux_hook): Check the is_sym field. (coff_print_aux): Likewise. (coff_compute_section_file_positions): Likewise. (coff_write_object_contents): Likewise. (coff_slurp_line_table): Likewise. (coff_slurp_symbol_table): Likewise. (CALC_ADDEND): Likewise. * coffgen.c (coff_renumber_symbols): Likewise. (coff_mangle_symbols): Likewise. (coff_fix_symbol_name): Likewise. (coff_write_symbol): Likewise. (coff_write_alien_symbol): Likewise. (coff_write_native_symbol): Likewise. (coff_write_symbols): Likewise. (coff_write_linenumbers): Likewise. (coff_pointerize_aux): Likewise. (coff_get_normalized_symtab): Likewise. (coff_get_symbol_info): Likewise. (bfd_coff_get_syment): Likewise. (bfd_coff_get_auxent): Likewise. (coff_print_symbol): Likewise. (coff_find_nearest_line_with_names): Likewise. (bfd_coff_set_symbol_class): Likewise. (coff_make_empty_symbol): Set the is_sym field. (coff_bfd_make_debug_symbol): Likewise. * peicode.h (pe_ILF_make_a_symbol): Likewise. * libcoff.h: Regenerate. * libcoff-in.h: Regenerate.
2014-11-13[AArch64] Remove example processors from GAS.Marcus Shawcroft2-5/+4
2014-11-12Fix z80-coff build breakageAlan Modra2-0/+8
* config/tc-z80.c (parse_exp_not_indexed, parse_exp): Warning fixes.
2014-11-12Fix x86 non-ELF build breakageAlan Modra2-0/+8
PR ld/17482 * config/tc-i386.c (output_insn): Don't test x86_elf_abi when not ELF.
2014-11-11Updated French and Ukranian translations supplied by the Translation Project.Nick Clifton2-109/+144
* po/uk.po: Updated Ukranian translation. * po/fr.po: Updated French translation.
2014-11-07Fix a typo in gas/ChangeLogH.J. Lu1-1/+2
2014-11-07X32: Add REX prefix to encode R_X86_64_GOTTPOFFH.J. Lu5-0/+47
Structions with R_X86_64_GOTTPOFF relocation must be encoded with REX prefix even if it isn't required by destination register. Otherwise linker can't safely perform IE -> LE optimization. bfd/ PR ld/17482 * elf64-x86-64.c (elf_x86_64_relocate_section): Update comments for IE->LE transition. gas/ PR ld/17482 * config/tc-i386.c (output_insn): Add a dummy REX_OPCODE prefix for structions with R_X86_64_GOTTPOFF relocation for x32 if needed. gas/testsuite/ PR ld/17482 * gas/i386/ilp32/x32-tls.d: New file. * gas/i386/ilp32/x32-tls.s: Likewise. ld/testsuite/ PR ld/17482 * ld-x86-64/tlsie4.dd: Updated.
2014-11-06Add mach parameter to nios2_find_opcode_hash.Sandra Loosemore2-1/+6
2014-11-06 Sandra Loosemore <sandra@codesourcery.com> include/opcode/ * nios2.h (nios2_find_opcode_hash): Add mach parameter to declaration. Fix obsolete comment. opcodes/ * nios2-dis.c (nios2_find_opcode_hash): Add mach parameter. (nios2_disassemble): Adjust call to nios2_find_opcode_hash. gas/ * config/tc-nios2.c (nios2_diagnose_overflow): Adjust call to nios2_find_opcode_hash.
2014-11-05Update .MIPS.abiflags to support MIPS R6Matthew Fortune6-0/+63
bfd/ * elfxx-mips.c (update_mips_abiflags_isa): Add E_MIPS_ARCH_32R6 and E_MIPS_ARCH_64R6 support. ld/testsuite/ * ld-mips-elf/abiflags-strip10-ph.d: New file. * ld-mips-elf/mips-eld.exp: Run the new test. gas/ * config/tc-mips.c (mips_elf_final_processing): Add INSN_ISA32R6 and INSN_ISA64R6 support. gas/testsuite/ * gas/mips/elf_arch_mips32r6.d: New file. * gas/mips/elf_arch_mips64r6.d: New file. * gas/mips/mips.exp: Run the new tests.
2014-11-04Don't use register keywordAlan Modra24-4044/+4308
* expr.c (expr_symbol_where): Don't use register keyword. * app.c (app_push, app_pop, do_scrub_chars): Likewise. * ecoff.c (add_string, add_ecoff_symbol, add_aux_sym_symint, add_aux_sym_rndx, add_aux_sym_tir, add_procedure, add_file, ecoff_build_lineno, ecoff_setup_ext, allocate_cluster. allocate_scope, allocate_vlinks, allocate_shash, allocate_thash, allocate_tag, allocate_forward, allocate_thead, allocate_lineno_list): Likewise. * frags.c (frag_more, frag_var, frag_variant, frag_wane): Likewise. * input-file.c (input_file_push, input_file_pop): Likewise. * input-scrub.c (input_scrub_push, input_scrub_next_buffer): Likewise. * subsegs.c (subseg_change): Likewise. * symbols.c (colon, symbol_table_insert, symbol_find_or_make) (dollar_label_name, fb_label_name): Likewise. * write.c (relax_align): Likewise. * config/tc-alpha.c (s_alpha_pdesc): Likewise. * config/tc-bfin.c (bfin_s_bss): Likewise. * config/tc-i860.c (md_estimate_size_before_relax): Likewise. * config/tc-m68hc11.c (md_convert_frag): Likewise. * config/tc-m68k.c (m68k_ip, crack_operand): Likewise. (md_convert_frag_1, s_even): Likewise. * config/tc-mips.c (mips_clear_insn_labels): Likewise. * config/tc-mn10200.c (md_begin): Likewise. * config/tc-s390.c (s390_setup_opcodes, md_begin): Likewise. * config/tc-sh.c (sh_elf_cons): Likewise. * config/tc-tic4x.c (tic4x_cons, tic4x_stringer): Likewise. * config/m68k-parse.y (m68k_reg_parse): Likewise. Convert from K&R. (yylex, m68k_ip_op, yyerror): Convert from K&R.
2014-11-04Use frag_now_fix_octets in gas d10v, d30vAlan Modra3-7/+9
obstack_next_free is supposed to return a void* rather than the char* it does currently, so expressions involving pointer arithmetic need a cast. Avoid the issue. * config/tc-d10v.c (find_opcode): Call frag_now_fix_octets rather than equivalent obstack_next_free expression. * config/tc-d30v.c (find_format): Likewise.
2014-11-03Fixes a snafu checking the size of 20-bit immedaite values.Nick Clifton2-1/+6
* config/tc-msp430.c (msp430_srcoperand): Fix range test for 20-bit values.
2014-10-31MIPS: Add Octeon 3 supportNaveen H.S7-1/+66
binutils: 2014-10-31 Andrew Pinski <apinski@cavium.com> Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com> * readelf.c (print_mips_isa_ext): Print the value of Octeon3. gas: 2014-10-31 Andrew Pinski <apinski@cavium.com> Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com> * config/tc-mips.c (CPU_IS_OCTEON): Handle CPU_OCTEON3. (mips_cpu_info_table): Octeon3 enables virt ase. * doc/c-mips.texi: Document octeon3 as an acceptable value for -march=. gas/testsuite: 2014-10-31 Andrew Pinski <apinski@cavium.com> Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com> * gas/mips/mips.exp: Add support for Octeon3 architecture. Also add in support for running Octeon3 tests. * gas/mips/octeon3.d: New test. * gas/mips/octeon3.s: New test source. opcodes: 2014-10-31 Andrew Pinski <apinski@cavium.com> Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com> * mips-dis.c (mips_arch_choices): Add octeon3. * mips-opc.c (IOCT): Include INSN_OCTEON3. (IOCT2): Likewise. (IOCT3): New define. (IVIRT): New define. (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0, tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti IVIRT instructions. Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another operand for IOCT3. bfd: 2014-10-31 Andrew Pinski <apinski@cavium.com> Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com> * archures.c: Add octeon3 for mips target. * bfd-in2.h: Regenerate. * bfd/cpu-mips.c: Define I_mipsocteon3. nfo_struct): Add octeon3 support. * bfd/elfxx-mips.c: (_bfd_elf_mips_mach): Add support for octeon3. (mips_set_isa_flags): Add support for octeon3. (bfd_mips_isa_ext): Add bfd_mach_mips_octeon3. (mips_mach_extensions): Make bfd_mach_mips_octeon3 an extension of bfd_mach_mips_octeon2. (print_mips_isa_ext): Print the value of Octeon3.
2014-10-31Add forgotten changelog entry.Andrew Pinski1-0/+7
2014-10-21 Andrew Pinski <apinski@cavium.com> * config/tc-aarch64.c (aarch64_cpus): Add thunderx. * doc/c-aarch64.texi: Document that thunderx is a valid processor name.
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