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2006-06-12gas/testsuite/H.J. Lu6-0/+69
2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run nops and x86-64-nops. * gas/i386/nops.d: New file. * gas/i386/nops.s: Likewise. * gas/i386/x86-64-nops.d: Likewise. * gas/i386/x86-64-nops.s: Likewise. include/opcode/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Add "nop" with memory reference. opcodes/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f. (twobyte_has_modrm): Set 1 for 0x1f.
2006-06-12gas/H.J. Lu7-4/+40
2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_suffix): Don't add rex64 for "xchg %rax,%rax". gas/testsuite/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/opcode.s: Add "xchg %ax,%ax". * gas/i386/opcode.d: Updated. * gas/i386/x86-64-opcode.s: Add xchg %ax,%ax, xchg %eax,%eax, xchg %rax,%rax, rex64 xchg %rax,%rax and xchg %rax,%r8. * gas/i386/x86-64-opcode.d: Updated. include/opcode/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Update comment for 64bit NOP. opcodes/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (NOP_Fixup): Removed. (NOP_Fixup1): New. (NOP_Fixup2): Likewise. (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
2006-06-09Lost bit belonging to the last commit.Thiemo Seufer1-0/+1
2006-06-09 [ gas/ChangeLog ]Thiemo Seufer5-0/+46
* config/tc-mips.c (mips_ip): Maintain argument count. [ gas/testsuite/ChangeLog ] * gas/mips/mips32-sf32.s, gas/mips/mips32-sf32.d: New test for odd single precision FPRs on MIPS32. * gas/mips/mips.exp: Run them.
2006-06-09 * config/tc-iq2000.c: Include sb.h.Alan Modra2-0/+5
2006-06-08 * gas/mips/mips32.s: Added cop2 branches with explicit conditionThiemo Seufer3-0/+25
code register numbers. * gas/mips/mips32.d: Likewise.
2006-06-08 * config/tc-mips.c (mips_pseudo_table): Add "origin" and "repeat"Thiemo Seufer2-0/+7
aliases for better compatibility with SGI tools.
2006-06-08 * configure.in (BFDLIB, BFDVER_H, ALL_OBJ_DEPS): Delete.Alan Modra7-1871/+1761
* Makefile.am (GASLIBS): Expand @BFDLIB@. (BFDVER_H): Delete. (OBJS): Expand @ALL_OBJ_DEPS@. Depend on all fopen-*.h variants. (obj-aout.o): Depend on $(DEP_@target_get_type@_aout) (obj-coff.o, obj-ecoff.o, obj-elf.o): Similarly. Run "make dep-am". * dep-in.sed: Don't substitute bfdver.h. Do remove symcat.h. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * configure: Regenerate.
2006-06-07bfd/doc:Joseph Myers2-1/+5
* bfd.texinfo: Remove local @tex code. bfd: * po/Make-in (pdf, ps): New dummy targets. binutils: * po/Make-in (pdf, ps): New dummy targets. gas: * po/Make-in (pdf, ps): New dummy targets. gprof: * po/Make-in (pdf, ps): New dummy targets. ld: * po/Make-in (pdf, ps): New dummy targets. opcodes: * po/Make-in (pdf, ps): New dummy targets.
2006-06-07 * config/tc-arm.c (stdarg.h): include.Julian Brown2-503/+1557
(arm_it): Add uncond_value field. Add isvec and issingle to operand array. (arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and REG_TYPE_NSDQ (single, double or quad vector reg). (reg_expected_msgs): Update. (BAD_FPU): Add macro for unsupported FPU instruction error. (parse_neon_type): Support 'd' as an alias for .f64. (parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ sets of registers. (parse_vfp_reg_list): Don't update first arg on error. (parse_neon_mov): Support extra syntax for VFP moves. (operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO, OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ. (parse_operands): Support isvec, issingle operands fields, new parse codes above. (do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs, msr variants. (do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above. (NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez. (NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros. (NEON_SHAPE_DEF): New macro. Define table of possible instruction shapes. (neon_shape): Redefine in terms of above. (neon_shape_class): New enumeration, table of shape classes. (neon_shape_el): New enumeration. One element of a shape. (neon_shape_el_size): Register widths of above, where appropriate. (neon_shape_info): New struct. Info for shape table. (neon_shape_tab): New array. (neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL. (neon_check_shape): Rewrite as... (neon_select_shape): New function to classify instruction shapes, driven by new table neon_shape_tab array. (neon_quad): New function. Return 1 if shape should set Q flag in instructions (or equivalent), 0 otherwise. (type_chk_of_el_type): Support F64. (el_type_of_type_chk): Likewise. (neon_check_type): Add support for VFP type checking (VFP data elements fill their containing registers). (do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE in thumb mode for VFP instructions. (do_vfp_nsyn_opcode): New function. Look up the opcode in argument, and encode the current instruction as if it were that opcode. (try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS arguments, call function in PFN. (do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul) (do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str) (do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul) (do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push) (do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions. Redirect Neon-syntax VFP instructions to VFP instruction handlers. (do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm) (do_neon_qshl_imm, do_neon_logic, do_neon_bitfield) (neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh) (do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri) (do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext) (do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn) (do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long) (do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt) (do_neon_swp): Use neon_select_shape not neon_check_shape. Use neon_quad. (vfp_or_neon_is_neon): New function. Call if a mnemonic shared between VFP and Neon turns out to belong to Neon. Perform architecture check and fill in condition field if appropriate. (do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg) (do_neon_cvt): Add support for VFP variants of instructions. (neon_cvt_flavour): Extend to cover VFP conversions. (do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP vmov variants. (do_neon_ldr_str): Handle single-precision VFP load/store. (do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use NS_NULL not NS_IGNORE. (opcode_tag): Add OT_csuffixF for operands which either take a conditional suffix, or have 0xF in the condition field. (md_assemble): Add support for OT_csuffixF. (NCE): Replace macro with... (NCE_tag, NCE, NCEF): New macros. (nCE): Replace macro with... (nCE_tag, nCE, nCEF): New macros. (insns): Add support for VFP insns or VFP versions of insns msr, mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop, vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia, vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared VFP/Neon insns together.
2006-06-07 * gas/arm/itblock.s: New file. Helper macro for making all-true ITJulian Brown13-0/+758
blocks. * gas/arm/neon-cond-bad-inc.s: New test. Make sure unconditional Neon instructions are rejected... * gas/arm/neon-cond-bad.s: In ARM mode, and... * gas/arm/neon-cond-bad_t2.s: Accepted in Thumb mode (with IT). * gas/arm/neon-cond-bad.l: Expected error output in ARM mode. * gas/arm/neon-cond-bad.d: Control ARM mode test. * gas/arm/neon-cond-bad_t2.d: Expected output in Thumb mode. * gas/arm/vfp-neon-syntax-inc.s: Test VFP Neon-style syntax. * gas/arm/vfp-neon-syntax.s: ...in ARM mode. * gas/arm/vfp-neon-syntax_t2.s: ...and Thumb mode. * gas/arm/vfp-neon-syntax.d: Expected output in ARM mode. * gas/arm/vfp-neon-syntax_t2.d: Expected output in Thumb mode.
2006-06-072006-06-06 Paul Brook <paul@codesourcery.com>Paul Brook5-224/+229
opcodes/ * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm instructions. (neon_opcodes): Add conditional execution specifiers. (thumb_opcodes): Ditto. (thumb32_opcodes): Ditto. (arm_conditional): Change 0xe to "al" and add "" to end. (ifthen_state, ifthen_next_state, ifthen_address): New. (IFTHEN_COND): Define. (print_insn_coprocessor, print_insn_neon): Print thumb conditions. (print_insn_arm): Change %c to use new values of arm_conditional. (print_insn_thumb16): Print thumb conditions. Add %I. (print_insn_thumb32): Print thumb conditions. (find_ifthen_state): New function. (print_insn): Track IT block state. gas/testsuite/ * gas/arm/thumb2_bcond.d: Update expected output. * gas/arm/thumb32.d: Ditto. * gas/arm/vfp1_t2.d: Ditto. * gas/arm/vfp1xD_t2.d: Ditto. binutils/testsuite/ * binutils-all/arm/objdump.exp: New file. * binutils-all/arm/thumb2-cond.s: New test.
2006-06-07remove some duplicate #include's.Alan Modra70-253/+143
2006-06-07include/opcode/Alan Modra3-3/+24
* ppc.h (PPC_OPCODE_POWER6): Define. Adjust whitespace. gas/ * config/tc-ppc.c (parse_cpu): Handle "-mpower6". (md_show_usage): Document it. (ppc_setup_opcodes): Test power6 opcode flag bits. * doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6". opcodes/ * ppc-dis.c (powerpc_dialect): Handle power6 option. (print_ppc_disassembler_options): Mention power6.
2006-06-06 [ gas/ChangeLog ]Thiemo Seufer6-24/+376
* config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro. (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete. (macro_build): Update comment. (mips_ip): Allow DSP64 instructions for MIPS64R2. (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and CPU_HAS_MDMX. (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and MIPS_CPU_ASE_MDMX flags for sb1. [ gas/testsuite/ChangeLog ] * gas/mips/mips64-dsp.s, gas/mips/mips64-dsp.d: New DSP64 tests. * gas/mips/mips.exp: Run DSP64 tests. [ opcodes/ChangeLog ] * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2. * mips-opc.c: Add DSP64 instructions.
2006-06-05 [ gas/ChangeLog ]Thiemo Seufer9-1000/+249
* config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew appropriate. (mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate. (mips_ip): Make overflowed/underflowed constant arguments in DSP and MT instructions a fatal error. Use INSERT_OPERAND where appropriate. Improve warnings for break and wait code overflows. Use symbolic constant of OP_MASK_COPZ. (mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate. [ gas/testsuite/ChangeLog ] * gas/mips/mips32-dsp.d, gas/mips/mips32-dsp.s, gas/mips/mips32-mt.d, gas/mips/mips32-mt.s: Remove instructions with invalid arguments. * gas/mips/mips32-dsp.l, gas/mips/mips32-mt.l: Delete file. [ include/opcode/ChangeLog ] * mips.h: Improve description of MT flags.
2006-06-05bfd/, binutils/, gas/, gprof/, ld/, opcodes/Daniel Jacobowitz2-0/+5
* po/Make-in (top_builddir): Define.
2006-06-02binutils:Joseph Myers4-6/+10
* doc/Makefile.am (TEXI2DVI): Define. * doc/Makefile.in: Regenerate. gas: * doc/Makefile.am (TEXI2DVI): Define. * doc/Makefile.in: Regenerate. * doc/c-arc.texi: Fix typo. ld: * Makefile.am (TEXI2DVI): Add -I $(top_srcdir)/../libiberty. * Makefile.in: Regenerate.
2006-06-01 * doc/c-avr.texi: New file.Denis Chertykov4-0/+368
* doc/Makefile.am (CPU_DOCS): Add c-avr.texi * doc/all.texi: Set AVR * doc/as.texinfo: Include c-avr.texi
2006-06-01 * config/obj-ieee.c: Delete.Alan Modra10-784/+37
* config/obj-ieee.h: Delete. * Makefile.am (OBJ_FORMATS): Remove ieee. (OBJ_FORMAT_CFILES, OBJ_FORMAT_HFILES): Similarly. (obj-ieee.o): Remove rule. * Makefile.in: Regenerate. * configure.in (atof): Remove tahoe. (OBJ_MAYBE_IEEE): Don't define. * configure: Regenerate. * config.in: Regenerate. * doc/Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.
2006-05-31Configury changes: update src repository (binutils, gdb, and rda) to useDaniel Jacobowitz7-2708/+534
config/gettext-sister.m4 instead of the old gettext.m4. Regenerate all affected autotools files. Include intl in gdb releases again.
2006-05-30Update Spanish translationNick Clifton2-3949/+4290
2006-05-29 * doc/c-avr.texi: New file.Denis Chertykov1-0/+7
* doc/Makefile.am (CPU_DOCS): Add c-avr.texi * doc/all.texi: Set AVR * doc/as.texinfo: Include c-avr.texi
2006-05-28 * config/bfin-parse.y (check_macfunc): Loose the condition ofJie Zhang2-2/+8
calling check_multiply_halfregs ().
2006-05-26Remove ">>>>>>> 1.2917".H.J. Lu1-1/+0
2006-05-25include/opcodes/Richard Sandiford3-0/+21
* m68k.h (mcf_mask): Define. opcodes/ * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd and fmovem entries. Put register list entries before immediate mask entries. Use "l" rather than "L" in the fmovem entries. * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it out from INFO. (m68k_scan_mask): New function, split out from... (print_insn_m68k): ...here. If no architecture has been set, first try printing an m680x0 instruction, then try a Coldfire one. gas/testsuite/ * gas/m68k/mcf-fpu.s: Add fmovemd and fmovem instructions. * gas/m68k/mcf-fpu.d: Adjust accordingly.
2006-05-25 * gas/bfin/vector2.s, gas/bfin/vector2.d: Test to ensure (m) is notJie Zhang3-0/+13
thrown away.
2006-05-25 * config/bfin-parse.y (asm_1): Better check and deal withJie Zhang2-38/+44
vector and scalar Multiply 16-Bit Operands instructions.
2006-05-24Add TLS support for hppa-linuxNick Clifton3-2549/+2532
2006-05-24Add support for AVR6 familyNick Clifton4-104/+145
2006-05-23 [ gas/ChangeLog ]Thiemo Seufer11-94/+321
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename. (ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS, ISA_HAS_MXHC1): New macros. (HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments. (mips_cpu_info): Change to use combined ASE/IS_ISA flag. (MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines. (mips_after_parse_args): Change default handling of float register size to account for 32bit code with 64bit FP. Better sanity checking of ISA/ASE/ABI option combinations. (s_mipsset): Support switching of GPR and FPR sizes via .set {g,f}p={32,64,default}. Better sanity checking for .set ASE options. (mips_elf_final_processing): We should record the use of 64bit FP registers in 32bit code but we don't, because ELF header flags are a scarce ressource. (mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef, 24kex, 34kc, 34kf, 34kx, 25kf CPU definitions. (mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA. * doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document missing -march options. Document .set arch=CPU. Move .set smartmips to ASE page. Use @code for .set FOO examples. [ gas/testsuite/Changelog ] * gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d, gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l, gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler output. * gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files, catch assembler warnings.
2006-05-23 * config/tc-bfin.c (bfin_start_line_hook): Bump line countersJie Zhang2-1/+17
if needed.
2006-05-23Commit the missing bits of my last patch.Jie Zhang1-3/+3
2006-05-23 * config/bfin-defs.h (bfin_equals): Remove declaration.Jie Zhang4-47/+9
* config/bfin-parse.y (asm_1): Remove "expr ASSIGN expr". * config/tc-bfin.c (bfin_name_is_register): Remove. (bfin_equals): Remove. * config/tc-bfin.h (TC_EQUAL_IN_INSN): Redefine as 1. (bfin_name_is_register): Remove declaration.
2006-05-22* gas/mips/mips32-dsp.l: Fix expected unsigned decoding of -1 in warning ↵Nick Clifton3-145/+151
messages. * gas/mips/mips32-mt.l: Likewise.
2006-05-22Remove ChangeLog entries, since the template files were already up to date.Nick Clifton1-4/+0
2006-05-22Update translation templatesNick Clifton1-0/+4
2006-05-19 * gas/mips/vxworks1-el.d, gas/mips/vxworks1-xgot-el.d: Add littleThiemo Seufer6-2/+187
endian testcases. * gas/mips/vxworks1.d, gas/mips/vxworks1-xgot.d: Build as big endian. * gas/mips/mips.exp: Run new testcases.
2006-05-19 * config/tc-mipc.c (ISA_HAS_ODD_SINGLE_FPR): New define.Thiemo Seufer2-12/+54
(mips_oddfpreg_ok): New function. (mips_ip): Use it. -------------------------------------------------------------------
2006-05-19 * config/tc-mips.h (tc_mips_regname_to_dw2regnum): Declare.Thiemo Seufer3-372/+432
* config/tc-mipc.c (ABI_NEEDS_64BIT_REGS, ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Reformat. (regname, RTYPE_MASK, RTYPE_NUM, RTYPE_FPU, RTYPE_FCC, RTYPE_VEC, RTYPE_GP, RTYPE_CP0, RTYPE_PC, RTYPE_ACC, RTYPE_CCC, RNUM_MASK, RWARN, GENERIC_REGISTER_NUMBERS, FPU_REGISTER_NAMES, FPU_CONDITION_CODE_NAMES, COPROC_CONDITION_CODE_NAMES, N32N64_SYMBOLIC_REGISTER_NAMES, O32_SYMBOLIC_REGISTER_NAMES, SYMBOLIC_REGISTER_NAMES, MIPS16_SPECIAL_REGISTER_NAMES, MDMX_VECTOR_REGISTER_NAMES, MIPS_DSP_ACCUMULATOR_NAMES, reg_names, reg_names_o32, reg_names_n32n64): Define register classes. (reg_lookup): New function, use register classes. (md_begin): Reserve register names in the symbol table. Simplify OBJ_ELF defines. (mips_ip): Fix comment formatting. Handle symbolic COP0 registers. Use reg_lookup. (mips16_ip): Use reg_lookup. (tc_get_register): Likewise. (tc_mips_regname_to_dw2regnum): New function. -------------------------------------------------------------------
2006-05-19 * config/tc-arm.c, config/tc-arm.h (tc_arm_regname_to_dw2regnum):Thiemo Seufer15-15/+32
Un-constify string argument. * config/tc-i386.c, config/tc-i386.h (tc_x86_regname_to_dw2regnum): Likewise. * config/tc-m68k.c, config/tc-m68k.h (tc_m68k_regname_to_dw2regnum): Likewise. * config/tc-ppc.c, config/tc-ppc.h (tc_ppc_regname_to_dw2regnum): Likewise. * config/tc-s390.c, config/tc-s390.h (tc_s390_regname_to_dw2regnum): Likewise. * config/tc-sh.c, config/tc-sh.h (sh_regname_to_dw2regnum): Likewise. * config/tc-sparc.c, config/tc-sparc.h (sparc_regname_to_dw2regnum): Likewise. -------------------------------------------------------------------
2006-05-19 * gas/config/tc-m68k.c (m68k_init_arch): Move checking ofNathan Sidwell2-9/+14
cfloat/m68881 to correct architecture before using it.
2006-05-16* config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate constant values.Nick Clifton2-10/+16
2006-05-152006-05-15 Paul Brook <paul@codesourcery.com>Paul Brook2-1/+7
bfd/ * cpu-arm.c (bfd_is_arm_mapping_symbol_name): Rename ... (bfd_is_arm_special_symbol_name): ... to this. Add type argument. Check symbol name is of specified type. * elf32-arm.c (elf32_arm_is_target_special_symbol, arm_elf_find_function, elf32_arm_output_symbol_hook): Use bfd_is_arm_special_symbol_name. * bfd-in.h (BFD_ARM_SPECIAL_SYM_TYPE_MAP, BFD_ARM_SPECIAL_SYM_TYPE_TAG, BFD_ARM_SPECIAL_SYM_TYPE_OTHER, BFD_ARM_SPECIAL_SYM_TYPE_ANY): Define. (bfd_is_arm_mapping_symbol_name): Remove prototype. (bfd_is_arm_special_symbol_name): Add prototype. * bfd-in2.h: Regenerate. gas/ * config/tc-arm.c (arm_adjust_symtab): Use bfd_is_arm_special_symbol_name. ld/testsuite/ * ld-arm/arm-be8.d: New test. * ld-arm/arm-be8.s: New test. * ld-arm/arm-elf.exp: Add arm-be8.
2006-05-15bfd:Bob Wilson2-8/+15
* elf32-xtensa.c (check_loop_aligned): Fix reversed check for undefined opcode. Clean up assertions. (narrow_instruction, widen_instruction): Remove "do_it" parameters. Factor most of the code into separate functions.... (can_narrow_instruction, can_widen_instruction): New. (prev_instr_is_a_loop): New. (compute_ebb_proposed_actions): Combine error handling code for decode errors. Replace call to insn_decode_len with inline code. Use can_narrow_instruction and can_widen_instruction. Handle errors from call to xtensa_opcode_is_loop. (relax_section): Adjust calls to narrow_instruction and widen_instruction. gas: * config/tc-xtensa.c (is_direct_call_opcode, is_branch_jmp_to_next, xg_assemble_vliw_tokens, xtensa_mark_narrow_branches, xtensa_fix_short_loop_frags, is_local_forward_loop, relax_frag_immed): Handle errors from calls to xtensa_opcode_is_* functions.
2006-05-14 [ gas/ChangeLog ]Thiemo Seufer9-1/+190
* config/tc-mips.c (macro_build): Test for currently active mips16 option. (mips16_ip): Reject invalid opcodes. [ opcodes/ChangeLog ] * mips16-opc.c (I1, I32, I64): New shortcut defines. (mips16_opcodes): Change membership of instructions to their lowest baseline ISA. [ gas/testsuite/ChangeLog ] * gas/mips/mips.exp: Run new tests. * gas/mips/mips16e.s, gas/mips/mips16e.d, gas/mips/mips16e-64.s, gas/mips/mips16e-64.d, gas/mips/mips16e-64.l: New tests.
2006-05-11bfd/doc/Carlos O'Donell2-6/+11
2006-05-11 Carlos O'Donell <carlos@codesourcery.com> * bfd.texinfo: Rename "Index" to "BFD Index" gas/ 2006-05-11 Carlos O'Donell <carlos@codesourcery.com> * doc/as.texinfo: Rename "Index" to "AS Index", and "ABORT" to "ABORT (COFF)". ld/ 2006-05-11 Carlos O'Donell <carlos@codesourcery.com> * ld.texinfo: Rename "Index" to "LD Index"
2006-05-112006-05-11 Paul Brook <paul@codesourcery.com>Paul Brook3-11/+207
bfd/ * elf32-arm.c (elf32_arm_reloc_map): Add MOVW and MOVT relocs. (elf32_arm_final_link_relocate): Handle MOVW and MOVT relocs. (elf32_arm_gc_sweep_hook, elf32_arm_check_relocs): Ditto. * reloc.c: Ditto. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * libcoff.h: Regenerate. gas/ * config/tc-arm.c (parse_half): New function. (operand_parse_code): Remove OP_Iffff. Add OP_HALF. (parse_operands): Ditto. (do_mov16): Reject invalid relocations. (do_t_mov16): Ditto. Use Thumb reloc numbers. (insns): Replace Iffff with HALF. (md_apply_fix): Add MOVW and MOVT relocs. (tc_gen_reloc): Ditto. * doc/c-arm.texi: Document relocation operators ld/testsuite/ * ld-arm/arm-elf.exp: Add arm-movwt. * ld-arm/arm-movwt.d: New test. * ld-arm/arm-movwt.s: New test. * ld-arm/arm.ld: Add .far.
2006-05-112006-05-11 Paul Brook <paul@codesourcery.com>Paul Brook5-3/+36
gas/ * config/tc-arm.c (arm_fix_adjustable): Return 0 for function symbols. gas/testsuite/ * gas/arm/local_function.d: New test. * gas/arm/local_function.s: New test.
2006-05-11 [ gas/ChangeLog ]Thiemo Seufer5-8/+13
* config/tc-mips.c (append_insn): Don't check the range of j or jal addresses. [ gas/testsuite/ChangeLog ] * gas/mips/jal-range.l: Don't check the range of j or jal addresses.
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