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2016-06-09[AARCH64][GAS] Fix two -Wstack-usage warnings.Renlin Li2-7/+10
Warning triggerd by gcc 5 with -O0 flag. error: stack usage might be unbounded [-Werror=stack-usage=] gas/ 2016-06-08 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (print_operands): Substitute size. (output_operand_error_record): Likewise.
2016-06-07PowerPC VLEAlan Modra2-18/+24
VLE is an encoding, not a particular processor architecture, so it isn't really proper to select insns based on PPC_OPCODE_VLE. For example {"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, shows two insns that have the same encoding, both available with VLE. Enabling both with VLE means we can't disassemble the second variant even if -Maltivec is given rather than -Mspe. Also, we don't check user assembly against the processor type as well as we could. Another problem is that when using the VLE encoding, insns from the main ppc opcode table are not available, except those using opcode 4 and 31. Correcting this revealed two errors in the ld testsuite, use of "nop" and "rfmci" when -mvle. This patch fixes those problems in the opcode table, and removes PPCNONE. I find a plain 0 distracts less from other values. In addition, I've implemented code to recognize some machine values from the apuinfo note present in ppc32 objects. It's not a complete disambiguation since we're lacking info to detect newer chips, but what we have should help with disassembly. include/ * elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL, PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE: Define. opcodes/ * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default cpu for "vle" to e500. * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE. (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise. (PPCNONE): Delete, substitute throughout. (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated" except for major opcode 4 and 31. (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags. bfd/ * cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry to match other 32-bit archs. * elf32-ppc.c (_bfd_elf_ppc_set_arch): New function. (ppc_elf_object_p): Call it. (ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix overlong line. (APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here. * elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch. * bfd-in.h (_bfd_elf_ppc_at_tls_transform, _bfd_elf_ppc_at_tprel_transform): Move to.. * elf-bfd.h: ..here. (_bfd_elf_ppc_set_arch): Declare. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define. (ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden by vle_opcodes, and that vle flag doesn't enable opcodes. Don't add vle_opcodes twice. (ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL. ld/ * testsuite/ld-powerpc/apuinfo1.s: Delete nop. * testsuite/ld-powerpc/apuinfo-vle2.s: New. * testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
2016-06-07[ARM] Add command line option for RAS extension.Matthew Wahab5-4/+76
This patch adds the architecture extension "+ras" to enable RAS support. It is enabled by default for -march=armv8.2-a and available but disabled by default for armv8-a and armv8.1-a. gas/ * config/tc-arm.c (arm_ext_v8_2): Rename to arm_ext_ras. (arm_ext_ras): Renamed from arm_ext_v8_2. (insns): Update for arm_ext_v8_2 renaming. (arm_extensions): Add "ras". * doc/c-arm.texi (ARM Options): Add an entry for "ras". * testsuite/gas/arm/armv8-a+ras.d: New. * testsuite/gas/arm/armv8_2-a.d: Add explicit command line options. include/ * opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding entries. (ARM_AEXT_V8_2A): Add ARM_EXT2_RAS. opcodes/ * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with ARM_EXT_RAS in relevant entries.
2016-06-05fixup another old style function definitionTrevor Saunders2-2/+5
gas/ChangeLog: 2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * itbl-parse.y (yyerror): Use modern argument declaration style.
2016-06-05sh{,64}: make arg type enumTrevor Saunders3-9/+23
The values are always members of the enum, except the two places -1 is assigned only to playcate -Wuninitialized because gcc isn't or at least didn't used to be smart enough to figure out its only used if it was set. gas/ChangeLog: 2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-sh.c (parse_reg): Change type of mode argument to sh_arg_type. (get_operand): Adjust. (insert): Change type of how to bfd_reloc_code_real_type. (insert4): Likewise. * config/tc-sh64.c (shmedia_get_operand): Adjust. (shmedia_parse_reg): Change type of mode to shmedia_arg_type.
2016-06-05nds32: constify ptr_argTrevor Saunders2-1/+6
it points to the result of strchr on a const char *, so it aliases something that is const. Further its only passed to a function that expects a const char *, so there's no reason for it to not be const. gas/ChangeLog: 2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-nds32.c (nds32_parse_option): Make the type of ptr_arg const char *.
2016-06-03Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.Peter Bergner7-1/+127
opcodes/ PR binutils/20196 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable opcodes for E6500. gas/ PR binutils/20196 * gas/testsuite/gas/ppc/e6500.s <lbarx, lharx, lwarx, ldarx, stbcx., sthcx., stwcx., stdcx.>: Add tests. * gas/testsuite/gas/ppc/e6500.d: Likewise. * gas/testsuite/gas/ppc/power8.s: Likewise. * gas/testsuite/gas/ppc/power8.d: Likewise. * gas/testsuite/gas/ppc/power4.s <lwarx, ldarx, stwcx., stdcx.>: Add tests. * gas/testsuite/gas/ppc/power4.d: Likewise.
2016-06-03Handle indirect branches for AMD64 and Intel64H.J. Lu6-24/+83
AMD64 spec and Intel64 spec differ in indirect branches in 64-bit mode. AMD64 supports indirect branches with 16-bit address via the data size prefix while the data size prefix is ignored by Intel64. gas/ PR binutis/18386 * testsuite/gas/i386/i386.exp: Run x86-64-branch-4. * testsuite/gas/i386/x86-64-branch.d: Updated. * testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise. * testsuite/gas/i386/x86-64-branch-4.l: New file. * testsuite/gas/i386/x86-64-branch-4.s: Likewise. opcodes/ PR binutis/18386 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode. (indir_v_mode): New. Add comments for '&'. (reg_table): Replace "{T|}" with "{&|}" on call and jmp. (putop): Handle '&'. (intel_operand_size): Handle indir_v_mode. (OP_E_register): Likewise. * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add 64-bit indirect call/jmp for AMD64. * i386-tbl.h: Regenerated
2016-06-03[AArch64][gas] Add support for Cortex-A73Kyrylo Tkachov3-0/+8
* config/tc-aarch64.c (aarch64_cpus): Add cortex-a73 entry. * doc/c-aarch64.texi (-mcpu): Document cortex-a73 value.
2016-06-03[ARM][gas] Add support for Cortex-A73Kyrylo Tkachov3-0/+8
* config/tc-arm.c (arm_cpus): Add cortex-a73 entry. * doc/c-arm.texi (-mcpu=): Document cortex-a73 value.
2016-06-02Allow ARC Linux targets that do not use uclibc.Vineet Gupta2-1/+5
bfd * config.bfd: Replace -uclibc with *. gas * configure.tgt: Replace -uclibc with *. ld * configure.tgt: Replace -uclibc with *.
2016-06-02Add support for 48 and 64 bit ARC instructions.Andrew Burgess4-69/+276
gas * config/tc-arc.c (parse_opcode_flags): New function. (find_opcode_match): Move flag parsing code out to new function. Ignore operands marked IGNORE. (build_fake_opcode_hash_entry): New function. (find_special_case_long_opcode): New function. (find_special_case): Lookup long opcodes. * testsuite/gas/arc/nps400-7.d: New file. * testsuite/gas/arc/nps400-7.s: New file. include * opcode/arc.h (MAX_INSN_ARGS): Increase to 16. (struct arc_long_opcode): New structure. (arc_long_opcodes): Declare. (arc_num_long_opcodes): Declare. opcodes * arc-dis.c (struct arc_operand_iterator): New structure. (find_format_from_table): All the old content from find_format, with some minor adjustments, and parameter renaming. (find_format_long_instructions): New function. (find_format): Rewritten. (arc_insn_length): Add LSB parameter. (extract_operand_value): New function. (operand_iterator_next): New function. (print_insn_arc): Use new functions to find opcode, and iterator over operands. * arc-opc.c (insert_nps_3bit_dst_short): New function. (extract_nps_3bit_dst_short): New function. (insert_nps_3bit_src2_short): New function. (extract_nps_3bit_src2_short): New function. (insert_nps_bitop1_size): New function. (extract_nps_bitop1_size): New function. (insert_nps_bitop2_size): New function. (extract_nps_bitop2_size): New function. (insert_nps_bitop_mod4_msb): New function. (extract_nps_bitop_mod4_msb): New function. (insert_nps_bitop_mod4_lsb): New function. (extract_nps_bitop_mod4_lsb): New function. (insert_nps_bitop_dst_pos3_pos4): New function. (extract_nps_bitop_dst_pos3_pos4): New function. (insert_nps_bitop_ins_ext): New function. (extract_nps_bitop_ins_ext): New function. (arc_operands): Add new operands. (arc_long_opcodes): New global array. (arc_num_long_opcodes): New global. * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
2016-06-01ns32k: remove dupplicate definition of input_line_pointerTrevor Saunders2-1/+4
gas/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-ns32k.c: Remove definition of input_line_pointer.
2016-06-01avr: replace sentinal with iteration from 0 to ARRAY_SIZETrevor Saunders2-4/+8
This seems a little easier to understand than using a sentinal, and will hopefully let the compiler optimize the loop better. It also has the effect that we stop initializing a field of the sentinal that is an enum with zero. gas/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-avr.c (avr_parse_cons_expression): Replace iteration to sentinal with iteration to array size.
2016-06-01xtensa: typedef enums when defining themTrevor Saunders2-10/+11
I think this is the more typical way to do this. Its also slightly shorter and less repeditive. gas/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/xtensa-relax.h: Move typedefs of enums to the enums definition.
2016-06-01ns32k: use XOBNEW in another spotTrevor Saunders2-1/+6
gas/ChangeLog: 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-ns32k.c (bit_fix_new): Replace obstack-alloc with XOBNEW macro.
2016-06-01Add support for some variants of the ARC nps400 rflt instruction.Graham Markall3-50/+62
gas * testsuite/gas/arc/nps-400-1.s: Add rflt variants with operands of types a,b,u6, 0,b,u6, and 0,b,limm. * testsuite/gas/arc/nps-400-1.d: Likewise. opcodes * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and 0,b,limm to the rflt instruction.
2016-05-29Add missing ChangeLog entriesH.J. Lu1-0/+15
2016-05-29Add .noavx512XX directives to x86 assemblerH.J. Lu7-0/+801
Add .noavx512f, .noavx512cd, .noavx512er, .noavx512pf, .noavx512dq, .noavx512bw, .noavx512vl, .noavx512ifma, .noavx512vbmi directives to x86 assembler. gas/ PR gas/20145 * config/tc-i386.c (cpu_noarch): Add noavx512f, noavx512cd, noavx512er, noavx512pf, noavx512dq, noavx512bw, noavx512vl, noavx512ifma and noavx512vbmi. * doc/c-i386.texi: Mention noavx512f, noavx512cd, noavx512er, noavx512pf, noavx512dq, noavx512bw, noavx512vl, noavx512ifma and noavx512vbmi. * testsuite/gas/i386/i386.exp: Run noavx512-1 and noavx512-2. * testsuite/gas/i386/noavx512-1.l: New file. * testsuite/gas/i386/noavx512-1.s: Likewise. * testsuite/gas/i386/noavx512-2.l: Likewise. * testsuite/gas/i386/noavx512-2.s: Likewise. opcodes/ PR gas/20145 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS, CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS, CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS, CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS, CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS. * i386-init.h: Regenerated.
2016-05-27Update x86 CPU_XXX_FLAGS handlingH.J. Lu17-10/+482
Support defining CPU_XXX_FLAGS with other CPU_XXX_FLAGS. Update CPU_XXX_FLAGS to enable more bits like x87 and SYSCALL. Don't enable MMX when enabling SSE, AVX or AVX512. Don't disable AVX nor AVX512 when disabling SSE. Don't disable AVX512 when disabling AVX. Disable F16C, FMA, FMA4 and XOP when disabling AVX. Add 87, no287, no387, no687, nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2 directives to x86 assembler. TODO: Add more .noXXX, like .noavx512f, directives to x86 assembler. gas/ PR gas/20145 * config/tc-i386.c (cpu_arch): Add 687. (cpu_noarch): Add no287, no387, no687, nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2. (parse_real_register): Check cpuregmmx instead of cpummx for MMX register. Check cpuregxmm instead of cpusse for XMM register. Check cpuregymm instead of cpuavx for YMM register. Check cpuregzmm/cpuregmask instead of cpuavx512f for ZMMM/mask register. * doc/c-i386.texi: Mention 687, no287, no387, no687, nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2. * testsuite/gas/i386/arch-10-prefetchw.d (as): Add mmx. * testsuite/gas/i386/arch-10.d (as): Likewise. * testsuite/gas/i386/arch-11.s: Add ".arch .mmx". * testsuite/gas/i386/i386.exp: Pass mmx to assembler for arch-10-3 and arch-10-4. Run no87-3, nosse-4, nosse-5, noavx-3 and noavx-4. * testsuite/gas/i386/no87-3.l: New file. * testsuite/gas/i386/no87-3.s: Likewise. * testsuite/gas/i386/noavx-3.l: Likewise. * testsuite/gas/i386/noavx-3.s: Likewise. * testsuite/gas/i386/noavx-4.d: Likewise. * testsuite/gas/i386/noavx-4.s: Likewise. * testsuite/gas/i386/nosse-4.l: Likewise. * testsuite/gas/i386/nosse-4.s: Likewise. * testsuite/gas/i386/nosse-5.d: Likewise. * testsuite/gas/i386/nosse-5.s: Likewise. opcodes/ PR gas/20145 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS. Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS, CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS. Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS, CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS, CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS, CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and CpuRegMask for AVX512. (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM and CpuRegMask. (set_bitfield_from_cpu_flag_init): New function. (set_bitfield): Remove const on f. Call set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS. * i386-opc.h (CpuRegMMX): New. (CpuRegXMM): Likewise. (CpuRegYMM): Likewise. (CpuRegZMM): Likewise. (CpuRegMask): Likewise. (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm and cpuregmask. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2016-05-27Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu2-7/+11
AMD64 vs CpuIntel64 ISA should be handled similar as AT&T vs Intel syntax. Since cpu_flags isn't sorted by position, we need to check the whole cpu_flags array for the maximum position when verifying CpuMax. gas/ PR gas/20154 * config/tc-i386.c (cpu_flags_match): Don't set cpuamd64 nor cpuintel64. (match_template): Check Intel64/AMD64 ISA. opcodes/ PR gas/20154 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64. (opcode_modifiers): Add AMD64 and Intel64. (main): Properly verify CpuMax. * i386-opc.h (CpuAMD64): Removed. (CpuIntel64): Likewise. (CpuMax): Set to CpuNo64. (i386_cpu_flags): Remove cpuamd64 and cpuintel64. (AMD64): New. (Intel64): Likewise. (i386_opcode_modifier): Add amd64 and intel64. (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64 on call and jmp. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2016-05-27Correct CpuMax in i386-opc.hH.J. Lu2-8/+19
CpuMax should be CpuIntel64, not CpuNo64. i386-gen.c is updated to verify that CpuMax is correct. X86 assembler is updated to properly set cpuamd64 and cpuintel64. gas/ PR gas/20154 * config/tc-i386.c (intel64): New. (cpu_flags_match): Set cpuamd64 and cpuintel64. (md_parse_option): Set intel64 instead of cpuamd64 and cpuintel64. opcodes/ PR gas/20154 * i386-gen.c (main): Fail if CpuMax is incorrect. * i386-opc.h (CpuMax): Set to CpuIntel64. * i386-tbl.h: Regenerated.
2016-05-27Don't clear cpu64 nor cpuno64H.J. Lu2-2/+5
No need to clear cpu64 nor cpuno64 since they will be cleared by cpu_flags_and. * config/tc-i386.c (cpu_flags_match): Don't clear cpu64 nor cpuno64.
2016-05-26Add support for new POWER ISA 3.0 instructions.Peter Bergner5-0/+27
opcodes/ * ppc-opc.c (CY): New define. Document it. (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics. gas/ * testsuite/gas/ppc/altivec3.d <vmsumudm>: Add test. * testsuite/gas/ppc/altivec3.s: Likewise. * testsuite/gas/ppc/power9.d <addex[.], lwzmx, vmsumudm>: Add tests. * testsuite/gas/ppc/power9.s: Likewise.
2016-05-26Append ".p2align 4" to some x86 directive testsH.J. Lu11-0/+23
Append ".p2align 4" to some x86 directive tests for explicit paddings for section alignment to avoid implicit section alignment in assembler listings. * testsuite/gas/i386/avx512vl-2.l: Append "#pass". * testsuite/gas/i386/noavx-1.l: Likewise. * testsuite/gas/i386/nommx-1.l: Likewise. * testsuite/gas/i386/nosse-1.l: Likewise. * testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise. * testsuite/gas/i386/avx512vl-2.s: Append ".p2align 4". * testsuite/gas/i386/noavx-1.s: Likewise. * testsuite/gas/i386/nommx-1.s: Likewise. * testsuite/gas/i386/nosse-1.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
2016-05-26metag: make an array's type unsigned char[]Trevor Saunders2-1/+6
It contains values between 128 and 256 which fit in an unsigned char, but not a signed char, so we should explicitly use unsigned char to not rely on how these values are converted to signed char. gas/ChangeLog: 2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-metag.c (metag_handle_align): Make the type of noop unsigned char.
2016-05-26rx: make the type of a variable bfd_reloc_code_real_typeTrevor Saunders2-1/+9
gas/ChangeLog: 2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-rx.c (md_convert_frag): Make the type of reloc_type bfd_reloc_code_real_type.
2016-05-25Require another match for AVX512VLH.J. Lu11-0/+245
The AVX512VL bit alone isn't sufficient to select a 128-bit or 256-bit AVX512 instruction. We must match another AVX512 bit. PR gas/20140 * config/tc-i386.c (cpu_flags_match): Require another match for AVX512VL. * testsuite/gas/i386/i386.exp: Run avx512vl-1, avx512vl-2, x86-64-avx512vl-1 and x86-64-avx512vl-2. * testsuite/gas/i386/avx512vl-1.l: New file. * testsuite/gas/i386/avx512vl-1.s: Likewise. * testsuite/gas/i386/avx512vl-2.l: Likewise. * testsuite/gas/i386/avx512vl-2.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl-1.l: Likewise. * testsuite/gas/i386/x86-64-avx512vl-1.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise. * testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
2016-05-25Enable VREX for AVX512 directivesH.J. Lu4-0/+23
Enable VREX for AVX512 instructions with upper 16 vector registers. gas/ PR gas/20141 * testsuite/gas/i386/i386.exp: Run x86-64-pr20141. * testsuite/gas/i386/x86-64-pr20141.d: New file. * testsuite/gas/i386/x86-64-pr20141.s: Likewise. opcodes/ PR gas/20141 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. * i386-init.h: Regenerated.
2016-05-25Reimplement .no87/.nommx/.nosse/.noavx directivesH.J. Lu19-163/+418
Move all .noXXX directives to cpu_noarch. gas/ * config/tc-i386.c (arch_entry): Remove negated. (noarch_entry): New struct. (cpu_arch): Updated. Remove .no87, .nommx, .nosse and .noavx. (cpu_noarch): New. (set_cpu_arch): Check cpu_noarch after cpu_arch. (md_parse_option): Allow -march=+nosse. Check cpu_noarch after cpu_arch. (output_message): New function. (show_arch): Use it. Handle cpu_noarch. * testsuite/gas/i386/i386.exp: Run nommx-1, nommx-2, nommx-3, nosse-1, nosse-2, nosse-3, noavx-1 and noavx-2. * testsuite/gas/i386/noavx-1.l: New file. * testsuite/gas/i386/noavx-1.s: Likewise. * testsuite/gas/i386/noavx-2.s: Likewise. * testsuite/gas/i386/noavx-2.l: Likewise. * testsuite/gas/i386/nommx-1.s: Likewise. * testsuite/gas/i386/nommx-1.l: Likewise. * testsuite/gas/i386/nommx-2.s: Likewise. * testsuite/gas/i386/nommx-2.l: Likewise. * testsuite/gas/i386/nommx-3.s: Likewise. * testsuite/gas/i386/nommx-3.l: Likewise. * testsuite/gas/i386/nosse-1.s: Likewise. * testsuite/gas/i386/nosse-1.l: Likewise. * testsuite/gas/i386/nosse-2.s: Likewise. * testsuite/gas/i386/nosse-2.l: Likewise. * testsuite/gas/i386/nosse-3.s: Likewise. * testsuite/gas/i386/nosse-3.l: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS. * i386-init.h: Regenerated.
2016-05-25Fix typo in changelog entryNick Clifton1-1/+1
2016-05-25Only generate VMOV.I64 instructions for loading constant floating point ↵Chua Zheng Leong4-3/+14
values if this instruction is supported by the currently selected fpu. PR target/2006764 * config/tc-arm.c (move_or_literal_pool): Only generate a VMOV.I64 instruction if supported by the currently selected fpu variant. * testsuite/gas/arm/vfpv3-ldr_immediate.s: Add test of this PR. * testsuite/gas/arm/vfpv3-ldr_immediate.d: Update expected disassembly.
2016-05-24MIPS/GAS: Treat local jump relocs the same no matter if REL or RELAMaciej W. Rozycki7-7/+147
Do not convert jump relocs against local MIPS16 or microMIPS symbols to refer to a section symbol instead even on RELA targets, as it makes it impossible for the linker to make a JAL to JALX conversion based on ISA symbol annotation, breaking regular and compressed MIPS interlinking. gas/ * config/tc-mips.c (mips_fix_adjustable): Also return 0 for jump relocations against MIPS16 or microMIPS symbols on RELA targets. * testsuite/gas/mips/jalx-local.d: New test. * testsuite/gas/mips/jalx-local-n32.d: New test. * testsuite/gas/mips/jalx-local-n64.d: New test. * testsuite/gas/mips/jalx-local.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/jalx-local.d: New test. * testsuite/ld-mips-elf/jalx-local-n32.d: New test. * testsuite/ld-mips-elf/jalx-local-n64.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-05-24MIPS/GAS: Cut TLS reloc dead code path in `md_apply_fix'Maciej W. Rozycki2-8/+12
With code refactoring made in commit b886a2ab0d52 and the addition of `calculate_reloc' and a separate test for TLS relocs against constants made there the preexisting fall-through from the TLS reloc switch case has effectively become a dead execution path. This is because the call to `calculate_reloc' present there is only made if `fixP->fx_done' is true, which can only be the case if `fixP->fx_addsy' is NULL, which in turn has already triggered the TLS reloc test and made execution break out of the switch statement. Remove the fall-through then and reshape code accordingly. gas/ * config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS16_TLS_TPREL_LO16>: Remove fall-through, adjust code accordingly.
2016-05-24xtensa: make map_suffix_reloc_to_operator return operatorTTrevor Saunders2-4/+10
It always returns an element of the enum operatorT, so it should be clearer to make that the return type. gas/ChangeLog: 2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-xtensa.c (struct suffix_reloc_map): Change type of field operator to operatorT. (map_suffix_reloc_to_operator): Change return type to operatorT.
2016-05-24d30v: make var type operatorTTrevor Saunders2-1/+5
gas/ChangeLog: 2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-d30v.c (find_format): Change type of X_op to operatorT.
2016-05-24mmix: constify handler_charpTrevor Saunders2-1/+6
gas/ChangeLog: 2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-mmix.c (mmix_parse_predefined_name): Change type of handler_charp to const char *.
2016-05-24ft32: fixup TARGET_FORMATTrevor Saunders2-3/+7
Nothing ever assigns to ft32_target_format, so its always null, which means the bfd target arch is the default one. It looks like ft32 only has one target format, so we can just define TARGET_FORMAT to be that literal string. gas/ChangeLog: 2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-ft32.h (DEFAULT_TARGET_FORMAT): Remove. (ft32_target_format): Likewise. (TARGET_FORMAT): Adjust.
2016-05-24ia64: use XOBNEW and XOBNEWVECTrevor Saunders2-4/+9
gas/ChangeLog: 2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-ia64.c (dot_rot): simplify allocations from obstacks. (ia64_frob_label): Likewise.
2016-05-24change some variable's type to op_errTrevor Saunders3-2/+7
They only hold values from the op_err enum, so it should be clearer to give them the enum type. gas/ChangeLog: 2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-cr16.c (check_range): Make type of retval op_err. * config/tc-crx.c: Likewise.
2016-05-23[ARC] Add XY registers, update neg instruction.Claudiu Zissulescu2-1/+32
gas/ 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (md_begin): Add XY registers. (cpu_types): Code density is default off for ARC EM. opcodes/ 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com> * arc-tbl.h (neg): New instruction variant.
2016-05-23[ARC] Rename "class" named attributes.Claudiu Zissulescu2-12/+18
gas/ 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com> * config/tc-arc.c (attributes_t): Renamed attribute class to attr_class. (find_opcode_match, assemble_insn, tokenize_extinsn): Changed. opcode/ 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com> * arc-dis.c (find_format, find_format, get_auxreg) (print_insn_arc): Changed. * arc-ext.h (INSERT_XOP): Likewise. include/ 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com> * opcode/arc.h (struct arc_opcode): Renamed attribute class to insn_class. (struct arc_flag_class): Renamed attribute class to flag_class.
2016-05-23oops - omitted from previous deltaNick Clifton1-0/+4
2016-05-23Add support for configuring for the ARM Phoenix target.Kuba Sejdak1-0/+1
bfd * config.bfd: Add entry for arm-phoenix. gas * configuse.tgt: Add entry for arm-phoenix. ld * Makefile.am: Add earmelf_phoenix.c. * Makefile.in: Regenerate. * configure.tgt: Add entry for arm-phoenix. * emulparams/armelf_phoenix.sh: New file.
2016-05-23tic54x: use concat moreTrevor Saunders2-6/+9
gas/ChangeLog: 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-tic54x.c (tic54x_sect): simplify string creation.
2016-05-23spu: make some constants unsignedTrevor Saunders2-1/+5
The field in spu_opcode is unsigned, and for some values of opcode we can end up shifting into the high bit. So avoid possibly creating a negative number and then assigning it to a unsigned field by shifting an unsigned constant. gas/ChangeLog: 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-spu.c (APUOP): Use OPCODE as an unsigned constant.
2016-05-23tic54x: rename typedef of struct symbol_Trevor Saunders2-23/+34
generic gas code has a struct symbol, and tic54x typedefs a struct to symbol. This seems at least rather confusing, and it seems like target specific headers shouldn't put such generic names in the global namespace preventing other generic code from using them. opcodes/ChangeLog: 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * tic54x-dis.c (sprint_mmr): Adjust. * tic54x-opc.c: Likewise. gas/ChangeLog: 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-tic54x.c (tic54x_mmregs): Adjust. (md_begin): Likewise. (encode_condition): Likewise. (encode_cc3): Likewise. (encode_cc2): Likewise. (encode_operand): Likewise. (tic54x_undefined_symbol): Likewise. include/ChangeLog: 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of plain symbol.
2016-05-20MIPS: Add support for P6600Matthew Fortune3-1/+9
gas/ * config/tc-mips.c (mips_cpu_info_table): Update comment. Add p6600 entry. * doc/c-mips.texi: Document p6600 -march option.
2016-05-20Preserve addend for R_386_GOT32 and R_X86_64_GOT32H.J. Lu8-5/+64
We should preserve addend for R_386_GOT32 and R_X86_64_GOT32 as in "movl $foo@GOT + 4, %eax" and "movq $foo@GOT + 4, %rax". PR gas/19600 * config/tc-i386.c (md_apply_fix): Preserve addend for BFD_RELOC_386_GOT32 and BFD_RELOC_X86_64_GOT32. * testsuite/gas/i386/addend.d: New file. * testsuite/gas/i386/addend.s: Likewise. * testsuite/gas/i386/x86-64-addend.d: Likewise. * testsuite/gas/i386/x86-64-addend.s: Likewise. * testsuite/gas/i386/i386.exp: Run addend and x86-64-addend. * testsuite/gas/i386/reloc32.d: Updated.
2016-05-20MIPS: Fix the encoding of immediates with microMIPS JALXMaciej W. Rozycki11-1/+234
The microMIPS JALX instruction shares the R_MICROMIPS_26_S1 relocation with microMIPS J/JAL/JALS instructions, however unlike the latters its encoded immediate argument is unusually shifted left by 2 rather than 1 in calculating the value used for the operation requested. We already handle this exception in `mips_elf_calculate_relocation' in LD, in a scenario where JALX is produced as a result of relaxing JAL for the purpose of making a cross-mode jump. We also get it right in the disassembler in `decode_micromips_operand'. What we don't correctly do however is processing microMIPS JALX produced by GAS from an assembly source, where a non-zero constant argument or a symbol reference with a non-zero in-place addend has been used. In this case the same calculation is made as for microMIPS J/JAL/JALS, causing the wrong encoding to be produced by GAS on making an object file, and then again by LD in the final link. The latter in particular causes the calculation, where the addend fits in the relocatable field, to produce different final addresses for the same source code depending on whether REL or RELA relocations are used. Correct these issues by special-casing microMIPS JALX in the places that have been previously missed. bfd/ * elfxx-mips.c (mips_elf_read_rel_addend): Adjust the addend for microMIPS JALX. gas/ * config/tc-mips.c (append_insn): Correct the encoding of a constant argument for microMIPS JALX. (tc_gen_reloc): Correct the encoding of an in-place addend for microMIPS JALX. * testsuite/gas/mips/jalx-addend.d: New test. * testsuite/gas/mips/jalx-addend-n32.d: New test. * testsuite/gas/mips/jalx-addend-n64.d: New test. * testsuite/gas/mips/jalx-imm.d: New test. * testsuite/gas/mips/jalx-imm-n32.d: New test. * testsuite/gas/mips/jalx-imm-n64.d: New test. * testsuite/gas/mips/jalx-addend.s: New test source. * testsuite/gas/mips/jalx-imm.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/jalx-addend.d: New test. * testsuite/ld-mips-elf/jalx-addend-n32.d: New test. * testsuite/ld-mips-elf/jalx-addend-n64.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
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