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2013-09-18binutils/Tristan Gingold2-0/+6
2013-09-18 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.24. gas/ 2013-09-18 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.24. ld/ 2013-09-18 Tristan Gingold <gingold@adacore.com> * NEWS: Add marker for 2.24.
2013-09-18 * config/tc-msp430.c (OPTION_MOVE_DATA): Define.Nick Clifton3-1/+59
(move_data): New variable. (md_parse_option): Parse -md. (msp430_section): New function. Catch references to the .bss or .data sections and generate a special symbol for use by the libcrt library. (md_pseudo_table): Intercept .section directives. (md_longopt): Add -md (md_show_usage): Likewise. (msp430_operands): Generate a warning message if a NOP is inserted into the instruction stream. * doc/c-msp430.texi (node MSP430 Options): Document -md option.
2013-09-172013-09-17 Doug Gilmore <Doug.Gilmore@imgtec.com>Steve Ellcey2-3/+6
* config/tc-mips.c (mips_elf_final_processing): Set EF_MIPS_FP64 for -mgp32 -mfp64, removing old FIXME.
2013-09-17opcodes/Richard Sandiford3-0/+8
* s390-opc.txt (clih): Make the immediate unsigned. gas/testsuite/ * gas/s390/zarch-z196.s, gas/s390/zarch-z196.d: Test CLIH with 4000000000.
2013-09-16gas/config/tc-arm.c: Fix parsing of NEON load/store element sizes.Will Newton8-0/+47
The existing code would accept VLD2.64 and similar undefined instructions. gas/ChangeLog: 2013-09-16 Will Newton <will.newton@linaro.org> * config/tc-arm.c (do_neon_ld_st_interleave): Add constraint disallowing element size 64 with interleave other than 1. gas/testsuite/ChangeLog: 2013-09-16 Will Newton <will.newton@linaro.org> * gas/arm/neon-ldst-es.d: Add VLD1.64 instructions. * gas/arm/neon-ldst-es.s: Likewise. * testsuite/gas/arm/neon-ldst-es-bad.d: New file. * testsuite/gas/arm/neon-ldst-es-bad.l: Likewise. * testsuite/gas/arm/neon-ldst-es-bad.s: Likewise.
2013-09-122013-09-12 Chao-ying Fu <Chao-ying.Fu@imgtec.com>Chao-ying Fu4-0/+24
* gas/mips/bltzal.s: New file. * gas/mips/bltzal.l: New file. * gas/mips/mips.exp: Run the bltzal test.
2013-09-122013-09-12 Chao-ying Fu <Chao-ying.Fu@imgtec.com>Chao-ying Fu2-0/+9
* config/tc-mips.c (match_insn): Set error when $31 is used for bltzal* and bgezal*.
2013-09-12 * dwarf.c (dwarf_vmatoa): Rename to dwarf_vmatoa_1 and add aNick Clifton23-266/+292
precision parameter. (dwarf_vmatoa): New wrapper for dwarf_vmatoa_1. (print_dwarf_vma): Use dwarf_vmatoa_1. (SAFE_BYTE_GET): Add check that VAL is big enough to contain AMOUNT bytes. (process_debug_info): Use an unsigned int for the offset size. (process_debug_pubnames): Likewise. (display_debug_aranges): Likewise. (struct Frame_Chunk): Use dwarf_vma type for pc_begin and pc_range fields. (frame_display_row): Use print_dwarf_vma to display dwarf_vma values. (display_debug_frames): Likewise. * binutils-all/x86-64/compressed-1a.d: Update expected output to allow for 64-bit addresses. * ld-elf/eh1.d: Update expected output to allow for 64-bit addresses. * ld-elf/eh2.d: Likewise. * ld-elf/eh3.d: Likewise. * ld-elf/eh4.d: Likewise. * ld-elf/eh5.d: Likewise. * ld-elf/eh6.d: Likewise. * ld-mips-elf/eh-frame1-n64.d: Likewise. * ld-mips-elf/eh-frame2-n64.d: Likewise. * ld-mips-elf/eh-frame3.d: Likewise. * gas/cfi/cfi-alpha-1.d: Update expected output to allow for 64-bit addresses. * gas/cfi/cfi-alpha-3.d: Likewise. * gas/cfi/cfi-arm-1.d: Likewise. * gas/cfi/cfi-common-1.d: Likewise. * gas/cfi/cfi-common-2.d: Likewise. * gas/cfi/cfi-common-3.d: Likewise. * gas/cfi/cfi-common-4.d: Likewise. * gas/cfi/cfi-common-5.d: Likewise. * gas/cfi/cfi-common-6.d: Likewise. * gas/cfi/cfi-common-7.d: Likewise. * gas/cfi/cfi-hppa-1.d: Likewise. * gas/cfi/cfi-i386-2.d: Likewise. * gas/cfi/cfi-i386.d: Likewise. * gas/cfi/cfi-m68k.d: Likewise. * gas/cfi/cfi-mips-1.d: Likewise. * gas/cfi/cfi-ppc-1.d: Likewise. * gas/cfi/cfi-s390-1.d: Likewise. * gas/cfi/cfi-s390x-1.d: Likewise. * gas/cfi/cfi-sh-1.d: Likewise. * gas/cfi/cfi-sparc-1.d: Likewise. * gas/cfi/cfi-sparc64-1.d: Likewise. * gas/cfi/cfi-x86_64.d: Likewise.
2013-09-04gas/Tristan Gingold6-0/+56
* config/tc-ppc.c (md_apply_fix): Handle defined after use toc symbols. gas/testsuite/ * gas/ppc/aix.exp: Run xcoff-toc-1 test. * gas/ppc/xcoff-toc-1.s, gas/ppc/xcoff-toc-1.d: New test.
2013-09-04 PR gas/15914Nick Clifton9-82/+198
* config/tc-arm.c (T16_32_TAB): Add _udf. (do_t_udf): New function. (insns): Add "udf". * gas/arm/udf-bad.s: New file. * gas/arm/udf-bad.d: New file. * gas/arm/udf-bad.l: New file. * gas/arm/udf.s: New file. * gas/arm/udf.d: New file. * gas/arm/udf.l: New file. * arm-dis.c (arm_opcodes): Add udf. (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION. (thumb32_opcodes): Add udf.w. (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
2013-08-28 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if theNick Clifton3-1/+11
immediate is not suitable for the 32-bit ABI. * gas/aarch64/illegal.s: Add illegal constant for logical operation. * gas/aarch64/illegal.l: Add expected error message.
2013-08-23* config/rx-parse.y: Rearrange the components of a bison grammar to issueDJ Delorie2-6/+15
assembler errors at correct position.
2013-08-23 opcodes/Maciej W. Rozycki6-23/+17
* micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps", replacing NODS. gas/testsuite/ * gas/testsuite/gas/mips/micromips-insn32.d: Adjust for delay slot scheduling of ALNV.PS. * gas/testsuite/gas/mips/micromips-noinsn32.d: Likewise. * gas/testsuite/gas/mips/micromips-trap.d: Likewise. * gas/testsuite/gas/mips/micromips.d: Likewise. * gas/testsuite/gas/mips/micromips@alnv_ps-swap.d: Likewise.
2013-08-23 PR binutils/15834Nick Clifton9-27/+34
Fix typos: --- bfd/bfdio.c | 2 +- bfd/elf32-spu.c | 2 +- bfd/elfnn-aarch64.c | 2 +- binutils/od-xcoff.c | 2 +- config/tcl.m4 | 2 +- gas/config/tc-ia64.c | 2 +- gas/config/tc-sparc.c | 2 +- gas/config/tc-z80.c | 12 ++++++------ gas/doc/c-i386.texi | 6 +++--- gas/doc/c-m32r.texi | 2 +- gas/testsuite/gas/d10v/instruction_packing.d | 2 +- gas/testsuite/gas/z80/atend.d | 2 +- gold/object.h | 2 +- include/gdb/remote-sim.h | 2 +- include/opcode/ChangeLog | 2 +- include/opcode/i960.h | 2 +- ld/testsuite/ld-mips-elf/mips16-pic-1.inc | 2 +- opcodes/aarch64-asm.c | 2 +- opcodes/aarch64-dis.c | 2 +- opcodes/msp430-dis.c | 2 +-
2013-08-23gas/config/tc-arm.c: Improve validation of NEON addressing modes.Will Newton5-13/+40
NEON vector load and store instructions do not accept immediates or pre-indexed base plus offset addressing modes, so make sure that the assembler enforces this. gas/ChangeLog: 2013-08-23 Will Newton <will.newton@linaro.org> * config/tc-arm.c (do_neon_ldx_stx): Add extra constraints for pre-indexed addressing modes. * testsuite/gas/arm/neon-addressing-bad.l: Add test for VLDn and VSTn instructions. * testsuite/gas/arm/neon-addressing-bad.s: Likewise. gas/testsuite/ChangeLog: 2013-08-23 Will Newton <will.newton@linaro.org> * testsuite/gas/arm/neon-addressing-bad.l: Add test for VLDn and VSTn instructions. * testsuite/gas/arm/neon-addressing-bad.s: Likewise.
2013-08-21 * symbols.c (fb_label_instance_inc, fb_label_instance): ProperlyAlan Modra2-2/+7
range check label number for use with fb_low_counter array.
2013-08-19gas/Richard Sandiford64-1627/+1675
* config/tc-mips.c (mips_check_isa_supports_ase, reg_lookup) (mips_parse_argument_token, validate_micromips_insn, md_begin) (check_regno, match_float_constant, check_completed_insn, append_insn) (match_insn, match_mips16_insn, match_insns, macro_start) (macro_build_ldst_constoffset, load_register, macro, mips_ip) (mips16_ip, mips_set_option_string, md_parse_option) (mips_after_parse_args, mips_after_parse_args, md_pcrel_from) (md_apply_fix, s_align, s_option, s_mipsset, s_tls_rel_directive) (s_gpword, s_gpdword, s_ehword, s_nan, tc_gen_reloc, md_convert_frag) (s_mips_end, s_mips_ent, s_mips_frame, s_mips_mask, mips_parse_cpu): Start error messages with a lower-case letter. Do not end error messages with a period. Wrap long messages to 80 character-lines. Use "cannot" instead of "can't" and "can not". gas/testsuite/ * gas/mips/ase-errors-1.l, gas/mips/ase-errors-2.l, gas/mips/ase-errors-3.l, gas/mips/ase-errors-4.l, gas/mips/at-2.l, gas/mips/baddata1.l, gas/mips/elf-rel30.l, gas/mips/illegal.l, gas/mips/jalr.l, gas/mips/ldstla-32-1.l, gas/mips/ldstla-32-mips3-1.l, gas/mips/lui-1.l, gas/mips/macro-warn-1.l, gas/mips/macro-warn-1-n32.l, gas/mips/macro-warn-2.l, gas/mips/macro-warn-3.l, gas/mips/macro-warn-4.l, gas/mips/micromips-branch-delay.l, gas/mips/micromips-branch-relax.l, gas/mips/micromips-branch-relax-pic.l, gas/mips/micromips-ill.l, gas/mips/micromips.l, gas/mips/micromips-size-0.l, gas/mips/micromips-size-1.l, gas/mips/micromips-warn-branch-delay.l, gas/mips/micromips-warn.l, gas/mips/mips16e-64.l, gas/mips/mips16e-save-err.l, gas/mips/mips1-fp.l, gas/mips/mips32r2-fp32.l, gas/mips/mips32r2-ill.l, gas/mips/mips32-sf32.l, gas/mips/mips4-branch-likely.l, gas/mips/mips4-fp.l, gas/mips/mips5-fp.l, gas/mips/mips64-mips3d.l, gas/mips/mips-double-float-flag.l, gas/mips/mips-gp64-fp32.l, gas/mips/mips-gp64-fp64.l, gas/mips/mips-hard-float-flag.l, gas/mips/mips-macro-ill-nofp.l, gas/mips/mips-macro-ill-sfp.l, gas/mips/nan-error-1.l, gas/mips/nan-error-2.l, gas/mips/noat-2.l, gas/mips/noat-3.l, gas/mips/noat-4.l, gas/mips/noat-5.l, gas/mips/noat-6.l, gas/mips/noat-7.l, gas/mips/octeon-ill.l, gas/mips/r5900-error-vu0.l, gas/mips/r5900-nollsc.l, gas/mips/relax-bc1any.l, gas/mips/relax-bposge.l, gas/mips/relax.l, gas/mips/relax-swap1.l, gas/mips/relax-swap2.l, gas/mips/set-arch.l, gas/mips/tls-ill.l, gas/mips/vr5400-ill.l: Adjust expected output.
2013-08-19gas/Richard Sandiford2-78/+48
* config/tc-mips.c (imm_expr): Expand comment. (set_at, macro, mips16_macro): Expect imm_expr to be O_constant when populated.
2013-08-19include/opcode/Richard Sandiford2-21/+11
* mips.h: Remove references to "+I" and imm2_expr. gas/ * config/tc-mips.c (imm2_expr): Delete. (md_assemble, match_insn, imm2_expr.X_op, mips_ip): Update accordingly.
2013-08-19include/opcode/Richard Sandiford11-212/+97
* mips.h (M_DEXT, M_DINS): Delete. opcodes/ * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins" macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases. Use +H rather than +C for the real "dext". * mips-opc.c (mips_builtin_opcodes): Likewise. gas/ * config/tc-mips.c (report_bad_range, report_bad_field): Delete. (macro): Remove M_DEXT and M_DINS handling. gas/testsuite/ * gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS error messages to have the same form as the EXT and INS ones. * gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d, gas/mips/micromips.d, gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect "dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu".
2013-08-19gas/Richard Sandiford2-179/+191
* config/tc-mips.c (mips_arg_info): Replace allow_nonconst and lax_max with lax_match. (match_int_operand): Update accordingly. Don't report an error for !lax_match-only cases. (match_insn): Replace more_alts with lax_match and use it to initialize the mips_arg_info field. Add a complete_p parameter. Handle implicit VU0 suffixes here. (match_invalid_for_isa, match_insns, match_mips16_insns): New functions. (mips_ip, mips16_ip): Use them.
2013-08-19gas/Richard Sandiford6-36/+51
* config/tc-mips.c (match_expression): Report uses of registers here. Add a "must be an immediate expression" error. Handle elided offsets here rather than... (match_int_operand): ...here. gas/testsuite/ * gas/mips/octeon-ill.l: Adjust expected output. * gas/mips/lui-1.l, gas/mips/lui-1.s: Add more cases.
2013-08-19gas/Richard Sandiford18-302/+332
* config/tc-mips.c (mips_arg_info): Remove soft_match. (match_out_of_range, match_not_constant): New functions. (match_const_int): Remove fallback parameter and check for soft_match. Use match_not_constant. (match_mapped_int_operand, match_addiusp_operand) (match_perf_reg_operand, match_save_restore_list_operand) (match_mdmx_imm_reg_operand): Update accordingly. Use match_out_of_range and set_insn_error* instead of as_bad. (match_int_operand): Likewise. Use match_not_constant in the !allows_nonconst case. (match_float_constant): Report invalid float constants. (match_insn, match_mips16_insn): Remove soft_match code. Rely on match_float_constant to check for invalid constants. Fail the match if match_const_int or match_float_constant return false. (mips_ip): Update accordingly. (mips16_ip): Likewise. Undo null termination of instruction name once lookup is complete. gas/testsuite/ * gas/mips/ext-ill.l, gas/mips/lui-1.l, gas/mips/mips16e-64.l, gas/mips/mips32r2-ill-fp64.l, gas/mips/mips32r2-ill-nofp.l, gas/mips/mips32r2-ill.l, gas/mips/mips64r2-ill.l, gas/mips/octeon-ill.l, gas/mips/r5900-error-vu0.l, gas/mips/vr5400-ill.l: Adjust expected errors. * gas/mips/micromips-size-0.l, gas/mips/micromips-size-0.s: Likewise. Add new tests. * gas/mips/mips16e-save-err.s, gas/mips/mips16e-save-err.l: New test. * gas/mips/mips.exp: Run it.
2013-08-19gas/Richard Sandiford4-70/+213
* config/tc-mips.c (mips_insn_error_format): New enum. (mips_insn_error): New struct. (insn_error): Change to a mips_insn_error. (clear_insn_error, set_insn_error_format, set_insn_error) (set_insn_error_i, set_insn_error_ss, report_insn_error): New functions. (mips_parse_argument_token, md_assemble, match_insn) (match_mips16_insn): Use them instead of manipulating insn_error directly. (mips_ip, mips16_ip): Likewise. Simplify control flow. gas/testsuite/ * gas/mips/micromips-ill.l: Expect "floating-point expression required"
2013-08-19gas/Richard Sandiford2-499/+536
* config/tc-mips.c (normalize_constant_expr): Move further up file. (normalize_address_expr): Likewise. (match_insn, match_mips16_insn): New functions, split out from... (mips_ip, mips16_ip): ...here.
2013-08-19include/opcode/Richard Sandiford2-55/+37
* mips.h (OP_OPTIONAL_REG): New mips_operand_type. (mips_optional_operand_p): New function. opcodes/ * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros. * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG and OPTIONAL_MAPPED_REG. * mips-opc.c (decode_mips_operand): Likewise. * mips16-opc.c (decode_mips16_operand): Likewise. * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG. gas/ * config/tc-mips.c (operand_reg_mask, match_operand): Handle OP_OPTIONAL_REG. (mips_ip, mips16_ip): Use mips_optional_operand_p to check for optional operands.
2013-08-16 * config/tc-ppc.c (ppc_elf_cons): Allow @l and other relocAlan Modra2-2/+6
modifiers generally.
2013-08-16 * config/tc-ppc.c (ppc_elf_lcomm): Use subsection 1.Alan Modra2-8/+11
2013-08-14 * config/tc-ppc.c (ppc_comm): Accept optional fourth .lcommDavid Edelsohn2-5/+24
argument as alignment.
2013-08-09 * elf32-rl78.c (rl78_elf_merge_private_bfd_data): Complain if G10Nick Clifton4-8/+40
flag bits do not match. (rl78_elf_print_private_bfd_data): Describe G10 flag. * readelf.c (get_machine_flags): Handle RL78 G10 flag. * config/tc-rl78.c (elf_flags): New variable. (enum options): Add OPTION_G10. (md_longopts): Add mg10. (md_parse_option): Parse -mg10. (rl78_elf_final_processing): New function. * config/tc-rl78.c (tc_final_processing): Define. * doc/c-rl78.texi: Document -mg10 option. * rl78.c (E_FLAG_RL78_G10): Define. * lib/ld-lib.exp (check_shared_lib_support): Note that the RL78 does not support shared library generation.
2013-08-06opcodes/Richard Sandiford7-11/+41
2013-08-06 Jürgen Urban <JuergenUrban@gmx.de> * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of VCLIPW. gas/ 2013-08-06 Jürgen Urban <JuergenUrban@gmx.de> * config/tc-mips.c (match_vu0_suffix_operand): Allow single-channel suffixes to be elided too. (mips_lookup_insn): Don't reject INSN2_VU0_CHANNEL_SUFFIX here. (mips_ip): Assume .xyzw if no VU0 suffix is specified. Allow +N to be omitted too. gas/testsuite/ 2013-08-06 Jürgen Urban <JuergenUrban@gmx.de> * gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l, gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d: Allow single-channel suffixes to be elided.
2013-08-05bfd/Richard Sandiford2-2/+6
2013-08-05 John Tytgat <john@bass-software.com> * po/BLD-POTFILES.in: Regenerate. * po/SRC-POTFILES.in: Likewise. gas/ 2013-08-05 John Tytgat <john@bass-software.com> * po/POTFILES.in: Regenerate. gprof/ 2013-08-05 John Tytgat <john@bass-software.com> * po/POTFILES.in: Regenerate.
2013-08-05gas/Eric Botcazou3-4/+14
* config/tc-sparc.c (sparc_arch_types): Add leon. (sparc_arch): Move sparc4 around and add leon. (sparc_target_format): Document -Aleon. * doc/c-sparc.texi: Likewise. include/ * opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_LEON. opcodes/ * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for bfd_mach_sparc. * sparc-opc.c (MASK_LEON): Define. (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON. (letandleon): New macro. (v9andleon): Likewise. (sparc_opc): Add leon. (umac): Enable for letandleon. (smac): Likewise. (casa): Enable for v9andleon. (cas): Likewise. (casl): Likewise.
2013-08-05gas/Richard Sandiford2-2/+6
* config/tc-mips.c (mips_lookup_insn): Make length and opend signed.
2013-08-04include/opcode/Richard Sandiford11-115/+20642
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * mips.h: Document new VU0 operand characters. (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types. (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R) (OP_REG_R5900_ACC): New mips_reg_operand_types. (INSN2_VU0_CHANNEL_SUFFIX): New macro. (mips_vu0_channel_mask): Declare. opcodes/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. (print_vu0_channel): New function. (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (print_insn_args): Handle '#'. (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX. * mips-opc.c (mips_vu0_channel_mask): New constant. (decode_mips_operand): Handle new VU0 operand types. (VU0, VU0CH): New macros. (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E" for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2. Use "+6" rather than "G" for QMFC2 and QMTC2. gas/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * config/tc-mips.c (MAX_OPERANDS): Bump to 6. (RWARN): Bump to 0x8000000. (RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R) (RTYPE_R5900_ACC): New register types. (RTYPE_MASK): Include them. (R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New macros. (reg_names): Include them. (mips_parse_register_1): New function, split out from... (mips_parse_register): ...here. Add a channels_ptr parameter. Look for VU0 channel suffixes when nonnull. (reg_lookup): Update the call to mips_parse_register. (mips_parse_vu0_channels): New function. (OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types. (mips_operand_token): Add a "channels" field to the union. Extend the comment above "ch" to OT_DOUBLE_CHAR. (mips_parse_base_start): Match -- and ++. Handle channel suffixes. (mips_parse_argument_token): Handle channel suffixes here too. (validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX. Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits. Handle '#' formats. (md_begin): Register $vfN and $vfI registers. (operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. (match_vu0_suffix_operand): New function. (match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (macro): Use "+7" rather than "E" for LDQ2 and STQ2. (mips_lookup_insn): New function. (mips_ip): Use it. Allow "+K" operands to be elided at the end of an instruction. Handle '#' sequences. gas/testsuite/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> * gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric coprocessor registers. * gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d, gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d, gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests. * gas/mips/mips.exp: Run them.
2013-08-03gas/Richard Sandiford2-400/+416
* config/tc-mips.c (macro, mips16_macro): Create an array of operand values and use it instead of sreg, treg, xreg, etc.
2013-08-03include/opcode/Richard Sandiford2-185/+91
* mips.h (mips_pcrel_operand): Inherit from mips_int_operand. (mips_int_operand_min, mips_int_operand_max): New functions. (mips_decode_pcrel_operand): Use mips_decode_int_operand. opcodes/ * mips-formats.h (PCREL): Reorder parameters and update the definition to match new mips_pcrel_operand layout. (JUMP, JALX, BRANCH): Update accordingly. * mips16-opc.c (decode_mips16_operand): Likewise. gas/ * config/tc-mips.c (match_int_operand): Use mips_int_operand_min and mips_int_operand_max. (mips16_immed_operand, mips16_immed_operands, MIPS16_NUM_IMMED): Delete. (mips16_immed_operand, mips16_immed_in_range_p): New functions. (mips16_immed, mips16_extended_frag): Use them. Use mips_int_operand instead of mips16_immed_operand.
2013-08-03gas/Richard Sandiford6-2/+202
* config/tc-mips.c (mips16_macro): Don't use move_register. (mips16_ip): Allow macros to use 'p'. gas/testsuite/ * gas/mips/mips16-macro.s, gas/mips/mips16-macro.d: New test. * gas/mips/mips.exp: Run it.
2013-08-01include/opcode/Richard Sandiford2-215/+313
* mips.h (mips_decode_reg_operand): New function. (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL) (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4) (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI): New macros. (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D) (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T) (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S) (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z) (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D) (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD) (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG) (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP) (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP) (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other macros to cover the gaps. (INSN2_MOD_SP): Replace with... (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros. (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z) (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y) (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z) (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X): Delete. opcodes/ * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): New macros. (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R) (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete. (mips_builtin_opcodes): Use the new position-based read-write flags instead of field-based ones. Use UDI for "udi..." instructions. * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): New macros. (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete. (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags. (WR_SP, RD_16): New macros. (RD_SP): Redefine as an INSN2_* flag. (MOD_SP): Redefine in terms of RD_SP and WR_SP. (mips16_opcodes): Use the new position-based read-write flags instead of field-based ones. Use RD_16 for "nop". Move RD_SP to pinfo2 field. * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): New macros. (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj) (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D) (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete. (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP. (micromips_opcodes): Use the new position-based read-write flags instead of field-based ones. * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand. (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead of field-based flags. gas/ * config/tc-mips.c (MAX_OPERANDS): New macro. (mips_operand_array): New structure. (mips_operands, mips16_operands, micromips_operands): New arrays. (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map) (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map) (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map) (micromips_to_32_reg_q_map): Delete. (insn_operands, insn_opno, insn_extract_operand): New functions. (validate_mips_insn): Take a mips_operand_array as argument and use it to build up a list of operands. Extend to handle INSN_MACRO and MIPS16. (validate_mips16_insn): New function. (validate_micromips_insn): Take a mips_operand_array as argument. Handle INSN_MACRO. (md_begin): Initialize mips_operands, mips16_operands and micromips_operands. Call validate_mips_insn and validate_micromips_insn for macro instructions too. Call validate_mips16_insn for MIPS16 instructions. (insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask): New functions. (gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use them. Handle INSN_UDI. (get_append_method): Use gpr_read_mask.
2013-08-01include/opcode/Richard Sandiford2-24/+24
* mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31) (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH) (MIPS16_INSN_COND_BRANCH): Delete. opcodes/ * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags. (WR_SP): Replace with... (MOD_SP): ...this. (mips16_opcodes): Update accordingly. * mips-dis.c (print_insn_mips16): Likewise. gas/ * config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same flags for MIPS16 and non-MIPS16 instructions. (gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block. (gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too. (gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling. (can_swap_branch_p, get_append_method): Use the same flags for MIPS16 and non-MIPS16 instructions. Fix formatting.
2013-08-01gas/Richard Sandiford2-38/+27
* config/tc-mips.c (reg_needs_delay): Move later in file. Use gpr_write_mask. (insns_between): Use gpr_read_mask instead of EXTRACT_OPERAND.
2013-07-26Add Intel AVX-512 supportH.J. Lu71-65/+124687
binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-25opcodes/Richard Sandiford2-4/+9
2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi> PR gas/15220 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps. gas/testsuite/ * gas/mips/loongson-2f.d: Fix expected output for madd.ps, msub.ps, nmadd.ps and nmsub.ps.
2013-07-25Support Intel SHAH.J. Lu9-0/+308
gas/ 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386.c (cpu_arch): Add .sha. * doc/c-i386.texi: Document sha/.sha. gas/testsuite/ 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/i386/sha.d: New. * gas/i386/sha.s: New. * gas/i386/x86-64-sha.d: New. * gas/i386/x86-64-sha.s: New. * gas/i386/i386.exp: Run new SHA tests. opcodes/ 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD, PREFIX_0F3ACC. (prefix_table): Updated. (three_byte_table): Likewise. * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS. (cpu_flags): Add CpuSHA. (i386_cpu_flags): Add cpusha. * i386-init.h: Regenerate. * i386-opc.h (CpuSHA): New. (CpuUnused): Restored. (i386_cpu_flags): Add cpusha. * i386-opc.tbl: Add SHA instructions. * i386-tbl.h: Regenerate.
2013-07-24Support Intel MPXH.J. Lu26-41/+1344
gas/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386.c (BND_PREFIX): New. (struct _i386_insn): Add new field bnd_prefix. (add_bnd_prefix): New. (cpu_arch): Add MPX. (i386_operand_type): Add regbnd. (md_assemble): Handle BND prefixes. (parse_insn): Likewise. (output_branch): Likewise. (output_jump): Likewise. (build_modrm_byte): Handle regbnd. (OPTION_MADD_BND_PREFIX): New. (md_longopts): Add entry for 'madd-bnd-prefix'. (md_parse_option): Handle madd-bnd-prefix option. (md_show_usage): Add description for madd-bnd-prefix option. * doc/c-i386.texi: Document mpx/.mpx and -madd-bnd-prefix. gas/testsuite/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/i386/mpx-add-bnd-prefix.s: New. * gas/i386/mpx-add-bnd-prefix.d: New. * gas/i386/mpx-inval-1.l: New. * gas/i386/mpx-inval-1.s: New. * gas/i386/mpx.d: New. * gas/i386/mpx.s: New. * gas/i386/x86-64-mpx-add-bnd-prefix.d: New. * gas/i386/x86-64-mpx-add-bnd-prefix.s: New. * gas/i386/x86-64-mpx-addr32.d: New. * gas/i386/x86-64-mpx-addr32.s: New. * gas/i386/x86-64-mpx-inval-1.l: New. * gas/i386/x86-64-mpx-inval-1.s: New. * gas/i386/x86-64-mpx-inval-2.l: New. * gas/i386/x86-64-mpx-inval-2.s: New. * gas/i386/x86-64-mpx.d: New. * gas/i386/x86-64-mpx.s: New. * gas/i386/nops.d: Adjust to MPX changes. * gas/i386/nops.s: Likewise. * gas/i386/x86-64-nops.d: Likewise. * gas/i386/x86-64-nops.s: Likewise. * gas/i386/ilp32/x86-64-nops.d: Likewise. * gas/i386/i386.exp: Run new MPX tests. include/opcode/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386.h (BND_PREFIX_OPCODE): New. opcodes/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis.c (BND_Fixup): New. (Ebnd): New. (Ev_bnd): New. (Gbnd): New. (BND): New. (v_bnd_mode): New. (bnd_mode): New. (MOD enum): Add new entries. (PREFIX enum): Likewise. (dis tables): Replace XX with BND for near branch and call instructions. (prefix_table): Add new entries. (mod_table): Likewise. (names_bnd): New. (intel_names_bnd): New. (att_names_bnd): New. (BND_PREFIX): New. (prefix_name): Handle BND_PREFIX. (print_insn): Initialize names_bnd. (intel_operand_size): Handle new modes. (OP_E_register): Likewise. (OP_E_memory): Likewise. (OP_G): Likewise. * i386-gen.c (cpu_flag_init): Add CpuMPX. (cpu_flags): Add CpuMPX. (operand_type_init): Add RegBND. (opcode_modifiers): Add BNDPrefixOk. (operand_types): Add RegBND. * i386-init.h: Regenerate. * i386-opc.h (CpuMPX): New. (CpuUnused): Comment out. (i386_cpu_flags): Add cpumpx. (BNDPrefixOk): New. (i386_opcode_modifier): Add bndprefixok. (RegBND): New. (i386_operand_type): Add regbnd. * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets. Add MPX instructions and bnd prefix. * i386-reg.tbl: Add bnd0-bnd3 registers. * i386-tbl.h: Regenerate.
2013-07-24bfd/Tristan Gingold11-2/+154
2013-07-24 Tristan Gingold <gingold@adacore.com> * coff-rs6000.c (xcoff_howto_table): Fix masks and pc_relative for R_RBR. Add numbers in comments. (_bfd_xcoff_reloc_type_lookup): Handle BFD_RELOC_PPC_B16. * coff64-rs6000.c: Likewise. gas/ 2013-07-24 Tristan Gingold <gingold@adacore.com> * config/tc-ppc.c (md_apply_fix): Adjust BFD_RELOC_PPC_B16 on xcoff targets. gas/testsuite/ 2013-07-24 Tristan Gingold <gingold@adacore.com> * gas/ppc/test2xcoff32.s, gas/ppc/test2xcoff32.d: New files * gas/ppc/ppc.exp: Add new test. * gas/ppc/xcoff-br16-1.s, gas/ppc/xcoff-br16-1.d, gas/ppc/xcoff-br16-2.s, gas/ppc/xcoff-br16-2.d: New files * gas/ppc/aix.exp: Add new tests.
2013-07-242013-07-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel2-4/+5
* config/tc-s390.c (s390_machine): Don't force the .machine argument to lower case.
2013-07-222013-07-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>Kyrylo Tkachov2-1/+6
* config/tc-arm.c (s_arm_arch_extension): Improve error message for invalid extension.
2013-07-19[AArch64, ILP32] Retire -milp32 and -mlp64; use -mabi=ilp32 and -mabi=lp64.Yufeng Zhang6-6/+77
gas/ * config/tc-aarch64.c (enum aarch64_abi_type): New enumeration tag. (AARCH64_ABI_LP64, AARCH64_ABI_ILP32): New enumerators. (aarch64_abi): New variable. (ilp32_p): Change to be a macro. (aarch64_opts): Remove the support for option -milp32 and -mlp64. (struct aarch64_option_abi_value_table): New struct. (aarch64_abis): New table. (aarch64_parse_abi): New function. (aarch64_long_opts): Add entry for -mabi=. * doc/as.texinfo (Target AArch64 options): Document -mabi. * doc/c-aarch64.texi: Likewise. gas/testsuite/ * gas/aarch64/ilp32-basic.d (#as): Update to use -mabi=ilp32
2013-07-18 * ar.c (usage): Fix C conformance issue.Nick Clifton2-1/+6
* config/tc-i386-intel.c (i386_intel_operand): Fixed signed vs unsigned comparison.
generated by cgit v1.1 at 2024-11-22 19:09:07 +0000