| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2013-07-26 | Add Intel AVX-512 support | H.J. Lu | 71 | -65/+124687 | |
| binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate. | |||||
| 2013-07-25 | opcodes/ | Richard Sandiford | 2 | -4/+9 | |
| 2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi> PR gas/15220 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps. gas/testsuite/ * gas/mips/loongson-2f.d: Fix expected output for madd.ps, msub.ps, nmadd.ps and nmsub.ps. | |||||
| 2013-07-25 | Support Intel SHA | H.J. Lu | 9 | -0/+308 | |
| gas/ 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386.c (cpu_arch): Add .sha. * doc/c-i386.texi: Document sha/.sha. gas/testsuite/ 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/i386/sha.d: New. * gas/i386/sha.s: New. * gas/i386/x86-64-sha.d: New. * gas/i386/x86-64-sha.s: New. * gas/i386/i386.exp: Run new SHA tests. opcodes/ 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD, PREFIX_0F3ACC. (prefix_table): Updated. (three_byte_table): Likewise. * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS. (cpu_flags): Add CpuSHA. (i386_cpu_flags): Add cpusha. * i386-init.h: Regenerate. * i386-opc.h (CpuSHA): New. (CpuUnused): Restored. (i386_cpu_flags): Add cpusha. * i386-opc.tbl: Add SHA instructions. * i386-tbl.h: Regenerate. | |||||
| 2013-07-24 | Support Intel MPX | H.J. Lu | 26 | -41/+1344 | |
| gas/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386.c (BND_PREFIX): New. (struct _i386_insn): Add new field bnd_prefix. (add_bnd_prefix): New. (cpu_arch): Add MPX. (i386_operand_type): Add regbnd. (md_assemble): Handle BND prefixes. (parse_insn): Likewise. (output_branch): Likewise. (output_jump): Likewise. (build_modrm_byte): Handle regbnd. (OPTION_MADD_BND_PREFIX): New. (md_longopts): Add entry for 'madd-bnd-prefix'. (md_parse_option): Handle madd-bnd-prefix option. (md_show_usage): Add description for madd-bnd-prefix option. * doc/c-i386.texi: Document mpx/.mpx and -madd-bnd-prefix. gas/testsuite/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/i386/mpx-add-bnd-prefix.s: New. * gas/i386/mpx-add-bnd-prefix.d: New. * gas/i386/mpx-inval-1.l: New. * gas/i386/mpx-inval-1.s: New. * gas/i386/mpx.d: New. * gas/i386/mpx.s: New. * gas/i386/x86-64-mpx-add-bnd-prefix.d: New. * gas/i386/x86-64-mpx-add-bnd-prefix.s: New. * gas/i386/x86-64-mpx-addr32.d: New. * gas/i386/x86-64-mpx-addr32.s: New. * gas/i386/x86-64-mpx-inval-1.l: New. * gas/i386/x86-64-mpx-inval-1.s: New. * gas/i386/x86-64-mpx-inval-2.l: New. * gas/i386/x86-64-mpx-inval-2.s: New. * gas/i386/x86-64-mpx.d: New. * gas/i386/x86-64-mpx.s: New. * gas/i386/nops.d: Adjust to MPX changes. * gas/i386/nops.s: Likewise. * gas/i386/x86-64-nops.d: Likewise. * gas/i386/x86-64-nops.s: Likewise. * gas/i386/ilp32/x86-64-nops.d: Likewise. * gas/i386/i386.exp: Run new MPX tests. include/opcode/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386.h (BND_PREFIX_OPCODE): New. opcodes/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis.c (BND_Fixup): New. (Ebnd): New. (Ev_bnd): New. (Gbnd): New. (BND): New. (v_bnd_mode): New. (bnd_mode): New. (MOD enum): Add new entries. (PREFIX enum): Likewise. (dis tables): Replace XX with BND for near branch and call instructions. (prefix_table): Add new entries. (mod_table): Likewise. (names_bnd): New. (intel_names_bnd): New. (att_names_bnd): New. (BND_PREFIX): New. (prefix_name): Handle BND_PREFIX. (print_insn): Initialize names_bnd. (intel_operand_size): Handle new modes. (OP_E_register): Likewise. (OP_E_memory): Likewise. (OP_G): Likewise. * i386-gen.c (cpu_flag_init): Add CpuMPX. (cpu_flags): Add CpuMPX. (operand_type_init): Add RegBND. (opcode_modifiers): Add BNDPrefixOk. (operand_types): Add RegBND. * i386-init.h: Regenerate. * i386-opc.h (CpuMPX): New. (CpuUnused): Comment out. (i386_cpu_flags): Add cpumpx. (BNDPrefixOk): New. (i386_opcode_modifier): Add bndprefixok. (RegBND): New. (i386_operand_type): Add regbnd. * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets. Add MPX instructions and bnd prefix. * i386-reg.tbl: Add bnd0-bnd3 registers. * i386-tbl.h: Regenerate. | |||||
| 2013-07-24 | bfd/ | Tristan Gingold | 11 | -2/+154 | |
| 2013-07-24 Tristan Gingold <gingold@adacore.com> * coff-rs6000.c (xcoff_howto_table): Fix masks and pc_relative for R_RBR. Add numbers in comments. (_bfd_xcoff_reloc_type_lookup): Handle BFD_RELOC_PPC_B16. * coff64-rs6000.c: Likewise. gas/ 2013-07-24 Tristan Gingold <gingold@adacore.com> * config/tc-ppc.c (md_apply_fix): Adjust BFD_RELOC_PPC_B16 on xcoff targets. gas/testsuite/ 2013-07-24 Tristan Gingold <gingold@adacore.com> * gas/ppc/test2xcoff32.s, gas/ppc/test2xcoff32.d: New files * gas/ppc/ppc.exp: Add new test. * gas/ppc/xcoff-br16-1.s, gas/ppc/xcoff-br16-1.d, gas/ppc/xcoff-br16-2.s, gas/ppc/xcoff-br16-2.d: New files * gas/ppc/aix.exp: Add new tests. | |||||
| 2013-07-24 | 2013-07-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> | Andreas Krebbel | 2 | -4/+5 | |
| * config/tc-s390.c (s390_machine): Don't force the .machine argument to lower case. | |||||
| 2013-07-22 | 2013-07-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com> | Kyrylo Tkachov | 2 | -1/+6 | |
| * config/tc-arm.c (s_arm_arch_extension): Improve error message for invalid extension. | |||||
| 2013-07-19 | [AArch64, ILP32] Retire -milp32 and -mlp64; use -mabi=ilp32 and -mabi=lp64. | Yufeng Zhang | 6 | -6/+77 | |
| gas/ * config/tc-aarch64.c (enum aarch64_abi_type): New enumeration tag. (AARCH64_ABI_LP64, AARCH64_ABI_ILP32): New enumerators. (aarch64_abi): New variable. (ilp32_p): Change to be a macro. (aarch64_opts): Remove the support for option -milp32 and -mlp64. (struct aarch64_option_abi_value_table): New struct. (aarch64_abis): New table. (aarch64_parse_abi): New function. (aarch64_long_opts): Add entry for -mabi=. * doc/as.texinfo (Target AArch64 options): Document -mabi. * doc/c-aarch64.texi: Likewise. gas/testsuite/ * gas/aarch64/ilp32-basic.d (#as): Update to use -mabi=ilp32 | |||||
| 2013-07-18 | * ar.c (usage): Fix C conformance issue. | Nick Clifton | 2 | -1/+6 | |
| * config/tc-i386-intel.c (i386_intel_operand): Fixed signed vs unsigned comparison. | |||||
| 2013-07-18 | * config/rx-defs.h: Add macros for RX100, RX200, RX600, and | Nick Clifton | 5 | -14/+66 | |
| RX610. * config/rx-parse.y: (rx_check_float_support): Add function to check floating point operation support for target RX100 and RX200. * config/tc-rx.c: Add CPU options RX100, RX200, RX600, and RX610. * doc/c-rx.texi: Add -mcpu option to recognize macros for RX100, RX200, RX600, and RX610 | |||||
| 2013-07-18 | * config/tc-avr.c (md_show_usage): Add avrxmega2 to help text | Nick Clifton | 2 | -0/+5 | |
| 2013-07-18 | * config/tc-avr.c: Make ata6289's ISA to AVR_ISA_AVR4. | Nick Clifton | 3 | -3/+8 | |
| * doc/c-avr.texi: Likewise. | |||||
| 2013-07-15 | gas/ | Richard Sandiford | 2 | -2/+8 | |
| * config/tc-mips.c (match_save_restore_list_operand): Avoid -Wformat error with older GCCs. (mips16_macro_build): Dereference args. | |||||
| 2013-07-14 | gas/ | Richard Sandiford | 8 | -465/+779 | |
| * config/tc-mips.c (mips_prefer_vec_regno, mips_parse_register): New functions, split out from... (reg_lookup): ...here. Remove itbl support. (reglist_lookup): Delete. (mips_operand_token_type): New enum. (mips_operand_token): New structure. (mips_operand_tokens): New variable. (mips_add_token, mips_parse_base_start, mips_parse_argument_token) (mips_parse_arguments): New functions. (md_begin): Initialize mips_operand_tokens. (mips_arg_info): Add a token field. Remove optional_reg field. (match_char, match_expression): New functions. (match_const_int): Use match_expression. Remove "s" argument and return a boolean result. Remove O_register handling. (match_regno, match_reg, match_reg_range): New functions. (match_int_operand, match_mapped_int_operand, match_msb_operand) (match_reg_operand, match_reg_pair_operand, match_perf_reg_operand) (match_addiusp_operand, match_clo_clz_dest_operand) (match_lwm_swm_list_operand, match_entry_exit_operand) (match_save_restore_list_operand, match_mdmx_imm_reg_operand) (match_tied_reg_operand): Remove "s" argument and return a boolean result. Match tokens rather than text. Update calls to match_const_int. Rely on match_regno to call check_regno. (match_pcrel_operand, match_pc_operand): Replace "s" argument with "arg" argument. Return a boolean result. (parse_float_constant): Replace with... (match_float_constant): ...this new function. (match_operand): Remove "s" argument and return a boolean result. Update calls to subfunctions. (mips_ip, mips16_ip): Call mips_parse_arguments. Use match routines rather than string-parsing routines. Update handling of optional registers for token scheme. gas/testsuite/ * gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: Add some more cases. * gas/mips/micromips-ill.s, gas/mips/micromips-ill.l: New test. * gas/mips/mips.exp: Run it. | |||||
| 2013-07-14 | gas/ | Richard Sandiford | 2 | -163/+176 | |
| * config/tc-mips.c (parse_float_constant): Split out from... (mips_ip): ...here. | |||||
| 2013-07-14 | gas/ | Richard Sandiford | 2 | -25/+5 | |
| * config/tc-mips.c (INSERT_BITS, INSERT_OPERAND, MIPS16_INSERT_OPERAND): Delete. | |||||
| 2013-07-14 | gas/ | Richard Sandiford | 2 | -541/+373 | |
| * config/tc-mips.c (mips32_to_16_reg_map): Delete. (match_entry_exit_operand): New function. (match_save_restore_list_operand): Likewise. (match_operand): Use them. (check_absolute_expr): Delete. (mips16_ip): Rewrite main parsing loop to use mips_operands. | |||||
| 2013-07-14 | gas/ | Richard Sandiford | 11 | -2435/+330 | |
| * config/tc-mips.c: Enable functions commented out in previous patch. (SKIP_SPACE_TABS): Move further up file. (mips32_to_micromips_reg_b_map, mips32_to_micromips_reg_c_map) (mips32_to_micromips_reg_d_map, mips32_to_micromips_reg_e_map) (ips32_to_micromips_reg_f_map, mips32_to_micromips_reg_g_map) (mips32_to_micromips_reg_l_map, mips32_to_micromips_reg_m_map) (mips32_to_micromips_reg_q_map, mips32_to_micromips_reg_n_map) (micromips_imm_b_map, micromips_imm_c_map): Delete. (mips_lookup_reg_pair): Delete. (macro): Use report_bad_range and report_bad_field. (mips_immed, expr_const_in_range): Delete. (mips_ip): Rewrite main parsing loop to use new functions. gas/testsuite/ * gas/mips/at-2.l: Remove duplicated $at warnings. * gas/mips/ext-ill.l, gas/mips/lui-1.l, gas/mips/mips32r2-ill.l, gas/mips/mips32r2-ill-nofp.l, gas/mips/mips32r2-ill-fp64.l, gas/mips/mips64r2-ill.l, gas/mips/octeon-ill.l: Update error messages. Expect negative numbers to be printed as such, rather than as large unsigned positive numbers. | |||||
| 2013-07-14 | gas/ | Richard Sandiford | 2 | -40/+855 | |
| * config/tc-mips.c (mips_oddfpreg_ok): Move further up file. Change return type to bfd_boolean. (report_bad_range, report_bad_field): New functions. (mips_arg_info): New structure. (match_const_int, convert_reg_type, check_regno, match_int_operand) (match_mapped_int_operand, match_msb_operand, match_reg_operand) (match_reg_pair_operand, match_pcrel_operand, match_perf_reg_operand) (match_addiusp_operand, match_clo_clz_dest_operand) (match_lwm_swm_list_operand, match_mdmx_imm_reg_operand) (match_pc_operand, match_tied_reg_operand, match_operand) (check_completed_insn): New functions, commented out for now. | |||||
| 2013-07-14 | gas/ | Richard Sandiford | 2 | -237/+52 | |
| * config/tc-mips.c (insn_insert_operand): New function. (macro_build, mips16_macro_build): Put null character check in the for loop and convert continues to breaks. Use operand structures to handle constant operands. | |||||
| 2013-07-14 | include/opcode/ | Richard Sandiford | 2 | -348/+116 | |
| * mips.h (mips_operand_type, mips_reg_operand_type): New enums. (mips_operand, mips_int_operand, mips_mapped_int_operand) (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand) (mips_pcrel_operand): New structures. (mips_insert_operand, mips_extract_operand, mips_signed_operand) (mips_decode_int_operand, mips_decode_pcrel_operand): New functions. (decode_mips_operand, decode_micromips_operand): Declare. opcodes/ * mips-formats.h: New file. * mips-opc.c: Include mips-formats.h. (reg_0_map): New static array. (decode_mips_operand): New function. * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h. (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map) (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map) (int_c_map): New static arrays. (decode_micromips_operand): New function. * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map) (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map) (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map) (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2) (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map) (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map) (micromips_imm_b_map, micromips_imm_c_map): Delete. (print_reg): New function. (mips_print_arg_state): New structure. (init_print_arg_state, print_insn_arg): New functions. (print_insn_args): Change interface and use mips_operand structures. Delete GET_OP_S. Move GET_OP definition to... (print_insn_mips): ...here. Update the call to print_insn_args. (print_insn_micromips): Use print_insn_args. gas/ * config/tc-mips.c (validate_mips_insn): Move further up file. Add insn_bits and decode_operand arguments. Use the mips_operand fields to work out which bits an operand occupies. Detect double definitions. (validate_micromips_insn): Move further up file. Call into validate_mips_insn. | |||||
| 2013-07-14 | gas/ | Richard Sandiford | 2 | -10/+4 | |
| * config/tc-mips.c (mips16_macro_build): Remove 'Y' case. | |||||
| 2013-07-14 | gas/ | Richard Sandiford | 2 | -28/+21 | |
| * config/tc-mips.c (macro_build): Take an int for "C", "k", "\\" and "~". (macro): Update accordingly. | |||||
| 2013-07-14 | gas/ | Richard Sandiford | 2 | -74/+83 | |
| * config/tc-mips.c (imm_expr, imm2_expr, offset_expr): Tweak commentary. (imm_reloc): Delete. (md_assemble): Remove imm_reloc handling. (mips_ip): Update commentary. Use offset_expr and offset_reloc rather than imm_expr and imm_reloc for 'i', 'j' and 'u'. Use a temporary array rather than imm_reloc when parsing constant expressions. Remove imm_reloc initialization. (mips16_ip): Update commentary. Use offset_expr and offset_reloc for the relaxable field. Use a relax_char variable to track the type of this field. Remove imm_reloc initialization. | |||||
| 2013-07-14 | include/opcode/ | Richard Sandiford | 2 | -0/+14 | |
| * mips.h: Document MIPS16 "I" opcode. opcodes/ * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands in macros. gas/ * config/tc-mips.c (mips16_ip): Handle "I". | |||||
| 2013-07-12 | include/elf/ | Maciej W. Rozycki | 23 | -2/+238 | |
| * mips.h (EF_MIPS_NAN2008): New macro. bfd/ * elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Handle EF_MIPS_NAN2008. (_bfd_mips_elf_print_private_bfd_data): Likewise. binutils/ * readelf.c (get_machine_flags): Handle EF_MIPS_NAN2008. gas/ * config/tc-mips.c (mips_flag_nan2008): New variable. (options): Add OPTION_NAN enum value. (md_longopts): Handle it. (md_parse_option): Likewise. (s_nan): New function. (mips_elf_final_processing): Handle EF_MIPS_NAN2008. (md_show_usage): Add -mnan. * doc/as.texinfo (Overview): Add -mnan. * doc/c-mips.texi (MIPS Opts): Document -mnan. (MIPS NaN Encodings): New node. Document .nan directive. (MIPS-Dependent): List the new node. gas/testsuite/ * gas/mips/nan-2008-1.d: New test. * gas/mips/nan-2008-2.d: New test. * gas/mips/nan-2008-3.d: New test. * gas/mips/nan-2008-4.d: New test. * gas/mips/nan-legacy-1.d: New test. * gas/mips/nan-legacy-2.d: New test. * gas/mips/nan-legacy-3.d: New test. * gas/mips/nan-legacy-4.d: New test. * gas/mips/nan-legacy-5.d: New test. * gas/mips/nan-error-1.l: New list test. * gas/mips/nan-error-2.l: New list test. * gas/mips/nan-2008-override.s: New test source. * gas/mips/nan-2008.s: New test source. * gas/mips/nan-legacy-override.s: New test source. * gas/mips/nan-legacy.s: New test source. * gas/mips/nan-error-1.s: New test source. * gas/mips/nan-error-2.s: New test source. * gas/mips/mips.exp: Run the new tests. ld/testsuite/ * ld-mips-elf/nan-2008.d: New test. * ld-mips-elf/nan-legacy.d: New test. * ld-mips-elf/nan-mixed-1.d: New test. * ld-mips-elf/nan-mixed-2.d: New test. * ld-mips-elf/nan-2008.s: New test source. * ld-mips-elf/nan-legacy.s: New test source. | |||||
| 2013-07-09 | gas/testsuite/ | Richard Sandiford | 5 | -0/+101 | |
| * gas/mips/la-reloc.s, gas/mips/la-reloc.d, gas/mips/dla-reloc.s, gas/mips/dla-reloc.d: Add files missing from earlier commit. | |||||
| 2013-07-09 | binutils/ | Tristan Gingold | 2 | -2/+6 | |
| 2013-07-09 Tristan Gingold <gingold@adacore.com> * configure.com: Add new defines to match changes in configure. gas/ 2013-07-09 Tristan Gingold <gingold@adacore.com> * configure.com: Define HAVE_SYS_TYPES_H and HAVE_UNISTD_H | |||||
| 2013-07-08 | Replace Xmmword with Qword on cvttps2pi | H.J. Lu | 4 | -0/+10 | |
| gas/testsuite/ PR gas/13572 * gas/i386/simd.s: Add a test for cvttps2pi. * gas/i386/simd-intel.d: Updated. * gas/i386/simd.d: Likewise. opcodes/ PR gas/13572 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi. * i386-tbl.h: Regenerated. | |||||
| 2013-07-08 | gas/ | Richard Sandiford | 7 | -5/+66 | |
| * config/tc-mips.c (mips_ip): Unconditionally parse an expression for 'A' and assume that the constant has been elided if the result is an O_register. gas/testsuite/ * gas/mips/la.s, gas/mips/la.d, gas/mips/la-svr4pic.d, gas/mips/la-xgot.d: Add tests for bracketed addresses. | |||||
| 2013-07-07 | include/opcode/ | Richard Sandiford | 26 | -3723/+3468 | |
| * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB) (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB) (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A) (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB) (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB) (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB) (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB) (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB) (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A) (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A) (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB) (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete. (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A): Rename to... (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB) (M_USD_AB): ...these. opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD and SD A(B) macros up. * micromips-opc.c (micromips_opcodes): Likewise. gas/ * config/tc-mips.c (gprel16_reloc_p): New function. (macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are BFD_RELOC_UNUSED. (offset_high_part, small_offset_p): New functions. (nacro): Use them. Remove *_OB and *_DOB cases. For single- register load and store macros, handle the 16-bit offset case first. If a 16-bit offset is not suitable for the instruction we're generating, load it into the temporary register using ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the M_L_DAB code once the address has been constructed. For double load and store macros, again handle the 16-bit offset case first. If the second register cannot be accessed from the same high part as the first, load it into AT using ADDRESS_ADDI_INSN. Fix the handling of LD in cases where the first register is the same as the base. Also handle the case where the offset is not 16 bits and the second register cannot be accessed from the same high part as the first. For unaligned loads and stores, fuse the offbits == 12 and old "ab" handling. Apply this handling whenever the second offset needs a different high part from the first. Construct the offset using ADDRESS_ADDI_INSN where possible, for offbits == 16 as well as offbits == 12. Use offset_reloc when constructing the individual loads and stores. (mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc and offset_reloc before matching against a particular opcode. Handle elided 'A' constants. Allow 'A' constants to use relocation operators. gas/testsuite/ * gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for truncated constants. * gas/mips/ldstla-32-shared.d: Likewise. * gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding 16-bit constants to the base. * gas/mips/micromips@mcu.d: Likewise. * gas/mips/micromips@cache.d: Likewise. * gas/mips/micromips@pref.d: Likewise. * gas/mips/micromips.d, gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise. Allow the full 16-bit offset range to be used for SB, LB and LBU in USH and ULH sequences. Fix the expected output for LD and SD when the two LW and SW offsets need different high parts. * gas/mips/eva.s: Test PREFE with relocation operators. * gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit constants. Update after eva.s change. * gas/mips/micromips@eva.d: Likewise. * gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s, gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d, gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s, gas/mips/ulh-reloc.d: New tests. * gas/mips/mips.exp: Run them. | |||||
| 2013-07-07 | gas/testsuite/ | Richard Sandiford | 3 | -2868/+2879 | |
| * gas/mips/eva.d, gas/mips/micromips@eva.d: Remove hard-coded addresses. Use gpr-names=numeric. | |||||
| 2013-07-07 | opcodes/ | Richard Sandiford | 3 | -4/+9 | |
| * mips16-opc.c: Add entries for argumentless "entry" and "exit" instructions. gas/testsuite/ * gas/mips/mips16.d, gas/mips/mips16-64.d: Remove trailing whitespace from ENTRY and EXIT lines. | |||||
| 2013-07-07 | include/opcode/ | Richard Sandiford | 6 | -11/+61 | |
| * mips.h: Remove documentation of "[" and "]". Update documentation of "k" and the MDMX formats. opcodes/ * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400 MDMX-like instructions. * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when printing "Q" operands for INSN_5400 instructions. gas/ * config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling. (mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions. Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions. gas/testsuite/ * gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: New test. * gas/mips/mips.exp: Run it. | |||||
| 2013-07-07 | include/opcode/ | Richard Sandiford | 2 | -7/+12 | |
| * mips.h: Update documentation of "+s" and "+S". opcodes/ * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and "+S" for "cins". * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments. Combine cases. gas/ * config/tc-mips.c (mips_ip): Preserve the real bit number for "+p". Require the msb to be <= 31 for "+s". Check that the size is <= 31 for both "+s" and "+S". | |||||
| 2013-07-07 | include/opcode/ | Richard Sandiford | 2 | -0/+12 | |
| * mips.h: Document "+i". opcodes/ * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for "jalx". * mips16-opc.c (mips16_opcodes): Likewise. * micromips-opc.c (micromips_opcodes): Likewise. * mips-dis.c (print_insn_args, print_mips16_insn_arg) (print_insn_mips16): Handle "+i". (print_insn_micromips): Likewise. Conditionally preserve the ISA bit for "a" but not for "+i". gas/ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn): (mips_ip, mips16_ip): Handle "+i". | |||||
| 2013-07-07 | include/opcode/ | Richard Sandiford | 2 | -64/+57 | |
| * mips.h: Remove "mi" documentation. Update "mh" documentation. (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI): Delete. (INSN2_WRITE_GPR_MHI): Rename to... (INSN2_WRITE_GPR_MH): ...this. opcodes/ * micromips-opc.c (WR_mhi): Rename to.. (WR_mh): ...this. (micromips_opcodes): Update "movep" entry accordingly. Replace "mh,mi" with "mh". * mips-dis.c (micromips_to_32_reg_h_map): Rename to... (micromips_to_32_reg_h_map1): ...this. (micromips_to_32_reg_i_map): Rename to... (micromips_to_32_reg_h_map2): ...this. (print_micromips_insn): Remove "mi" case. Print both registers in the pair for "mh". gas/ * config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete. (micromips_to_32_reg_h_map): Rename to... (micromips_to_32_reg_h_map1): ...this. (micromips_to_32_reg_i_map): Rename to... (micromips_to_32_reg_h_map2): ...this. (mips_lookup_reg_pair): New function. (gpr_write_mask, macro): Adjust after above renaming. (validate_micromips_insn): Remove "mi" handling. (mips_ip): Likewise. Parse both registers in a pair for "mh". | |||||
| 2013-07-07 | include/opcode/ | Richard Sandiford | 5 | -16/+12 | |
| * mips.h: Remove documentation of "+D" and "+T". opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries. * micromips-opc.c (micromips_opcodes): Likewise. * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D" and "+T" handling. Check for a "0" suffix when deciding whether to use coprocessor 0 names. In that case, also check for ",H" selectors. gas/ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn) (mips_ip): Remove "+D" and "+T" handling. gas/testsuite/ * gas/mips/lb.d, gas/mips/sb.d: Use coprocessor register names for LWC0 and SWC0. | |||||
| 2013-07-05 | 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> | Andreas Krebbel | 5 | -6/+74 | |
| opcodes/ * s390-opc.c (J12_12, J24_24): New macros. (INSTR_MII_UPI): Rename to INSTR_MII_UPP. (MASK_MII_UPI): Rename to MASK_MII_UPP. * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction. include/elf/ * s390.h: Add new relocs R_390_PC12DBL, R_390_PLT12DBL, R_390_PC24DBL, and R_390_PLT24DBL. gas/testsuite/ * gas/s390/zarch-zEC12.s: Change bprp second operand and add variants requiring relocations. * gas/s390/zarch-zEC12.d: Likewise. gas/ * config/tc-s390.c (md_gather_operands, md_apply_fix): Support new relocs. bfd/ * elf32-s390.c: Add new relocation definitions R_390_PC12DBL, R_390_PLT12DBL, R_390_PC24DBL, and R_390_PLT24DBL. (elf_s390_reloc_type_lookup, elf_s390_check_relocs) (elf_s390_gc_sweep_hook, elf_s390_relocate_section): Support new relocations. * elf64-s390.c: See elf32-s390.c * bfd-in2.h: Add new relocs to enum bfd_reloc_code_real. * libbfd.h: Add new reloc strings. | |||||
| 2013-07-03 | [PATCH, COMMITTED] [AArch64] Replace the :got_prel19: address modifier with ↵ | Marcus Shawcroft | 4 | -8/+12 | |
| :got: | |||||
| 2013-07-03 | [AArch64] Tidy up switch statement in GAS. | Marcus Shawcroft | 2 | -32/+37 | |
| 2013-07-02 | bfd/ | Alan Modra | 2 | -2/+4 | |
| * elf64-ppc.c (ppc64_elf_relocate_section): Set "relocation" for .TOC. after relocatable check. gas/ * config/tc-ppc.c (ppc_elf_adjust_symtab): Don't make .TOC. weak. | |||||
| 2013-06-26 | * doc/as.texinfo (Overview): Remove @samp from MIPS ISA names. | Maciej W. Rozycki | 3 | -16/+17 | |
| * doc/c-mips.texi (MIPS Options): Remove @sc from MIPS ISA names. Replace @sc{mips16} with literal `MIPS16'. (MIPS ISA): Replace @sc{mips3} with literal `MIPS III'. | |||||
| 2013-06-26 | [AArch64, ILP32] 3/6 Support for ELF32 relocs and refactor reloc handling | Yufeng Zhang | 5 | -3/+108 | |
| bfd/ * bfd-in2.h: Re-generated. * elfnn-aarch64.c (HOWTO64, HOWTO32): New define. (IS_AARCH64_TLS_RELOC): Change to be based on the bfd reloc enumerators. (IS_AARCH64_TLSDESC_RELOC): Likewise. (PG, PG_OFFSET): Cast literal to bfd_vma. (elf64_aarch64_howto_table): Removed. (elf64_aarch64_howto_dynrelocs): Removed. (elf64_aarch64_tls_howto_table): Removed. (elf64_aarch64_tlsdesc_howto_table): Removed. (elfNN_aarch64_howto_table): New table to host all howto entires.. (R_AARCH64_*): Replaced by AARCH64_R (*) and AARCH64_R_STR (*). (elfNN_aarch64_bfd_reloc_from_howto): New function. (elfNN_aarch64_bfd_reloc_from_type): Ditto. (struct elf_aarch64_reloc_map): New. (elf_aarch64_reloc_map): New table. (elfNN_aarch64_howto_from_bfd_reloc): New function. (elfNN_aarch64_howto_from_type): Update to look up the new table elfNN_aarch64_howto_table. (struct elf64_aarch64_reloc_map): Remove. (elf64_aarch64_reloc_map): Remove. (elfNN_aarch64_reloc_type_lookup): Change to call elfNN_aarch64_howto_from_bfd_reloc. (elfNN_aarch64_reloc_name_lookup): Change to look up the new table elfNN_aarch64_howto_table. (aarch64_resolve_relocation): Refactor to switch on the bfd reloc enumerators. (bfd_elf_aarch64_put_addend): Likewise. (elfNN_aarch64_final_link_relocate): Likewise. (aarch64_tls_transition_without_check): Likewise. (aarch64_reloc_got_type): Likewise. (aarch64_can_relax_tls): Likewise. (aarch64_tls_transition): Likewise. (elfNN_aarch64_tls_relax): Likewise. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_relocate_section): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. (aarch64_tls_transition): Change to return a bfd reloc enumerator. * libbfd.h: Re-generated. * reloc.c: Re-order the AArch64 bfd reloc enumerators. (BFD_RELOC_AARCH64_RELOC_START) (BFD_RELOC_AARCH64_RELOC_END) (BFD_RELOC_AARCH64_LD_GOT_LO12_NC) (BFD_RELOC_AARCH64_LD32_GOT_LO12_NC) (BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC) (BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC) (BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC) (BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC) (BFD_RELOC_AARCH64_IRELATIVE): New relocs. gas/ * config/tc-aarch64.c (reloc_table): Replace BFD_RELOC_AARCH64_LD64_GOT_LO12_NC with BFD_RELOC_AARCH64_LD_GOT_LO12_NC; likewise to BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC and BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC. (md_apply_fix): Handle BFD_RELOC_AARCH64_LD_GOT_LO12_NC, BFD_RELOC_AARCH64_LD32_GOT_LO12_NC, BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC, BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC, BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC and BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC. (aarch64_force_relocation): Likewise. gas/testsuite/ * gas/aarch64/ilp32-basic.d: New file. * gas/aarch64/ilp32-basic.s: New file. include/elf/ * aarch64.h: Add ELF32 reloc codes and remove fake ELF64 ones. (R_AARCH64_IRELATIVE): New reloc. | |||||
| 2013-06-26 | [AArch64, ILP32] 2/6 Parametrize elfnn-aarch64.c and add basic support in ld | Yufeng Zhang | 3 | -3/+39 | |
| and gas. bfd/ * Makefile.am (BFD64_BACKENDS): Add elf32-aarch64.lo. (BUILD_CFILES): Add elf32-aarch64.c. (elf32-aarch64.c): New rule for generating from elfnn-aarch64.c. * Makefile.in: Re-generated. * archures.c (bfd_mach_aarch64_ilp32): New define. * bfd-in.h (bfd_elf32_aarch64_init_maps): New declaration. (bfd_elf32_aarch64_set_options): Ditto. (elf32_aarch64_setup_section_lists): Ditto. (elf32_aarch64_next_input_section): Ditto. (elf32_aarch64_size_stubs): Ditto. (elf32_aarch64_build_stubs): Ditto. * bfd-in2.h: Re-generated. * config.bfd (aarch64-*-elf): Add bfd_elf32_littleaarch64_vec and bfd_elf32_bigaarch64_vec. (aarch64-*-linux*): Likewise. (aarch64_be-*-elf): Likewise. (aarch64_be-*-linux*): Likewise. * configure.in (bfd_elf32_bigaarch64_vec) (bfd_elf32_littleaarch64_vec): New. * configure: Re-generated. * cpu-aarch64.c (compatible): Don't allow mixing ilp32 objects with lp64 ones. (bfd_aarch64_arch_ilp32): New. (bfd_aarch64_arch): Link to bfd_aarch64_arch_ilp32. * elfnn-aarch64.c (ARCH_SIZE): New define. (AARCH64_R, AARCH64_R_STR, LOG_FILE_ALIGN): New defines. (GOT_ENTRY_SIZE): Re-define as (ARCH_SIZE / 8). (elf64_aarch64_*): Rename to elfNN_aarch64_*. (ELF64_R_*): Rename to ELFNN_R_*. Plus other paramaterization. * targets.c (bfd_elf32_bigaarch64_vec, bfd_elf32_littleaarch64_vec): New declarations. (_bfd_target_vector): Add bfd_elf32_bigaarch64_vec and bfd_elf32_littleaarch64_vec. gas/ * config/tc-aarch64.c (ilp32_p): New static variable. (elf64_aarch64_target_format): Return the target according to the value of 'ilp32_p'. (md_begin): Determine 'mach' according to the value of 'ilp32_p'. (aarch64_opts): Add support for options '-milp32' and '-mlp64'. (aarch64_dwarf2_addr_size): New function. * config/tc-aarch64.h (aarch64_dwarf2_addr_size): New declaration. (DWARF2_ADDR_SIZE): New define. ld/ * Makefile.am (ALL_64_EMULATION_SOURCES): Add eaarch64elf32.c. (eaarch64elf32.c): New dependency and rule. * Makefile.in: Re-generated. * configure.tgt (aarch64-*-elf): Add aarch64elf32. (aarch64_be-*-elf, aarch64_be-*-linux*, aarch64-*-linux*): Likewise. * emulparams/aarch64elf32.sh: New file. | |||||
| 2013-06-26 | gas/ | Richard Sandiford | 2 | -3/+7 | |
| * doc/c-mips.texi: Use ISA instead of @sc{isa}. | |||||
| 2013-06-26 | include/opcode/ | Richard Sandiford | 2 | -1/+5 | |
| * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT. Use "source" rather than "destination" for microMIPS "G". gas/ * config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT. | |||||
| 2013-06-25 | bfd/ | Maciej W. Rozycki | 13 | -46/+16074 | |
| * elfxx-mips.h (_bfd_mips_elf_insn32): New prototype. * elfxx-mips.c (mips_elf_link_hash_table): Add insn32 member. (STUB_MOVE32_MICROMIPS, STUB_JALR32_MICROMIPS): New macros. (MICROMIPS_INSN32_FUNCTION_STUB_NORMAL_SIZE): Likewise. (MICROMIPS_INSN32_FUNCTION_STUB_BIG_SIZE): Likewise. (micromips_insn32_o32_exec_plt0_entry): New variable. (micromips_insn32_o32_exec_plt_entry): Likewise. (_bfd_mips_elf_adjust_dynamic_symbol): Handle insn32 mode. (mips_elf_estimate_stub_size): Likewise. (_bfd_mips_elf_size_dynamic_sections): Likewise. (_bfd_mips_elf_finish_dynamic_symbol): Likewise. (mips_finish_exec_plt): Likewise. (_bfd_mips_elf_relax_section): Likewise. (_bfd_mips_elf_insn32): New function. (_bfd_mips_elf_get_synthetic_symtab): Handle insn32 PLT. gas/ * config/tc-mips.c (mips_set_options): Add insn32 member. (mips_opts): Initialize it. (NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode. (options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values. (md_longopts): Add "minsn32" and "mno-insn32" options. (is_size_valid): Handle insn32 mode. (md_assemble): Pass instruction string down to macro. (brk_fmt): Add second dimension and insn32 mode initializers. (mfhl_fmt): Likewise. (BRK_FMT, MFHL_FMT): Handle insn32 mode. (macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding. (macro_build_jalr, move_register): Handle insn32 mode. (macro_build_branch_rs): Likewise. (macro): Handle insn32 mode. <M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases. (mips_ip): Handle insn32 mode. (md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32. (s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops. (mips_handle_align): Handle insn32 mode. (md_show_usage): Add -minsn32 and -mno-insn32. * doc/as.texinfo (Target MIPS options): Add -minsn32 and -mno-insn32 options. (-minsn32, -mno-insn32): New options. * doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32 options. (MIPS assembly options): New node. Document .set insn32 and .set noinsn32. (MIPS-Dependent): List the new node. gas/testsuite/ * gas/mips/micromips-insn32.d: New test. * gas/mips/micromips-noinsn32.d: Likewise. * gas/mips/micromips.l: Rename to... * gas/mips/micromips-warn.l: ... this. * gas/mips/micromips.d: Update accordingly. * gas/mips/micromips-trap.d: Likewise. * gas/mips/micromips.l: New list test. * gas/mips/micromips.s: Add conditionals. * gas/mips/mips.exp: Run the new tests. include/opcode/ * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum values. ld/ * emultempl/mipself.em (insn32): New variable. (mips_create_output_section_statements): Handle insn32 mode. (PARSE_AND_LIST_PROLOGUE): New macro. (PARSE_AND_LIST_LONGOPTS): Likewise. (PARSE_AND_LIST_OPTIONS): Likewise. * gen-doc.texi: Set MIPS. * ld.texinfo: Likewise. (Options specific to MIPS targets): New section. (ld and MIPS family): New node. (Top, Machine Dependent): List the new node. opcodes/ * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc" and "movep" macros. | |||||
| 2013-06-25 | * config/tc-msp430.c (msp430_srcoperand): Do not allow the use of | Nick Clifton | 2 | -11/+21 | |
| the PC in indirect addressing on 430xv2 parts. (msp430_operands): Add version test to hardware bug encoding restrictions. | |||||
| 2013-06-24 | gas/ | Roland McGrath | 5 | -5/+12 | |
| * config/tc-arm.c (parse_reg_list): Use skip_past_char for '}', so it skips whitespace before it. (s_arm_unwind_save_mmxwr, s_arm_unwind_save_mmxwcg): Likewise. gas/testsuite/ * gas/arm/macro-vld1.s: Add a case with whitespace before '}'. * gas/arm/macro-vld1.d: Update. | |||||
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