Age | Commit message (Collapse) | Author | Files | Lines |
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* config/tc-mips.c (macro): Fix unsupported opcode message
capitalization.
(mips_ip, mips16_ip): Likewise.
gas/testsuite/
* gas/mips/mips-double-float-flag.l: Adjust according to
unsupported opcode message capitalization fix.
* gas/mips/mips-hard-float-flag.l: Likewise.
* gas/mips/mips-macro-ill-nofp.l: Likewise.
* gas/mips/mips-macro-ill-sfp.l: Likewise.
* gas/mips/mips1-fp.l: Likewise.
* gas/mips/mips16e-64.l: Likewise.
* gas/mips/mips32-sf32.l: Likewise.
* gas/mips/mips32r2-fp32.l: Likewise.
* gas/mips/mips4-branch-likely.l: Likewise.
* gas/mips/mips4-fp.l: Likewise.
* gas/mips/octeon-ill.l: Likewise.
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mode.
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conditional.
(mips_ip): Likewise.
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"m14kec".
* doc/c-mips.texi (MIPS architecture options): Add "m14ke" and
"m14kec" to the list of -march options.
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that have an in-place addend narrower than the addresses used.
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* config/tc-mips.c (can_swap_branch_p): Exclude microMIPS
variant frags too.
gas/testsuite/
* gas/mips/relax-swap3.d: New test.
* gas/mips/mips16@relax-swap3.d: Likewise.
* gas/mips/micromips@relax-swap3.d: Likewise.
* gas/mips/relax-swap3.s: New test source.
* gas/mips/mips.exp: Run the new tests.
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* gas/doc/c-arm.texi (ARM Options): Add cortex-a7 to list of accepted
CPUs.
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* elf32-rl78.c (rl78_elf_merge_private_bfd_data): Delete unused
variable.
[gas]
* config/tc-rl78.c (tc_gen_reloc): Remove unused variable.
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with the (PLT) instruction suffix when operating in eabi mode.
* doc/c-arm.texi (ARM_Relocations): Extend description of (PLT)
suffix.
* gas/arm/pic.d: Update expected output.
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* configure.ac (rl78-*-*) New case.
* configure: Regenerate.
[bfd]
* Makefile.am (ALL_MACHINES): Add cpu-rl78.lo.
(ALL_MACHINES_CFILES): Add cpu-rl78.c.
(BFD32_BACKENDS): Add elf32-rl78.lo.
(BFD32_BACKENDS_CFILES): Add elf32-rl78.c.
(Makefile.in): Regenerate.
* archures.c (bfd_architecture): Define bfd_arch_rl78.
(bfd_archures_list): Add bfd_rl78_arch.
* config.bfd: Add rl78-*-elf.
* configure.in: Add bfd_elf32_rl78_vec.
* reloc.c (bfd_reloc_code_type): Add BFD_RELOC_RL78_* relocations.
* targets.c (bfd_target_vector): Add bfd_elf32_rl78_vec.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* cpu-rl78.c: New file.
* elf32-rl78.c: New file.
[binutils]
* readelf.c: Include elf/rl78.h
(guess_is_rela): Handle EM_RL78.
(dump_relocations): Likewise.
(get_machine_name): Likewise.
(is_32bit_abs_reloc): Likewise.
* NEWS: Mention addition of RL78 support.
* MAINTAINERS: Add myself as RL78 port maintainer.
[gas]
* Makefile.am (TARGET_CPU_CFILES): Add tc-rl78.c.
(TARGET_CPU_HFILES): Add rc-rl78.h.
(EXTRA_DIST): Add rl78-parse.c and rl78-parse.y.
(rl78-parse.c, rl78-parse.h, rl78-parse.o, rl78-defs.h): New rules.
* Makefile.in: Regenerate.
* configure.in: Add rl78 case.
* configure: Regenerate.
* configure.tgt: Add rl78 case.
* config/rl78-defs.h: New file.
* config/rl78-parse.y: New file.
* config/tc-rl78.c: New file.
* config/tc-rl78.h: New file.
* NEWS: Add Renesas RL78.
* doc/Makefile.am (c-rl78.texi): New.
* doc/Makefile.in: Likewise.
* doc/all.texi: Enable it.
* doc/as.texi: Add it.
[include]
* dis-asm.h (print_insn_rl78): Declare.
[include/elf]
* common.h (EM_RL78, EM_78K0R): New.
* rl78.h: New.
[include/opcode]
* rl78.h: New file.
[ld]
* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32rl78.c.
(+eelf32rl78.c): New rule.
* Makefile.in: Regenerate.
* configure.tgt: Add rl78-*-* case.
* emulparams/elf32rl78.sh: New file.
* NEWS: Mention addition of Renesas RL78 support.
[opcodes]
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and
rl78-dis.c.
(MAINTAINERCLEANFILES): Add rl78-decode.c.
(rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
* Makefile.in: Regenerate.
* configure.in: Add bfd_rl78_arch case.
* configure: Regenerate.
* disassemble.c: Define ARCH_rl78.
(disassembler): Add ARCH_rl78 case.
* rl78-decode.c: New file.
* rl78-decode.opc: New file.
* rl78-dis.c: New file.
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aliases.
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capitalization in gas/NEWs and ld/NEWS.
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* configure.in (ALL_LINGUAS): Add ja.
* configure: Regenerate.
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* cpu-epiphany.c: Reinstate full list of Copyright years.
* elf32-epiphany.c: Likewise.
cpu:
* epiphany.cpu, epiphany.opc: Likewise.
gas:
* config/tc-epiphany.c, config/tc-epiphany.h: Likewise.
* doc/c-epiphany.texi: Likewise.
include:
* elf/epiphany.h: Likewise.
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* doc/as.texinfo [EPIPHANY]: Include c-epiphany.texi to avoid
duplication.
opcodes:
* disassemble.c (ARCH_epiphany): Move into alphasorted spot.
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rx-parse.c: In function ‘rx_parse’:
rx-parse.c:3774:9: error: passing argument 1 of ‘rx_error’ discards ‘const’
qualifier from pointer target type [-Werror]
../../../gas/config/rx-defs.h:40:12: note:
expected ‘char *’ but argument is of type ‘const char *’
cc1: all warnings being treated as errors
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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* Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo .
(ALL_MACHINES_CFILES): Add cpu-epiphany.c .
(BFD32_BACKENDS): Add elf32-epiphany.lo .
(BFD32_BACKENDS_CFILES): Add elf32-epiphany.c .
* Makefile.in, bfd-in2.h, configure, libbfd.h: Regenerate.
* archures.c (bfd_arch_epiphany): Add.
(bfd_mach_epiphany16, bfd_mach_epiphany32): Define.
(bfd_epiphany_arch): Declare.
(bfd_archures_list): Add &bfd_epiphany_arch.
* config.bfd (epiphany-*-elf): New target case.
* configure.in (bfd_elf32_epiphany_vec): New target vector case.
* reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation.
(BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise.
(BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise.
(BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise.
* targets.c (bfd_elf32_epiphany_vec): Declare.
(_bfd_target_vector): Add bfd_elf32_epiphany_vec.
* po/SRC-POTFILES.in, po/bfd.pot: Regenerate.
* cpu-epiphany.c, elf32-epiphany.c: New files.
binutils:
* readelf.c (include "elf/epiphany.h")
(guess_is_rela, dump_relocation): Handle EM_ADAPTEVA_EPIPHANY.
(get_machine_name, is_32bit_abs_reloc, is_32bit_pcrel_reloc): Likewise.
(is_16bit_abs_reloc, is_none_reloc): Likewise.
* po/binutils.pot: Regenerate.
cpu:
* cpu/epiphany.cpu, cpu/epiphany.opc: New files.
gas:
* NEWS: Mention addition of Adapteva Epiphany support.
* config/tc-epiphany.c, config/tc-epiphany.h: New files.
* Makefile.am (TARGET_CPU_CFILES): Add config/tc-epiphany.c .
(TARGET_CPU_HFILES): Add config/tc-epiphany.h .
* Makefile.in, configure, doc/Makefile.in, po/POTFILES.in: Regenerate.
* configure.in: Also set using_cgen for epiphany.
* configure.tgt: Handle epiphany.
* doc/Makefile.am (CPU_DOCS): Add c-epiphany.texi .
* doc/all.texi: Set EPIPHANY.
* doc/as.texinfo: Add EPIPHANY-specific text.
* doc/c-epiphany.texi: New file.
* po/gas.pot: Regenerate.
gas/testsuite:
* gas/epiphany: New directory.
include:
* dis-asm.h (print_insn_epiphany): Declare.
* elf/epiphany.h: New file.
* elf/common.h (EM_ADAPTEVA_EPIPHANY): Define.
ld:
* NEWS: Mention addition of Adapteva Epiphany support.
* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32epiphany.c .
(eelf32epiphany.c): New rule.
* Makefile.in: Regenerate.
* configure.tgt: Handle epiphany-*-elf.
* po/ld.pot: Regenerate.
* testsuite/ld-srec/srec.exp: xfail epiphany.
* emulparams/elf32epiphany.sh: New file.
opcodes:
* Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
(TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
(CLEANFILES): Add stamp-epiphany.
(EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
(stamp-epiphany): New rule.
* Makefile.in, configure, po/POTFILES.in, po/opcodes.pot: Regenerate.
* configure.in: Handle bfd_epiphany_arch.
* disassemble.c (ARCH_epiphany): Define.
(disassembler): Handle bfd_arch_epiphany.
* epiphany-asm.c, epiphany-desc.c, epiphany-desc.h: New files.
* epiphany-dis.c, epiphany-ibld.c, epiphany-opc.c: Likewise.
* epiphany-opc.h: Likewise.
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* m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
gas/testsuite/
* gas/m68k/all.exp (movem-offset): Add test.
* gas/m68k/movem-offset.s: New test.
* gas/m68k/movem-offset.d: New.
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(start_noreorder): Likewise.
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(mips_elf_final_processing): Likewise.
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* config/tc-alpha.c (load_expression): Use symbol_mark_used accessor.
(s_alpha_comm): Use symbol_set_frag accessor.
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* s390-opc.txt: Add CPUMF instructions.
2011-10-21 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gas/s390/zarch-z10.d: Add CPUMF instructions.
* gas/s390/zarch-z10.s: Likewise.
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(md_convert_frag): Likewise.
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Julian Brown <julian@codesourcery.com>
gas/
* config/tc-arm.c (parse_shifter_operand): Fix handling
of explicit rotation.
(encode_arm_shifter_operand): Likewise.
gas/testsuite/
* gas/arm/adrl.d: Adjust.
* gas/arm/immed2.d: New test.
* gas/arm/immed2.s: New test.
ld/testsuite/
* ld-arm/cortex-a8-fix-b-plt.d: Adjust.
* ld-arm/cortex-a8-fix-bcc-plt.d: Adjust.
* ld-arm/cortex-a8-fix-bl-plt.d: Adjust.
* ld-arm/cortex-a8-fix-bl-rel-plt.d: Adjust.
* ld-arm/cortex-a8-fix-blx-plt.d: Adjust.
* ld-arm/ifunc-1.dd: Adjust.
* ld-arm/ifunc-2.dd: Adjust.
* ld-arm/ifunc-3.dd: Adjust.
* ld-arm/ifunc-4.dd: Adjust.
* ld-arm/ifunc-5.dd: Adjust.
* ld-arm/ifunc-6.dd: Adjust.
* ld-arm/ifunc-7.dd: Adjust.
* ld-arm/ifunc-8.dd: Adjust.
* ld-arm/ifunc-9.dd: Adjust.
* ld-arm/ifunc-10.dd: Adjust.
* ld-arm/ifunc-14.dd: Adjust.
* ld-arm/ifunc-15.dd: Adjust.
* ld-arm/ifunc-16.dd: Adjust.
opcodes/
* arm-dis.c (print_insn_arm): Explicitly specify rotation
if needed.
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(do_ldst): Warn in upredictable cases.
(do_t_ldst): Likewise.
(insns): Update accordingly.
* gas/arm/ldr-bad.s: New testcase.
* gas/arm/ldr-bad.l: Likewise.
* gas/arm/ldr-bad.d: Likewise.
* gas/arm/ldr.s: Likewise.
* gas/arm/ldr.d: Likewise.
* gas/arm/ldr-t-bad.s: Likewise.
* gas/arm/ldr-t-bad.l: Likewise.
* gas/arm/ldr-t-bad.d: Likewise.
* gas/arm/ldr-t.s: Likewise.
* gas/arm/ldr-t.d: Likewise.
* gas/arm/sp-pc-usage-t.s: Correct.
* gas/arm/sp-pc-usage-t.d: Update accordingly.
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* frags.h (bss_address_frag): Delete
(predefined_address_frag): New.
* frags.c (frag_init): Init predefined_address_frag. Delete ref
to bss_addres_frag.
* symbols.c (S_CAN_BE_REDEFINED): New function.
* symbols.h (S_CAN_BE_REDEFINED): Declare.
* read.c (assign_symbol): Use S_CAN_BE_REDEFINED.
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* symbols.h (local_symbol_make): Declare.
* as.c (main): Define __GAS_VERSION__.
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2011-09-28 Jan Beulich <jbeulich@suse.com>
* gas/ppc/476.s: Fix lswi first operand.
* gas/ppc/476.d: Adjust expected output.
* gas/ppc/a2.s: Fix lswi first operand.
* gas/ppc/a2.d: Adjust expected output.
* gas/ppc/power6.s: Fix lfdpx first operand.
* gas/ppc/power6.d: Adjust expected output.
opcodes/
2011-09-28 Jan Beulich <jbeulich@suse.com>
* ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
RBX): New.
(insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
(powerpc_opcodes): Use RAX for second and RBXC for third operand of
lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
on DFP quad instructions.
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* ld-scripts/phdrs.exp: Expect to fail for the RX.
* elf32-rx.c: Add support for PID mode.
(rx_elf_relocate_section): Add checks for unsafe PID relocations.
Include addend in R_RX_SYM relocations.
* config/rx-defs.h (rx_pid_register): New.
(rx_gp_register): New.
* config/rx-parse.y (rx_lex): Add support for %gpreg and %pidreg.
(displacement): Add PID support.
* config/tc-rx.c (rx_pid_mode): New.
(rx_num_int_regs): New.
(rx_pid_register): New.
(rx_gp_register): New.
(options): Add -mpid and -mint-register= options.
(md_longopts): Likewise.
(md_parse_option): Likewise.
(md_show_usage): Likewise.
(rx_pid_symbol): New.
(rx_pidreg_symbol): New.
(rx_gpreg_symbol): New.
(md_begin): Support PID.
(rx_validate_fix_sub): Support PID.
(tc_gen_reloc): Support PID.
* doc/c-rx.texi: Document PID support.
* rx.h (E_FLAG_RX_PID): New.
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* config/obj-coff.c (obj_coff_section): Add 'e' as specifier
for marking section SEC_EXCLUDE.
2011-09-27 Kai Tietz <ktietz@redhat.com>
* gas/pe/pe.exp: Add new testcase.
* gas/pe/section-exclude.d: New file.
* gas/pe/section-exclude.s: New file.
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* sparc-opc.c (sparc_opcodes): Fix random instruction to write
to a float instead of an integer register.
gas/testsuite/
* gas/sparc/hpcvis3.s: Update to use float reg for random insn.
* gas/sparc/hpcvis3.d: Likewise.
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opcodes/
* sparc-opc.c (sparc_opcodes): Add integer multiply-add
instructions.
gas/testsuite/
* gas/sparc/ima.d: New test.
* gas/sparc/ima.s: New test source.
* gas/sparc/sparc.exp: Run new test.
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2011-09-22 Tristan Gingold <gingold@adacore.com>
* NEWS: Add marker for 2.22.
gas/
2011-09-22 Tristan Gingold <gingold@adacore.com>
* NEWS: Add marker for 2.22.
ld/
2011-09-22 Tristan Gingold <gingold@adacore.com>
* NEWS: Add marker for 2.22.
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gas/
* config/tc-sparc.c (hwcap_allowed): New.
(struct sparc_arch): New field 'hwcap_allowed' containing a bitmask
of F_FOO flags which are enabled by the particular arch setting.
Add new options that provide explicit access to new instructions.
(md_parse_option): Only bump max_architecture if the requested one
is larger, or this is the first explicit request.
(get_hwcap_name): New function.
(sparc_ip): Validate that hwcaps used by an instruction have actually
been enabled.
* doc/c-sparc.texi: Document new sparc options.
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gas/testsuite/
* gas/sparc/imm-plus-rreg.d: Fix address regex for 64-bit.
* gas/sparc/save-args.d: Likewise.
* gas/sparc/ticc-imm-reg.d: Likewise, add -32 to options.
* gas/sparc/v8-movwr-imm.d: Likewise.
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bfd/
* elfxx-sparc.c (_bfd_sparc_elf_merge_private_bfd_data): New.
* elfxx-sparc.h: Declare it.
* elf32-sparc.c (elf32_sparc_merge_private_bfd_data): Call it.
* elf64-sparc.c (elf64_sparc_merge_private_bfd_data): Likewise.
binutils/
* readelf.c (display_sparc_hwcaps): New.
(display_sparc_gnu_attribute): New.
(process_sparc_specific): New.
(process_arch_specific): When EM_SPARC, EM_SPARC32PLUS,
or EM_SPARCV9 invoke process_sparc_specific.
gas/
* config/tc-sparc.c (hwcap_seen): New bitmask, defined when
not TE_SOLARIS.
(sparc_ip): When not TE_SOLARIS, accumulate hwcap bits from
sparc_opcode->flags of instruction into hwcap_seen.
(sparc_md_end): Create Tag_GNU_Sparc_HWCAPS attribute if
hwcap_seen is non-zero and not TE_SOLARIS.
gas/testsuite/
* gas/sparc/hpcvis3.s: Update for fixed fchksum16 mnemonic.
* gas/sparc/hpcvis3.d: Likewise.
include/elf/
* sparc.h (Tag_GNU_Sparc_HWCAPS): New object attribute.
(ELF_SPARC_HWCAP_*): New HWCAPS bitmask values.
include/opcode/
* sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
(F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
opcodes/
* sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
bits. Fix "fchksm16" mnemonic.
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* config/tc-alpha.c (insert_operand): Call as_bad_value_out_of_range
instead of as_warn_out_of_range.
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* sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
This has been reported as being accepted by the Sun assmebler.
gas/testsuite/
* gas/sparc/save-args.[sd]: New test.
* gas/sparc/sparc.exp: Run new test.
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The changes below bring 'mov' and 'ticc' instructions into line
with the V8 SPARC Architecture Manual.
* sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
* sparc-opc.c (sparc_opcodes): Add alias entries for
'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
'mov regrs2,%wim' and 'mov regrs2,%tbr'.
* sparc-opc.c (sparc_opcodes): Move/Change entries for
'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
and 'mov imm,%tbr'.
* sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
mov aliases.
gas/testsuite/
* gas/sparc/ticc-imm-reg.[sd]: New test.
* gas/sparc/v8-movwr-imm.[sd]: New test.
* gas/sparc/sparc.exp: Run new tests.
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* config/tc-sparc.c (sparc_ip): Handle 'i' + r<0..31>
in addition to 'i' + [goli]<0..7>.
gas/testsuite/
* gas/sparc/imm-plus-rreg.[sd]: New test.
* gas/sparc/sparc.exp: Run new test.
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