aboutsummaryrefslogtreecommitdiff
path: root/gas
AgeCommit message (Collapse)AuthorFilesLines
2011-07-04 * gas/mips/loc-swap.s: Add file missing from a previous commit.Maciej W. Rozycki1-0/+48
2011-07-04gas/Richard Sandiford2-2/+9
* config/tc-mips.c (gpr_read_mask, gpr_write_mask): Fix handling of register 0.
2011-07-04 gas/Maciej W. Rozycki8-4/+224
* config/tc-mips.c (append_insn): Make sure DWARF-2 location information is properly adjusted for branches that get swapped. gas/testsuite/ * gas/mips/loc-swap.d: New test case for DWARF-2 location with branch swapping. * gas/mips/loc-swap-dis.d: Likewise. * gas/mips/mips16@loc-swap.d: Likewise, MIPS16 version. * gas/mips/mips16@loc-swap-dis.d: Likewise. * gas/mips/loc-swap.s: Source for the new tests. * gas/mips/mips.exp: Run the new tests.
2011-07-03ELFOSABI_GNUThomas Schwinge1-0/+1
bfd/ * elf.c (_bfd_elf_set_osabi): Use ELFOSABI_GNU name instead of ELFOSABI_LINUX alias. * elf32-hppa.c: Likewise. * elf32-i370.c: Likewise. * elf64-hppa.c: Likewise. binutils/ * elfedit.c (osabis): Use ELFOSABI_GNU name instead of ELFOSABI_LINUX alias and ELFOSABI_HURD. Add GNU alias. * readelf.c (get_osabi_name, get_symbol_binding, get_symbol_type): Likewise. * doc/binutils.texi <elfedit>: Update accordingly. elfcpp/ * elfcpp.h (ELFOSABI): Add ELFOSABI_GNU with value of ELFOSABI_LINUX, keep ELFOSABI_LINUX as an alias. Remove ELFOSABI_HURD. gas/ * config/obj-elf.c (obj_elf_type): Use ELFOSABI_GNU name instead of ELFOSABI_LINUX alias. * config/tc-ia64.c: Likewise. include/elf/ * common.h (ELFOSABI_GNU): Define, replaces... (ELFOSABI_LINUX): ... this, kept as an alias. (ELFOSABI_HURD): Remove. ld/testsuite/ * ld-ifunc/ifunc.exp: Update for changed output. * ld-unique/unique.exp: Likewise.
2011-07-03ELFOSABI_GNUThomas Schwinge4-9/+17
bfd/ * elf.c (_bfd_elf_set_osabi): Use ELFOSABI_GNU name instead of ELFOSABI_LINUX alias. * elf32-hppa.c: Likewise. * elf32-i370.c: Likewise. * elf64-hppa.c: Likewise. binutils/ * elfedit.c (osabis): Use ELFOSABI_GNU name instead of ELFOSABI_LINUX alias and ELFOSABI_HURD. Add GNU alias. * readelf.c (get_osabi_name, get_symbol_binding, get_symbol_type): Likewise. * doc/binutils.texi <elfedit>: Update accordingly. elfcpp/ * elfcpp.h (ELFOSABI): Add ELFOSABI_GNU with value of ELFOSABI_LINUX, keep ELFOSABI_LINUX as an alias. Remove ELFOSABI_HURD. gas/ * config/obj-elf.c (obj_elf_type): Use ELFOSABI_GNU name instead of ELFOSABI_LINUX alias. * config/tc-ia64.c: Likewise. include/elf/ * common.h (ELFOSABI_GNU): Define, replaces... (ELFOSABI_LINUX): ... this, kept as an alias. (ELFOSABI_HURD): Remove. ld/testsuite/ * ld-ifunc/ifunc.exp: Update for changed output. * ld-unique/unique.exp: Likewise.
2011-06-30Fix rorx in BMI2.H.J. Lu7-75/+86
gas/testsuite/ 2011-06-30 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2011) * gas/i386/bmi2.s: Correct rorx tests. * gas/i386/x86-64-bmi2.s: Likewise. * gas/i386/bmi2-intel.d: Updated. * gas/i386/bmi2.d: Likewise. * gas/i386/x86-64-bmi2-intel.d: Likewise. * gas/i386/x86-64-bmi2.d: Likewise. opcodes/ 2011-06-30 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2011) * i386-dis.c (vex_len_table): Correct rorxS. * i386-opc.tbl: Correct rorx. * i386-tbl.h: Regenerated.
2011-06-30 * gas/arm/addthumb2err.s: New test file.Nick Clifton6-0/+74
* gas/arm/addthumb2err.d: Test control file. * gas/arm/addthumb2err.l: Expected error messages. * config/tc-arm.c (do_t_add_sub): Only allow LSL shifts of less than 4 in Thumb mode.
2011-06-30 PR gas/12931Nick Clifton4-1/+11
* gas/arm/blx-bad.d: Add exrta nop at end of disassembly. * gas/arm/inst-po-be.d: Add exrta nop at end of disassembly. * gas/arm/inst-po.d: Add exrta nop at end of disassembly.
2011-06-30 PR 12848Nick Clifton4-0/+34
* gas/arm/thumb-b-bad.s: New test. * gas/arm/thumb-b-bad.d: Test control file. * gas/arm/thumb-b-bad.l: Expected error output.
2011-06-30 PR gas/12848Nick Clifton2-28/+23
* config/tc-arm.c (BAD_RANGE): New error message define. (md_apply_fix): Use it. Fix range check for thumb branch instructions.
2011-06-29gas/Richard Sandiford2-156/+238
* config/tc-mips.c (append_method): New enum. (can_swap_branch_p, get_append_method): New functions. (append_insn): Use get_append_method to decide how the instruction should be added.
2011-06-29gas/Richard Sandiford2-96/+96
* config/tc-mips.c (append_insn): Remove bogus goto.
2011-06-29gas/Richard Sandiford2-7/+11
* config/tc-mips.c (append_insn): Always clear the history after an unconditional branch.
2011-06-29gas/Richard Sandiford2-0/+24
* config/tc-mips.c (find_altered_mips16_opcode): New function. (append_insn): Use it. opcodes/ * mips16-opc.c (jalrc, jrc): Move earlier in file.
2011-06-29gas/Richard Sandiford15-233/+214
* config/tc-mips.c (insn_uses_reg): Delete. (gpr_read_mask, gpr_write_mask): New functions. (fpr_read_mask, fpr_write_mask): Likewise. (insns_between, nops_for_vr4130, append_insn): Use them. gas/testsuite/ * gas/mips/mips16-e.d, gas/mips/mips16-f.d, gas/mips/mipsel16-e.d, gas/mips/mipsel16-f.d, gas/mips/tmips16-e.d, gas/mips/tmips16-f.d, gas/mips/tmipsel16-e.d, gas/mips/tmipsel16-f.d: Fix GPR mask. * gas/mips/reginfo-1.s, gas/mips/reginfo-1a.d, gas/mips/reginfo-1b.d: New tests. * gas/mips/mips.exp: Run them.
2011-06-29gas/Richard Sandiford9-10/+36
* config/tc-mips.c (md_mips_end): Call mips_emit_delays. gas/testsuite/ * gas/mips/24k-triple-stores-9.d: Add -z to dump options and explicitly match one nop. * gas/mips/24k-triple-stores-10.d: Likewise. * gas/mips/24k-triple-stores-11.d: Likewise. * gas/mips/lifloat.d: Likewise. * gas/mips/trunc.d: Likewise 1 extra nop. * gas/mips/vr4111.d: Likewise 2 nops.
2011-06-29 PR gas/12931Nick Clifton2-1/+24
* config/tc-arm.c (mapping_state): When changing to ARM or THUMB state set the minimum required alignment of the section.
2011-06-292011-06-29 Tristan Gingold <gingold@adacore.com>Tristan Gingold2-27/+20
* config/tc-i386.c (i386_mach): Convert to ISO-C. (md_begin, pe_directive_secrel, md_estimate_size_before_relax): Ditto. (md_convert_frag, md_apply_fix, md_undefined_symbol): Ditto. (md_section_align, tc_gen_reloc): Ditto.
2011-06-282011-06-28 Tristan Gingold <gingold@adacore.com>Tristan Gingold2-16/+9
* config/tc-alpha.c (s_alpha_pdesc): Fix indentation. Do not generate dummy fix.
2011-06-282011-06-28 Tristan Gingold <gingold@adacore.com>Tristan Gingold2-4/+13
* config/tc-alpha.c (load_expression): Use alloca instead of xmalloc. (emit_jsrjmp): Ditto. (tc_gen_reloc): Ditto.
2011-06-282011-06-28 Tristan Gingold <gingold@adacore.com>Tristan Gingold2-29/+34
* config/tc-alpha.c (alpha_evax_proc_hash): Remove. (alpha_evax_proc_data): New variable. (s_alpha_ent): Prevent nested function. Remove has_insert call. (s_alpha_pdesc): Do not call demand_empty_rest_of_line in case of error. Do not search in the hash table. Check if match with .ent. (s_alpha_name): Remove unused variable. (md_begin): Remove initialization of alpha_evax_proc_hash.
2011-06-272011-06-27 Tristan Gingold <gingold@adacore.com>Tristan Gingold2-22/+23
* config/tc-alpha.c (add_to_link_pool): Remove basesym parameter. Locally declare basesym. Add comments. Do not set literal_pool_size. (load_expression): Adjust call to add_to_link_pool. (s_alpha_pdesc): Define pdesc symbol using dot. Do not set literal_pool_size. (s_alpha_end): Use NULL instead of 0.
2011-06-272011-06-27 Tristan Gingold <gingold@adacore.com>Tristan Gingold3-14/+20
* config/obj-evax.c (evax_frob_file_before_adjust): Add comments. Fix style. * config/obj-evax.h (struct alpha_linkage_fixups): Remove seg field. Add comments. (obj_symbol_type, object_headers, OBJ_SYMFIELD_TYPE): Remove
2011-06-26Remove previous patch, committed in error.Richard Sandiford11-180/+233
2011-06-26gas/Richard Sandiford11-233/+180
* config/tc-mips.c (insn_uses_reg): Delete. (gpr_read_mask, gpr_write_mask): New functions. (fpr_read_mask, fpr_write_mask): Likewise. (insns_between, nops_for_vr4130, append_insn): Use them. gas/testsuite/ * gas/mips/mips16-e.d, gas/mips/mips16-f.d, gas/mips/mipsel16-e.d, gas/mips/mipsel16-f.d, gas/mips/tmips16-e.d, gas/mips/tmips16-f.d, gas/mips/tmipsel16-e.d, gas/mips/tmipsel16-f.d: Fix GPR mask.
2011-06-26gas/Richard Sandiford14-230/+252
* config/tc-mips.c (fix_24k_record_store_info): If the previous instruction was a store, and the next instructions are unknown, assume the worst. gas/testsuite/ * gas/mips/24k-branch-delay-1.d: Do not allow stores to be put into delay slots. * gas/mips/24k-triple-stores-1.d: Put the first nop after the second store, rather than the first. * gas/mips/24k-triple-stores-2.d: Likewise. * gas/mips/24k-triple-stores-4.d: Likewise. * gas/mips/24k-triple-stores-8.d: Likewise. * gas/mips/24k-triple-stores-3.d: Remove first nop. * gas/mips/24k-triple-stores-5.d: Likewise. * gas/mips/24k-triple-stores-6.d: Likewise. * gas/mips/24k-triple-stores-7.d: Likewise. * gas/mips/24k-triple-stores-9.d: Add a nop after the second store. Expect a nop at the end. * gas/mips/24k-triple-stores-10.d: Put the first nop after the second store, rather than the first. Expect a nop at the end.
2011-06-25gas/Richard Sandiford5-65/+273
PR gas/12915 * config/tc-mips.c (nops_for_vr4130, nops_for_24k, nops_for_insn) (nops_for_sequence, nops_for_insn_or_target): Add ignore parameters. (mips_emit_delays, start_noreorder): Update accordingly. (append_insn): Likewise. Revert original fix for this PR and use the ignore parameter instead. gas/testsuite/ * gas/mips/vr4130.s: Add some more ".set noreorder" tests. * gas/mips/vr4130.d: Update accordingly.
2011-06-242011-06-24 Tristan Gingold <gingold@adacore.com>Tristan Gingold2-2/+10
PR gas/11625 * config/obj-evax.c (evax_frob_symbol): Use as_bad instead of abort.
2011-06-242011-06-24 Tristan Gingold <gingold@adacore.com>Tristan Gingold2-10/+7
* config/tc-alpha.c (add_to_link_pool): Remove useless offset variable. Fix style.
2011-06-23gas/Richard Sandiford6-2/+45
PR gas/12915 * config/tc-mips.c (append_insn): Only consider hazards between the pre-noreorder block and ip. gas/testsuite/ * gas/mips/pr12915.s, gas/mips/pr12915.d: New test. * gas/mips/mips.exp: Run it.
2011-06-212011-06-21 Sameera Deshpande <sameera.deshpande@arm.com>Matthew Gretton-Dann8-2/+195
* gas/config/tc-arm.c (vfp_conv): Add check on range of immediate operand in vcvt instruction between floating-point and fixed-point. (operand_parse_code): Add "OP_oI32z". (parse_operands): OP_oI32z case added. * gas/testsuite/gas/arm/vcvt-bad.d: New test. * gas/testsuite/gas/arm/vcvt-bad.l: Likewise. * gas/testsuite/gas/arm/vcvt-bad.s: Likewise. * gas/testsuite/gas/arm/vcvt.d: Likewise. * gas/testsuite/gas/arm/vcvt.s: Likewise.
2011-06-20Revert x86_64-x32-* change.H.J. Lu2-8/+5
gas/ 2011-06-20 H.J. Lu <hongjiu.lu@intel.com> * configure.tgt: Revert x32 change. ld/ 2011-06-20 H.J. Lu <hongjiu.lu@intel.com> * configure.tgt: Revert x32 change. ld/testsuite/ 2011-06-20 H.J. Lu <hongjiu.lu@intel.com> * ld-elf/eh1.d: Revert x32 change. * ld-elf/eh2.d: Likewise. * ld-elf/eh3.d: Likewise. * ld-elf/eh4.d: Likewise.
2011-06-20 * doc/Makefile.am: (CPU_DOCS): Add c-xstormy16.texi.Nick Clifton5-0/+114
* doc/Makefile.in: Regenerate. * doc/all.texi: Set XSTORMY16. * doc/c-xstormy16.texi: New file.
2011-06-19Fix misc x32 bugs.H.J. Lu2-1/+12
bfd/ 2011-06-19 H.J. Lu <hongjiu.lu@intel.com> * elf64-x86-64.c (elf_backend_post_process_headers): Defined for x32. binutils/testsuite/ 2011-06-19 H.J. Lu <hongjiu.lu@intel.com> * binutils-all/elfedit-1.d: Updated for x32. gas/ 2011-06-19 H.J. Lu <hongjiu.lu@intel.com> * configure.tgt: Support x32. ld/ 2011-06-19 H.J. Lu <hongjiu.lu@intel.com> * configure.tgt: Support x32. ld/testsuite/ 2011-06-19 H.J. Lu <hongjiu.lu@intel.com> * ld-elf/eh1.d: Skip x32. * ld-elf/eh2.d: Likewise. * ld-elf/eh3.d: Likewise. * ld-elf/eh4.d: Likewise. * ld-elfvsb/elfvsb.exp: Only xfail 64bit x86_64-*-linux*. * ld-shared/shared.exp: Likewise. * ld-ifunc/ifunc-1-local-x86.d: Support x32. * ld-ifunc/ifunc-1-x86.d: Likewise. * ld-ifunc/ifunc-3a-x86.d: Likewise. * ld-x86-64/pcrel16.d: Likewise. * ld-x86-64/x86-64.exp (x86_64tests): Add missing -melf_x86_64.
2011-06-15 * NEWS: Mention addition of TILEPRO and TIKE-Gx support.Nick Clifton2-1/+6
2011-06-14gas/Tristan Gingold5-50/+39
2011-06-14 Tristan Gingold <gingold@adacore.com> * config/tc-ppc.h (struct ppc_tc_sy): Complete comment on within. (tc_new_dot_label): Define. (ppc_new_dot_label): Declare. * config/tc-ppc.c (ppc_frob_label): Set within target field. (ppc_fix_adjustable): Use this field to adjust the reloc. (ppc_new_dot_label): New function. gas/testsuite/ 2011-06-14 Tristan Gingold <gingold@adacore.com> * gas/ppc/test1xcoff32.d: Adjust for csect anchor.
2011-06-14 * po/POTFILES.in: Regenerate.Alan Modra2-0/+8
2011-06-13 * Makefile.am (ALL_MACHINES): Add cpu-tilegx.lo and cpu-tilepro.lo.Nick Clifton23-0/+42624
(ALL_MACHINE_CFILES): Add cpu-tilegx.c and cpu-tilepro.c. (BFD32_BACKENDS): Add elf32-tilegx.lo, elf32-tilepro.lo, and elfxx-tilegx.lo. (BFD32_BACKENDS_CFILES): Add elf32-tilegx.c elf32-tilepro.c, and elfxx-tilegx.c. (BFD64_BACKENDS): Add elf64-tilegx.lo. (BFD64_BACKENDS_CFILES): Add elf64-tilegx.c. * Makefile.in: Regenerate. * arctures.c (bfd_architecture): Define bfd_arch_tilepro, bfd_arch_tilegx, bfd_mach_tilepro, bfd_mach_tilegx. (bfd_arch_info): Add bfd_tilegx_arch, bfd_tilepro_arch. (bfd_archures_list): Add bfd_tilegx_arch, bfd_tilepro_arch. bfd-in2.h: Regenerate. * config.bfd: Handle tilegx-*-* and tilepro-*-*. * configure.in: Handle bfd_elf32_tilegx_vec, bfd_elf32_tilepro_vec, and bfd_elf64_tilegx_vec. * configure: Regenerate. * elf-bfd.h (enum elf_target_id): Define TILEGX_ELF_DATA and TILEPRO_ELF_DATA. * libbfd.h: Regenerate. * reloc.c: Add BFD_RELOC_TILEPRO_{COPY, GLOB_DAT, JMP_SLOT, RELATIVE, BROFF_X1, JOFFLONG_X1, JOFFLONG_X1_PLT, IMM8_X0, IMM8_Y0, IMM8_X1, IMM8_Y1, DEST_IMM8_X1, MT_IMM15_X1, MF_IMM15_X1, IMM16_X0, IMM16_X1, IMM16_X0_LO, IMM16_X1_LO, IMM16_X0_HI, IMM16_X1_HI, IMM16_X0_HA, IMM16_X1_HA, IMM16_X0_PCREL, IMM16_X1_PCREL, IMM16_X0_LO_PCREL, IMM16_X1_LO_PCREL, IMM16_X0_HI_PCREL, IMM16_X1_HI_PCREL, IMM16_X0_HA_PCREL, IMM16_X1_HA_PCREL, IMM16_X0_GOT, IMM16_X1_GOT, IMM16_X0_GOT_LO, IMM16_X1_GOT_LO, IMM16_X0_GOT_HI, IMM16_X1_GOT_HI, IMM16_X0_GOT_HA, IMM16_X1_GOT_HA, MMSTART_X0, MMEND_X0, MMSTART_X1, MMEND_X1, SHAMT_X0, SHAMT_X1, SHAMT_Y0, SHAMT_Y1, IMM16_X0_TLS_GD, IMM16_X1_TLS_GD, IMM16_X0_TLS_GD_LO, IMM16_X1_TLS_GD_LO, IMM16_X0_TLS_GD_HI, IMM16_X1_TLS_GD_HI, IMM16_X0_TLS_GD_HA, IMM16_X1_TLS_GD_HA, IMM16_X0_TLS_IE, IMM16_X1_TLS_IE, IMM16_X0_TLS_IE_LO, IMM16_X1_TLS_IE_LO, IMM16_X0_TLS_IE_HI, IMM16_X1_TLS_IE_HI, IMM16_X0_TLS_IE_HA, IMM16_X1_TLS_IE_HA, TLS_DTPMOD32, TLS_DTPOFF32, TLS_TPOFF32} Add BFD_RELOC_TILEGX_{HW0, HW1, HW2, HW3, HW0_LAST, HW1_LAST, HW2_LAST, COPY, GLOB_DAT, JMP_SLOT, RELATIVE, BROFF_X1, JUMPOFF_X1, JUMPOFF_X1_PLT, IMM8_X0, IMM8_Y0, IMM8_X1, IMM8_Y1, DEST_IMM8_X1, MT_IMM14_X1, MF_IMM14_X1, MMSTART_X0, MMEND_X0, SHAMT_X0, SHAMT_X1, SHAMT_Y0, SHAMT_Y1, IMM16_X0_HW0, IMM16_X1_HW0, IMM16_X0_HW1, IMM16_X1_HW1, IMM16_X0_HW2, IMM16_X1_HW2, IMM16_X0_HW3, IMM16_X1_HW3, IMM16_X0_HW0_LAST, IMM16_X1_HW0_LAST, IMM16_X0_HW1_LAST, IMM16_X1_HW1_LAST, IMM16_X0_HW2_LAST, IMM16_X1_HW2_LAST, IMM16_X0_HW0_PCREL, IMM16_X1_HW0_PCREL, IMM16_X0_HW1_PCREL, IMM16_X1_HW1_PCREL, IMM16_X0_HW2_PCREL, IMM16_X1_HW2_PCREL, IMM16_X0_HW3_PCREL, IMM16_X1_HW3_PCREL, IMM16_X0_HW0_LAST_PCREL, IMM16_X1_HW0_LAST_PCREL, IMM16_X0_HW1_LAST_PCREL, IMM16_X1_HW1_LAST_PCREL, IMM16_X0_HW2_LAST_PCREL, IMM16_X1_HW2_LAST_PCREL, IMM16_X0_HW0_GOT, IMM16_X1_HW0_GOT, IMM16_X0_HW1_GOT, IMM16_X1_HW1_GOT, IMM16_X0_HW2_GOT, IMM16_X1_HW2_GOT, IMM16_X0_HW3_GOT, IMM16_X1_HW3_GOT, IMM16_X0_HW0_LAST_GOT, IMM16_X1_HW0_LAST_GOT, IMM16_X0_HW1_LAST_GOT, IMM16_X1_HW1_LAST_GOT, IMM16_X0_HW2_LAST_GOT, IMM16_X1_HW2_LAST_GOT, IMM16_X0_HW0_TLS_GD, IMM16_X1_HW0_TLS_GD, IMM16_X0_HW1_TLS_GD, IMM16_X1_HW1_TLS_GD, IMM16_X0_HW2_TLS_GD, IMM16_X1_HW2_TLS_GD, IMM16_X0_HW3_TLS_GD, IMM16_X1_HW3_TLS_GD, IMM16_X0_HW0_LAST_TLS_GD, IMM16_X1_HW0_LAST_TLS_GD, IMM16_X0_HW1_LAST_TLS_GD, IMM16_X1_HW1_LAST_TLS_GD, IMM16_X0_HW2_LAST_TLS_GD, IMM16_X1_HW2_LAST_TLS_GD, IMM16_X0_HW0_TLS_IE, IMM16_X1_HW0_TLS_IE, IMM16_X0_HW1_TLS_IE, IMM16_X1_HW1_TLS_IE, IMM16_X0_HW2_TLS_IE, IMM16_X1_HW2_TLS_IE, IMM16_X0_HW3_TLS_IE, IMM16_X1_HW3_TLS_IE, IMM16_X0_HW0_LAST_TLS_IE, IMM16_X1_HW0_LAST_TLS_IE, IMM16_X0_HW1_LAST_TLS_IE, IMM16_X1_HW1_LAST_TLS_IE, IMM16_X0_HW2_LAST_TLS_IE, IMM16_X1_HW2_LAST_TLS_IE, TLS_DTPMOD64, TLS_DTPOFF64, TLS_TPOFF64, TLS_DTPMOD32, TLS_DTPOFF32, TLS_TPOFF32} * targets.c (bfd_elf32_tilegx_vec): Declare. (bfd_elf32_tilepro_vec): Declare. (bfd_elf64_tilegx_vec): Declare. (bfd_target_vector): Add bfd_elf32_tilegx_vec, bfd_elf32_tilepro_vec, and bfd_elf64_tilegx_vec. * cpu-tilegx.c: New file. * cpu-tilepro.c: New file. * elf32-tilepro.h: New file. * elf32-tilepro.c: New file. * elf32-tilegx.c: New file. * elf32-tilegx.h: New file. * elf64-tilegx.c: New file. * elf64-tilegx.h: New file. * elfxx-tilegx.c: New file. * elfxx-tilegx.h: New file. * Makefile.am (TARGET_CPU_CFILES): Add config/tc-tilegx.c and config/tc-tilepro.c. (TARGET_CPU_HFILES): Add config/tc-tilegx.h and config/tc-tilepro.h. * Makefile.in: Regenerate. * configure.tgt (tilepro-*-*): New. (tilegx-*-*): Likewise. * config/tc-tilegx.c: New file. * config/tc-tilegx.h: Likewise. * config/tc-tilepro.h: Likewise. * config/tc-tilepro.c: Likewise. * doc/Makefile.am (CPU_DOCS): Add c-tilegx.texi and c-tilepro.texi. * doc/Makefile.in: Regenerate. * doc/all.texi (TILEGX): Define. (TILEPRO): Define. * doc/as.texinfo: Add Tile-Gx and TILEPro documentation. Include c-tilegx.texi and c-tilepro.texi. * doc/c-tilegx.texi: New. * doc/c-tilepro.texi: New. * gas/tilepro/t_constants.s: New file. * gas/tilepro/t_constants.d: Likewise. * gas/tilepro/t_insns.s: Likewise. * gas/tilepro/tilepro.exp: Likewise. * gas/tilepro/t_insns.d: Likewise. * gas/tilegx/tilegx.exp: Likewise. * gas/tilegx/t_insns.d: Likewise. * gas/tilegx/t_insns.s: Likewise. * dis-asm.h (print_insn_tilegx): Declare. (print_insn_tilepro): Likewise. * tilegx.h: New file. * tilepro.h: New file. * common.h: Add EM_TILEGX. * tilegx.h: New file. * tilepro.h: New file. * Makefile.am (ALL_EMULATION_SOURCES): Add eelf32tilegx.c and eelf32tilepro.c. (ALL_64_EMULATION_SOURCES): Add eelf64tilegx.c. (eelf32tilegx.c): New target. (eelf32tilepro.c): Likewise. (eelf64tilegx.c): Likewise. * Makefile.in: Regenerate. * configure.tgt: Handle tilegx-*-* and tilepro-*-*. * emulparams/elf32tilegx.sh: New file. * emulparams/elf64tilegx.sh: New file. * emulparams/elf32tilepro.sh: New file. * ld-elf/eh5.d: Don't run on tile*. * ld-srec/srec.exp: xfail on tile*. * ld-tilegx/external.s: New file. * ld-tilegx/reloc.d: New file. * ld-tilegx/reloc.s: New file. * ld-tilegx/tilegx.exp: New file. * ld-tilepro/external.s: New file. * ld-tilepro/reloc.d: New file. * ld-tilepro/reloc.s: New file. * ld-tilepro/tilepro.exp: New file. * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c, tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c. * Makefile.in: Regenerate. * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch. * configure: Regenerate. * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro. * po/POTFILES.in: Regenerate. * tilegx-dis.c: New file. * tilegx-opc.c: New file. * tilepro-dis.c: New file. * tilepro-opc.c: New file.
2011-06-13PR gas/12854Nick Clifton3-6/+22
Add additional checks for extraneous shifts and extra tests in the testsuite.
2011-06-13 PR gas/12854Nick Clifton6-0/+40
* gas/arm/shift-bad.s: New test. * gas/arm/shift-bad.l: Expcted error output. * gas/arm/shift-bad.s: New control file. * config/tc-arm.c (do_shift): Do not allow shift operations at the end of a register based shift insn. (do_t_shift): Likewise.
2011-06-13 * config/tc-score.c (s3_my_get_expression): Delete unused localNick Clifton3-323/+309
variable 'seg'. (s3_do_ldst_insn): Delete unused local variable 'strbak'. (s3_do16_ldst_insn): Delete unused local variable 'temp'. (s3_do_macro_bcmp): Zero inst_expand array. (s3_do_macro_bcmpz): Likewise. (s3_s_score_end): Delete unused local variable 'dot'. (s3_gen_reloc): Delete unused local variables 'f', 's', and 'e'. * config/tc-score7.c (s7_my_get_expression): Delete unused local variable 'seg'. (s7_do_ldst_insn): Delete unused local variable 'strbak'. (s7_b32_relax_to_b16): Delete unused local variables 'r_old' and 'r_new'. (s7_s_score_end): Delete unused local variable 'dot'. (s7_relax_frag): Delete unused local variable 'relax_size'. (s7_gen_reloc): Delete unused local variables 'f', 's', and 'e'.
2011-06-13Update lzcnt testcases.H.J. Lu3-0/+10
2011-06-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10-lzcnt.d: Updated. * gas/i386/x86-64-arch-2-lzcnt.d: Likewise.
2011-06-10Support AVX Programming Reference (June, 2011).H.J. Lu47-12/+6396
gas/ 2011-06-10 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2011) * config/tc-i386.c (i386_error): Add invalid_vsib_address and unsupported_vector_index_register. (cpu_arch): Add .avx2, .bmi2, .lzcnt and .invpcid. (check_VecOperands): New. (match_template): Call check_VecOperands. Handle invalid_vsib_address and unsupported_vector_index_register. (build_modrm_byte): Support VecSIB. Check register-only source operand when two source operands are swapped. (i386_index_check): Allow Xmm/Ymm index registers. * doc/c-i386.texi: Document avx2/.avx2, bmi2/.bmi2, lzcnt/.lzcnt and invpcid./invpcid. gas/testsuite/ 2011-06-10 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2011) * gas/i386/arch-10-1.l: Updated. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/arch-10.s: Add LZCNT to comments. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/arch-10-lzcnt.d: New. * gas/i386/avx-gather-intel.d: Likewise. * gas/i386/avx-gather.d: Likewise. * gas/i386/avx-gather.s: Likewise. * gas/i386/avx2-intel.d: Likewise. * gas/i386/avx2.d: Likewise. * gas/i386/avx2.s: Likewise * gas/i386/avx256int-intel.d: Likewise. * gas/i386/avx256int.d: Likewise. * gas/i386/avx256int.s: Likewise. * gas/i386/bmi2-intel.d: Likewise. * gas/i386/bmi2.d: Likewise. * gas/i386/bmi2.s: Likewise. * gas/i386/inval-invpcid.l:Likewise. * gas/i386/inval-invpcid.s: Likewise. * gas/i386/invpcid-intel.d: Likewise. * gas/i386/invpcid.d: Likewise. * gas/i386/invpcid.s: Likewise. * gas/i386/x86-64-arch-2-lzcnt.d: Likewise. * gas/i386/x86-64-avx-gather-intel.d: Likewise. * gas/i386/x86-64-avx-gather.d: Likewise. * gas/i386/x86-64-avx-gather.s: Likewise. * gas/i386/x86-64-avx2-intel.d: Likewise. * gas/i386/x86-64-avx2.d: Likewise. * gas/i386/x86-64-avx2.s: Likewise. * gas/i386/x86-64-avx256int-intel.d: Likewise. * gas/i386/x86-64-avx256int.d: Likewise. * gas/i386/x86-64-avx256int.s: Likewise. * gas/i386/x86-64-bmi2-intel.d: Likewise. * gas/i386/x86-64-bmi2.d: Likewise. * gas/i386/x86-64-bmi2.s: Likewise. * gas/i386/x86-64-inval-invpcid.l: Likewise. * gas/i386/x86-64-inval-invpcid.s: Likewise. * gas/i386/x86-64-invpcid-intel.d: Likewise. * gas/i386/x86-64-invpcid.d: Likewise. * gas/i386/x86-64-invpcid.s: Likewise. opcodes/ 2011-06-10 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2011) * i386-dis.c (XMGatherQ): New. * i386-dis.c (EXxmm_mb): New. (EXxmm_mb): Likewise. (EXxmm_mw): Likewise. (EXxmm_md): Likewise. (EXxmm_mq): Likewise. (EXxmmdw): Likewise. (EXxmmqd): Likewise. (VexGatherQ): Likewise. (MVexVSIBDWpX): Likewise. (MVexVSIBQWpX): Likewise. (xmm_mb_mode): Likewise. (xmm_mw_mode): Likewise. (xmm_md_mode): Likewise. (xmm_mq_mode): Likewise. (xmmdw_mode): Likewise. (xmmqd_mode): Likewise. (ymmxmm_mode): Likewise. (vex_vsib_d_w_dq_mode): Likewise. (vex_vsib_q_w_dq_mode): Likewise. (MOD_VEX_0F385A_PREFIX_2): Likewise. (MOD_VEX_0F388C_PREFIX_2): Likewise. (MOD_VEX_0F388E_PREFIX_2): Likewise. (PREFIX_0F3882): Likewise. (PREFIX_VEX_0F3816): Likewise. (PREFIX_VEX_0F3836): Likewise. (PREFIX_VEX_0F3845): Likewise. (PREFIX_VEX_0F3846): Likewise. (PREFIX_VEX_0F3847): Likewise. (PREFIX_VEX_0F3858): Likewise. (PREFIX_VEX_0F3859): Likewise. (PREFIX_VEX_0F385A): Likewise. (PREFIX_VEX_0F3878): Likewise. (PREFIX_VEX_0F3879): Likewise. (PREFIX_VEX_0F388C): Likewise. (PREFIX_VEX_0F388E): Likewise. (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise. (PREFIX_VEX_0F38F5): Likewise. (PREFIX_VEX_0F38F6): Likewise. (PREFIX_VEX_0F3A00): Likewise. (PREFIX_VEX_0F3A01): Likewise. (PREFIX_VEX_0F3A02): Likewise. (PREFIX_VEX_0F3A38): Likewise. (PREFIX_VEX_0F3A39): Likewise. (PREFIX_VEX_0F3A46): Likewise. (PREFIX_VEX_0F3AF0): Likewise. (VEX_LEN_0F3816_P_2): Likewise. (VEX_LEN_0F3819_P_2): Likewise. (VEX_LEN_0F3836_P_2): Likewise. (VEX_LEN_0F385A_P_2_M_0): Likewise. (VEX_LEN_0F38F5_P_0): Likewise. (VEX_LEN_0F38F5_P_1): Likewise. (VEX_LEN_0F38F5_P_3): Likewise. (VEX_LEN_0F38F6_P_3): Likewise. (VEX_LEN_0F38F7_P_1): Likewise. (VEX_LEN_0F38F7_P_2): Likewise. (VEX_LEN_0F38F7_P_3): Likewise. (VEX_LEN_0F3A00_P_2): Likewise. (VEX_LEN_0F3A01_P_2): Likewise. (VEX_LEN_0F3A38_P_2): Likewise. (VEX_LEN_0F3A39_P_2): Likewise. (VEX_LEN_0F3A46_P_2): Likewise. (VEX_LEN_0F3AF0_P_3): Likewise. (VEX_W_0F3816_P_2): Likewise. (VEX_W_0F3818_P_2): Likewise. (VEX_W_0F3819_P_2): Likewise. (VEX_W_0F3836_P_2): Likewise. (VEX_W_0F3846_P_2): Likewise. (VEX_W_0F3858_P_2): Likewise. (VEX_W_0F3859_P_2): Likewise. (VEX_W_0F385A_P_2_M_0): Likewise. (VEX_W_0F3878_P_2): Likewise. (VEX_W_0F3879_P_2): Likewise. (VEX_W_0F3A00_P_2): Likewise. (VEX_W_0F3A01_P_2): Likewise. (VEX_W_0F3A02_P_2): Likewise. (VEX_W_0F3A38_P_2): Likewise. (VEX_W_0F3A39_P_2): Likewise. (VEX_W_0F3A46_P_2): Likewise. (MOD_VEX_0F3818_PREFIX_2): Removed. (MOD_VEX_0F3819_PREFIX_2): Likewise. (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise. (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise. (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise. (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise. (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise. (VEX_LEN_0F3A0E_P_2): Likewise. (VEX_LEN_0F3A0F_P_2): Likewise. (VEX_LEN_0F3A42_P_2): Likewise. (VEX_LEN_0F3A4C_P_2): Likewise. (VEX_W_0F3818_P_2_M_0): Likewise. (VEX_W_0F3819_P_2_M_0): Likewise. (prefix_table): Updated. (three_byte_table): Likewise. (vex_table): Likewise. (vex_len_table): Likewise. (vex_w_table): Likewise. (mod_table): Likewise. (putop): Handle "LW". (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode, xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode, vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode. (OP_EX): Likewise. (OP_E_memory): Handle vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. (OP_XMM): Handle vex_vsib_q_w_dq_mode. (OP_VEX): Likewise. * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS, CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS. (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID. (opcode_modifiers): Add VecSIB. * i386-opc.h (CpuAVX2): New. (CpuBMI2): Likewise. (CpuLZCNT): Likewise. (CpuINVPCID): Likewise. (VecSIB128): Likewise. (VecSIB256): Likewise. (VecSIB): Likewise. (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid. (i386_opcode_modifier): Add vecsib. * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2011-06-09 PR gas/12861Nick Clifton2-20/+21
* config/tc-cr16.c (tc_gen_reloc): Remove unused local variable code. (check_cinv_options): Remove unused local variables. Make function void. (md_assemble): Remove unused local variable.
2011-06-092011-06-09 James Greenhalgh <james.greenhalgh@arm.com>Richard Earnshaw6-17/+49
* config/tc-arm.c (do_ldrd): Warn in unpredictable cases. 2011-06-09 James Greenhalgh <james.greenhalgh@arm.com> * gas/arm/ldrd-unpredicatble.d: New testcase. * gas/arm/ldrd-unpredicatble.s: Likewise. * gas/arm/ldrd-unpredicatble.l: Likewise.
2011-06-03Fix attributation of previous delta.Nick Clifton1-1/+1
2011-06-03 PR gas/12698Nick Clifton2-0/+12
* config/tc-arm.c (parse_psr): Set m_profile to false when assembling for any architecture.
2011-06-02 gas/Nathan Sidwell8-15/+249
* config/tc-arm.c (parse_address_main): Handle -0 offsets. (encode_arm_addr_mode_2): Set default sign of zero here ... (encode_arm_addr_mode_3): ... and here. (encode_arm_cp_address): ... and here. (md_apply_fix): Use default sign of zero here. gas/testsuite/ * gas/arm/inst.d: Adjust for signed zero offsets. * gas/arm/ldst-offset0.d: New test. * gas/arm/ldst-offset0.s: New test. * gas/arm/offset-1.d: New test. * gas/arm/offset-1.s: New test. ld/testsuite/ Adjust tests for zero offset formatting. * ld-arm/cortex-a8-fix-bcc-plt.d: Adjust. * ld-arm/farcall-arm-arm-pic-veneer.d: Adjust. * ld-arm/farcall-arm-thumb.d: Adjust. * ld-arm/farcall-group-size2.d: Adjust. * ld-arm/farcall-group.d: Adjust. * ld-arm/farcall-mix.d: Adjust. * ld-arm/farcall-mix2.d: Adjust. * ld-arm/farcall-mixed-lib-v4t.d: Adjust. * ld-arm/farcall-mixed-lib.d: Adjust. * ld-arm/farcall-thumb-arm-blx-pic-veneer.d: Adjust. * ld-arm/farcall-thumb-arm-pic-veneer.d: Adjust. * ld-arm/farcall-thumb-thumb.d: Adjust. * ld-arm/ifunc-10.dd: Adjust. * ld-arm/ifunc-3.dd: Adjust. * ld-arm/ifunc-4.dd: Adjust. * ld-arm/ifunc-5.dd: Adjust. * ld-arm/ifunc-6.dd: Adjust. * ld-arm/ifunc-7.dd: Adjust. * ld-arm/ifunc-8.dd: Adjust. * ld-arm/jump-reloc-veneers-long.d: Adjust. * ld-arm/tls-longplt-lib.d: Adjust. * ld-arm/tls-thumb1.d: Adjust. opcodes/ * arm-dis.c (print_insn_coprocessor): Explicitly print #-0 as address offset. (print_arm_address): Likewise. Elide positive #0 appropriately. (print_insn_arm): Likewise.
2011-06-02Fix spelling mistakes.Nick Clifton5-1767/+2018
2011-05-312011-05-31 Paul Brook <paul@codesourcery.com>Paul Brook9-2/+45
gas/ * config/tc-arm.c (arm_cpus): Add Cortex-R5. (arm_extensions): Allow idiv on ARMv7-R. * doc/c-arm.text: Update idiv extension restrictions. gas/testsuite/ * gas/arm/arm-idiv-bad.d: New test. * gas/arm/arm-idiv-bad.s: New test. * gas/arm/arm-idiv-bad.l: New test. * gas/arm/arm-idiv.d: New test. * gas/arm/arm-idiv.s: New test. include/ * opcode/arm.h (ARM_ARCH_V7R_IDIV): Define.
generated by cgit v1.1 at 2024-12-30 18:16:49 +0000