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2012-10-15Added the changelog for the previous commit.Yufeng Zhang1-0/+5
2012-10-15Added missing alignment check to load/store uimm12 immediate offset.Yufeng Zhang2-0/+3
opcodes/ * aarch64-opc.c (operand_general_constraint_met_p): Change to check the alignment of addr.offset.imm instead of that of shifter.amount for operand type AARCH64_OPND_ADDR_UIMM12. gas/testsuite/ * gas/aarch64/illegal-2.s: Add test case. * gas/aarch64/illegal-2.l: Likewise.
2012-10-14 * config/tc-hppa.c (pa_get_number): New.Dave Anglin2-43/+52
(pa_get_absolute_expression): Simplify. (pa_ip): Use pa_get_number instead of pa_get_absolute_expression to get SOP, SFU and COPR identifiers.
2012-10-14 * config/tc-hppa.c (pa_ip): Reject double floating point stores andDave Anglin2-1/+9
loads that reference the right half of a floating point register.
2012-10-14 * gas/hppa/basic/fmemLRbug.s: Remove double load and store instructionsDave Anglin3-56/+46
which reference the right half of a floating point register. * gas/hppa/basic/basic.exp: Adjust expected results.
2012-10-13 * config/tc-hppa.c (pa_ip): Limit unit conditions for uxor to thoseDave Anglin2-8/+17
not involving a carry.
2012-10-13 * gas/hppa/basic/unit.s: Remove uxor instructions with unit conditionDave Anglin4-92/+75
involving a carry. * gas/hppa/basic/unit2.s: Likewise. * gas/hppa/basic/basic.exp: Adjusted expected.
2012-10-12gas/Peter Bergner2-2/+6
* doc/as.texinfo (-mpwr4, -mpwr7): Fix option name typos.
2012-10-112012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>Richard Earnshaw5-104/+112
* arm-dis.c: Use preferred form of vrint instruction variants for disassembly. 2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gas/arm/armv8-a+fp.d: Use preferred form of vrint instruction variants for disassembly. * gas/arm/armv8-a+fp.s: Likewise. * gas/arm/armv8-a+simd.d: Likewise. * gas/arm/armv8-a+simd.s: Likewise.
2012-10-112012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>Richard Earnshaw15-35/+74
* config/tc-arm.c: Change condition code insertion for lds[hb] instructions from after the 2nd character to after the 3rd. (tCM): Remove macro. (TxCM): Likewise. (TxCM_): Likewise. (TCM): Likewise. 2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gas/arm/ldgesb-bad.d: New file. * gas/arm/ldgesb-bad.l: Likewise. * gas/arm/ldgesb-bad.s: Likewise. * gas/arm/ldgesh-bad.d: Likewise. * gas/arm/ldgesh-bad.l: Likewise. * gas/arm/ldgesh-bad.s: Likewise. * gas/arm/ldsgeb.d: Likewise. * gas/arm/ldsgeb.s: Likewise. * gas/arm/ldsgeb.l: Likewise. * gas/arm/ldsgeh.d: Likewise. * gas/arm/ldsgeh.s: Likewise. * gas/arm/ldsgeh.l: Likewise.
2012-10-09Add AMD bdver3 support.Nagajyothi Eggone9-1/+429
gas/ * config/tc-i386.c (cpu_arch): Add CPU_BDVER3_FLAGS. * doc/c-i386.texi: Add -march=bdver3 option. gas/testsuite/ * gas/i386/i386.exp: Run bdver3 test cases. * gas/i386/nops-1-bdver3.d: New. * gas/i386/arch-10-bdver3.d: New. * gas/i386/x86-64-nops-1-bdver3.d: New. * gas/i386/x86-64-arch-2-bdver3.d: New. opcodes/ * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS. * i386-init.h: Regenerated.
2012-10-05opcodes/Peter Bergner8-0/+513
* ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2; * ppc-opc.c (VBA): New define. (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot, mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics. gas/testsuite/ * gas/ppc/power7.d: Add tests for mfppr, mfppr32, mtppr and mtppr32. * gas/ppc/power7.s: Likewise. * gas/ppc/altivec.d: Add tests for all legacy Altivec instructions. * gas/ppc/altivec.s: Likewise. * gas/ppc/altivec2.d: New test file. * gas/ppc/altivec2.s: Likewise. * gas/ppc/ppc.exp: Run it.
2012-10-04 * v850-dis.c (disassemble): Place square parentheses around secondNick Clifton4-5/+15
register operand of clr1, not1, set1 and tst1 instructions. * config/tc-v850.c (v850_insert_operand): Use a static buffer for the error message. * gas/v850/v850e1.d: Fix expected disassembly of clr1, not1, set1 and tst1 insns.
2012-10-042012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel3-4/+9
* gas/s390/zarch-zEC12.d: Fix branch preload instructions. * gas/s390/zarch-zEC12.s: Likewise.
2012-10-04Commit missing files from last patch.Andreas Krebbel2-0/+104
2012-10-042012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel6-2/+18
* config/tc-s390.c (s390_parse_cpu): Add new option zEC12. * doc/as.texinfo: Document new option zEC12. * doc/c-s390.texi: Likewise. 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/s390.exp: Run zEC12 tests. * gas/s390/zarch-zEC12.d: New file. * gas/s390/zarch-zEC12.s: New file. 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-mkopc.c: Support new option zEC12. * s390-opc.c: Add new instruction formats. * s390-opc.txt: Add new instructions for zEC12. 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
2012-10-03* config/tc-rl78.c: Change line_separator to '@' so that '|' canDJ Delorie2-1/+8
be used in expressions.
2012-10-01 * write.c (chain_frchains_together_1): Reorder assertion to avoidAlan Modra2-2/+7
uninit warning.
2012-09-25Add missing Cpu flags in bd and bt coresH.J. Lu10-6/+104
gas/testsuite/ 2012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com> * gas/i386/arch-10-bdver1.d: New file to test bdver1 core. * gas/i386/x86-64-arch-2-bdver1.d: Likewise. * gas/i386/i386.exp: Run bdver1 testcases. * gas/i386/arch-10-bdver2.d: Updated -march flags. * gas/i386/arch-10-btver1.d: Likewise. * gas/i386/arch-10-btver2.d: Likewise. * gas/i386/x86-64-arch-2-bdver2.d: Likewise. * gas/i386/x86-64-arch-2-btver1.d: Likewise. * gas/i386/x86-64-arch-2-btver2.d: Likewise. opcodes/ 2012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com> * gas/i386/arch-10-bdver1.d: New file to test bdver1 core. * gas/i386/x86-64-arch-2-bdver1.d: Likewise. * gas/i386/i386.exp: Run bdver1 testcases. * gas/i386/arch-10-bdver2.d: Updated -march flags. * gas/i386/arch-10-btver1.d: Likewise. * gas/i386/arch-10-btver2.d: Likewise. * gas/i386/x86-64-arch-2-bdver2.d: Likewise. * gas/i386/x86-64-arch-2-btver1.d: Likewise. * gas/i386/x86-64-arch-2-btver2.d: Likewise.
2012-09-23gas/testsuite/Richard Sandiford21-0/+394
2012-09-23 Maciej W. Rozycki <macro@codesourcery.com> * gas/mips/hilo-diff-eb.d: New test. * gas/mips/hilo-diff-eb-n32.d: New test. * gas/mips/hilo-diff-eb-n64.d: New test. * gas/mips/hilo-diff-el.d: New test. * gas/mips/hilo-diff-el-n32.d: New test. * gas/mips/hilo-diff-el-n64.d: New test. * gas/mips/mips16@hilo-diff-eb.d: New test. * gas/mips/mips16@hilo-diff-eb-n32.d: New test. * gas/mips/mips16@hilo-diff-eb-n64.d: New test. * gas/mips/mips16@hilo-diff-el.d: New test. * gas/mips/mips16@hilo-diff-el-n32.d: New test. * gas/mips/mips16@hilo-diff-el-n64.d: New test. * gas/mips/micromips@hilo-diff-eb.d: New test. * gas/mips/micromips@hilo-diff-eb-n32.d: New test. * gas/mips/micromips@hilo-diff-eb-n64.d: New test. * gas/mips/micromips@hilo-diff-el.d: New test. * gas/mips/micromips@hilo-diff-el-n32.d: New test. * gas/mips/micromips@hilo-diff-el-n64.d: New test. * gas/mips/hilo-diff.s: New test source. * gas/mips/mips.exp: Run the new tests.
2012-09-23gas/Richard Sandiford12-123/+319
* config/tc-mips.h (TC_FORCE_RELOCATION): Remove comment. * config/tc-mips.c (calculate_reloc): New function. (append_insn): Use it. Do not resolve compound relocations here. (mips16_macro_build, mips16_ip): Use calculate_reloc. (mips16_immed_extend): New function, split out from... (mips16_immed): ...here. (mips_frob_file): Handle null symbols. (mips_force_relocation): Remove NEWABI handling. (read_reloc_insn, write_reloc_insn): New functions. (md_apply_fix): Report TLS relocations against constants. Use read_reloc_insn, calculate_reloc and write_reloc_insn. Report relocations against constants that can't be resolved at assembly time. gas/testsuite/ * gas/mips/elf-rel22.s, gas/mips/elf-rel22.d: Add more tests. * gas/mips/elf-rel29.s, gas/mips/elf-rel29.d, gas/mips/micromips@elf-rel29.d, gas/mips/elf-rel30.s, gas/mips/elf-rel30.l: New tests. * gas/mips/mips.exp: Run them.
2012-09-23gas/Richard Sandiford2-2/+8
2012-09-23 Maciej W. Rozycki <macro@codesourcery.com> * config/tc-mips.c (append_insn) <BFD_RELOC_MIPS_JMP>: Don't mark as incomplete for constant expressions. <BFD_RELOC_MIPS16_JMP>: Likewise.
2012-09-23gas/Richard Sandiford9-38/+158
2012-09-23 Richard Sandiford <rdsandiford@googlemail.com> Maciej W. Rozycki <macro@codesourcery.com> * config/tc-mips.h (mips_record_label): Delete. (mips_add_dot_label): Declare. (tc_new_dot_label): Use it. * config/tc-mips.c (mips_assembling_insn): New variable. (md_assemble): Call mips_mark_labels. Set mips_assembling_insn while the main part of the function is executing. (mips_compressed_mark_label): New function, split out from... (mips_compressed_mark_labels): ...here. (append_insn): Don't call mips_mark_labels here. (mips_record_label): Make local. (mips_add_dot_label): New function. gas/testsuite/ * gas/mips/dot-1.s, gas/mips/dot-1.d, gas/mips/micromips@dot-1.d, gas/mips/mips16@dot-1.d: New test. * gas/mips/mips.exp: Run it.
2012-09-23Fix typo in previous commit.Richard Sandiford1-1/+1
2012-09-23gas/Richard Sandiford2-23/+49
* config/tc-mips.c (SEXT_16BIT): New macro. (mips16_immed): Take the reloc type as a parameter. Do not impose a signed vs. unsigned distinction on the value when a relocation operator was used. (mips16_macro_build, mips16_ip, md_convert_frag): Pass the reloc type to mips16_immed. (macro): Use SEXT_16BIT.
2012-09-23gas/Richard Sandiford2-144/+115
* config/tc-mips.c (read_insn, write_insn, read_compressed_insn): New functions. (install_insn, md_apply_fix, md_convert_frag, mips_handle_align): Use them, and write_compressed_insn.
2012-09-23gas/Richard Sandiford2-114/+107
* config/tc-mips.c (mips_cl_insn): Remove use_extend and extend. (MIPS16_EXTEND): New macro. (mips16_opcode_length): New function. (insn_length): Use it. (create_insn): Update after mips_cl_insn change. (write_compressed_insn): New function. (install_insn): Use it. (append_insn): Use insn_length to check for unextended MIPS16 instructions. (mips16_macro_build): Update call to mips16_immed. (mips16_ip): Likewise. Use MIPS16_EXTEND to force an extended instruction. (mips16_immed): Remove use_extend and extend; install EXTEND opcodes in the upper 16 bits of *INSN instead. Keep the instruction extended if it already is. Replace warn, small and ext with a forced_insn_length-like parameter. (md_convert_frag): Update call mips16_immed. Use write_compressed_insn.
2012-09-20Add x86-64-arch-2-1/x86-64-arch-2-2 testsH.J. Lu6-0/+206
* gas/i386/i386.exp: Run x86-64-arch-2-1 and x86-64-arch-2-2. * gas/i386/x86-64-arch-2-1.l: New file. * gas/i386/x86-64-arch-2-1.s: Likewise. * gas/i386/x86-64-arch-2-2.l: Likewise. * gas/i386/x86-64-arch-2-2.s: Likewise.
2012-09-20Replace CpuSSE3 with CpuCX16 for cmpxchg16bH.J. Lu12-7/+35
gas/ * config/tc-i386.c (cpu_arch): Add .cx16. * doc/c-i386.texi: Document .cx16. gas/testsuite/ * gas/i386/x86-64-arch-2.s: Add test for cmpxchg16b. * gas/i386/x86-64-arch-2.d: Update correspondingly. * gas/i386/x86-64-arch-2-bdver2.d: Likewise. * gas/i386/x86-64-arch-2-btver1.d: Likewise. * gas/i386/x86-64-arch-2-btver2.d: Likewise. * gas/i386/x86-64-arch-2-lzcnt.d: Likewise. * gas/i386/x86-64-arch-2-prefetchw.d: Likewise. * gas/i386/ilp32/x86-64-arch-2.d: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS, CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS, CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS, CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS. (cpu_flags): Add CpuCX16. * i386-opc.h (CpuCX16): New. (i386_cpu_flags): Add cpucx16. * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b. * i386-tbl.h: Regenerate. * i386-init.h: Likewise.
2012-09-19Fix spacing in last checkin.Steve Ellcey1-1/+1
2012-09-192012-09-19 Steve Ellcey <sellcey@mips.com>Steve Ellcey2-1/+5
* configure.tgt: Add mips*-mti-elf* target.
2012-09-182012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>Richard Earnshaw9-358/+373
opcodes: * arm-dis.c: Changed ldra and strl-form mnemonics to lda and stl-form. gas: * config/tc-arm.c: Changed ldra and strl-form mnemonics to lda and stl-form for armv8. gas/testsuite: * gas/arm/armv8-a-bad.l: Updated for changed mnemonics. * gas/arm/armv8-a-bad.s: Likewise. * gas/arm/armv8-a.d: Likewise. * gas/arm/armv8-a.s: Likewise. * gas/arm/inst.s: Added test for ldrt encoding compatibly with ldralt. * gas/arm/inst.d: Updated.
2012-09-18 opcodes/Maciej W. Rozycki5-22/+29
* micromips-opc.c (micromips_opcodes): Correct the encoding of the "swxc1" instruction. gas/testsuite/ * gas/mips/micromips.d: Correct the disassembly of SWXC1. * gas/mips/micromips-trap.d: Likewise. * gas/mips/micromips@24k-triple-stores-1.d: Likewise. * gas/mips/micromips@mips4-fp.d: Likewise.
2012-09-172012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>Richard Earnshaw9-7/+20
gas: * config/tc-aarch64.c (aarch64_archs): Rename 'armv8' to 'armv8-a'. gas/testsuite: * gas/aarch64/crypto.d (#as): Update for v8->v8-A change. * gas/aarch64/int-insns.d (#as): Likewise. * gas/aarch64/legacy_reg_names.s (.arch): Likewise. * gas/aarch64/neon-not.s (.arch): Likewise. * gas/aarch64/neon-vfp-reglist-post.s (.arch): Likewise. * gas/aarch64/neon-vfp-reglist.s (.arch): Likewise.
2012-09-15 * configure: Regenerate.David Edelsohn2-2/+7
2012-09-13Bi-endian patches for moxieAnthony Green3-30/+104
2012-09-122012-09-11 Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com>Richard Earnshaw5-53/+127
bfd/ * bfd-in2.h: Regenerated. * elf64-aarch64.c (elf64_aarch64_howto_table): Add R_AARCH64_GOT_LD_PREL19 reloc to HOWTO. (elf64_aarch64_reloc_map): Add reloc entry. (aarch64_resolve_relocation): Likewise. (bfd_elf_aarch64_put_addend): Likewise. (aarch64_reloc_got_type): Likewise. (elf64_aarch64_final_link_relocate): Likewise. (lf64_aarch64_check_relocs): Likewise. (elf64_aarch64_check_relocs): New case for R_AARCH64_ADR_PREL_LO21 reloc. * libbfd.h: Regenerated. * reloc.c (R_AARCH64_GOT_LD_PREL19): New reloc. gas/ * config/tc-aarch64.c (reloc_table): Add reloc to table entry. (parse_address_main): Add support for #:<reloc_op>:<symbol>. (parse_operands): Check for unused reloc. (md_apply_fix): New case for reloc. (aarch64_force_relocation): Likewise. gas/testsuite * gas/aarch64/reloc-insn.d (BFD_RELOC_AARCH64_GOT_LD_PREL19): Add expected asm for new reloc test. * gas/aarch64/reloc-insn.s (BFD_RELOC_AARCH64_GOT_LD_PREL19): Add test for reloc. include/ * elf/aarch64.h (R_AARCH64_GOT_LD_PREL19): New reloc. ld/testsuite * ld-aarch64/aarch64-elf.exp: New reloc tests. * ld-aarch64/emit-relocs-309-low-bad.d: New file. Expected asm for test failure (lower bound overflow). * ld-aarch64/emit-relocs-309-low.d: New file. Expected asm for test success (lower bound). * ld-aarch64/emit-relocs-309-up-bad.d: New file. Expected asm for test failure (upper bound overflow). * ld-aarch64/emit-relocs-309-up.d: New file. Expected asm for test success (upper bound). * ld-aarch64/emit-relocs-309.s: New file. Asm for new reloc tests.
2012-09-11 PR gas/13503Denis Chertykov2-1/+11
* config/tc-avr.h (TC_VALIDATE_FIX): Skip: BFD_RELOC_AVR_8_LO, BFD_RELOC_AVR_8_HI, BFD_RELOC_AVR_8_HLO.
2012-09-11 * Makefile.am (bootstrap): Add $EXEEXT to dependency.Alan Modra3-2/+7
* Makefile.in: Regenerate.
2012-09-10 * config.in: Disable sanity check for kfreebsd.Alan Modra2-1/+5
2012-09-10Regenerate binutils configureH.J. Lu2-7/+18
bfd/ 2012-09-10 H.J. Lu <hongjiu.lu@intel.com> * configure: Regenerated. binutils/ 2012-09-10 H.J. Lu <hongjiu.lu@intel.com> * configure: Regenerated. etc/ 2010-11-20 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> * Makefile.in (install-strip): New target. gas/ 2012-09-10 H.J. Lu <hongjiu.lu@intel.com> * configure: Regenerated. gold/ 2012-09-09 Alan Modra <amodra@gmail.com> * target.h (Target::gc_mark_symbol, do_gc_mark_symbol): New functions. gprof/ 2012-09-10 H.J. Lu <hongjiu.lu@intel.com> * configure: Regenerated. intl/ 2010-06-27 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> PR bootstrap/44621 ld/ 2012-09-10 H.J. Lu <hongjiu.lu@intel.com> * configure: Regenerated. libiberty/ 2011-08-28 H.J. Lu <hongjiu.lu@intel.com> * argv.c (dupargv): Replace malloc with xmalloc. Don't check opcodes/ 2012-09-10 H.J. Lu <hongjiu.lu@intel.com> * configure: Regenerated.
2012-09-08Change moxie branch target encodings.Anthony Green2-1/+7
2012-09-062012-09-06 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel3-14/+126
* config/tc-s390.c (set_highgprs_p): New variable. (s390_machinemode): New function. (md_pseudo_table): Add new pseudo command machinemode. (md_parse_option): Set set_highgprs_p to TRUE if -mzarch was specified on command line. (s390_elf_final_processing): Set the highgprs flag in the ELF header depending on set_highgprs_p. * doc/c-s390.texi: Document new pseudo machinemode.
2012-09-05 * doc/as.texinfo: Document -mvle.James Lemke2-1/+2
Missed with the original port commit. Committed as obvious / trivial.
2012-09-05* gas/doc/c-ppc.texi: Document -mvle.James Lemke2-0/+7
This was missing from the initial VLE port commit. Committed as obvious / trivial.
2012-09-04Add Intel Itanium Series 9500 supportH.J. Lu8-5/+2585
bfd/ 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> * cpu-ia64-opc.c (ins_cnt6a): New function. (ext_cnt6a): Ditto. (ins_strd5b): Ditto. (ext_strd5b): Ditto. (elf64_ia64_operands): Add new operand types. gas/ 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> * config/tc-ia64.c (reg_symbol): Add a new register. (indirect_reg): Ditto. (pseudo_func): Add new symbolic constants. (operand_match): Add new operand types recognition. (operand_insn): Add new register recognition. (md_begin): Add new register definition. (specify_resource): Add new register recognition. gas/testsuite/ 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> * gas/testsuite/gas/ia64/psn.d: New file. * gas/testsuite/gas/ia64/psn.s: New file. * gas/testsuite/gas/ia64/ia64.exp: Add new testcase. * gas/testsuite/gas/ia64/opc-i.d: Fixed failing tests. * gas/testsuite/gas/ia64/opc-m.d: Ditto. include/opcode/ 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> * ia64.h (ia64_opnd): Add new operand types. opcodes/ 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> * ia64-asmtab.h (completer_index): Extend bitfield to full uint. * ia64-gen.c: Promote completer index type to longlong. (irf_operand): Add new register recognition. (in_iclass_mov_x): Add an entry for the new mov_* instruction type. (lookup_specifier): Add new resource recognition. (insert_bit_table_ent): Relax abort condition according to the changed completer index type. (print_dis_table): Fix printf format for completer index. * ia64-ic.tbl: Add a new instruction class. * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions. * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions. * ia64-opc.h: Define short names for new operand types. * ia64-raw.tbl: Add new RAW resource for DAHR register. * ia64-waw.tbl: Add new WAW resource for DAHR register. * ia64-asmtab.c: Regenerate.
2012-09-01 PR gas/14521Hans-Peter Nilsson2-1/+18
* config/tc-mmix.h (tc_frob_file_before_fix): Renumber sections after call to mmix_frob_file.
2012-09-01 PR gas/14521Hans-Peter Nilsson3-0/+18
* gas/mmix/group-1.d, gas/mmix/group-1.s: New test.
2012-08-31 * doc/c-mips.texi (MIPS Opts): Correct a typo in the -mips5Maciej W. Rozycki2-1/+6
option.
2012-08-28Add support for constructing pc-relative addresses to the plt, byWalter Lee3-0/+84
adding the necessary assembly operators and relocations. bfd: * reloc.c (Add BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL, BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL, BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL, BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL, BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL, BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL, BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL, BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL, BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL, BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL, BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL, BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL, BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL, BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL): new relocations. * elfxx-tilegx.c (tilegx_elf_howto_table): Handle new relocations. (tilegx_reloc_map): Ditto. (reloc_to_create_func): Ditto. (tilegx_elf_check_relocs): Ditto. (tilegx_elf_gc_sweep_hook): Ditto. (tilegx_elf_relocate_section): Ditto. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas: * tc-tilegx.c (O_hw0_plt): Define operator. (O_hw1_plt): Ditto. (O_hw1_last_plt): Ditto. (O_hw2_last_plt): Ditto. (md_begin): Handle new operators. (emit_tilegx_instruction): Ditto. (md_apply_fix): Ditto. * doc/c-tilegx.texi: Document new operators. include/elf: * tilegx.h (R_TILEGX_IMM16_X0_HW0_PLT_PCREL): New relocation. (R_TILEGX_IMM16_X1_HW0_PLT_PCREL): Ditto. (R_TILEGX_IMM16_X0_HW1_PLT_PCREL): Ditto. (R_TILEGX_IMM16_X1_HW1_PLT_PCREL): Ditto. (R_TILEGX_IMM16_X0_HW2_PLT_PCREL): Ditto. (R_TILEGX_IMM16_X1_HW2_PLT_PCREL): Ditto. (R_TILEGX_IMM16_X0_HW3_PLT_PCREL): Ditto. (R_TILEGX_IMM16_X1_HW3_PLT_PCREL): Ditto. (R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL): Ditto. (R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL): Ditto. (R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL): Ditto. (R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL): Ditto. (R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL ): Ditto. (R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL): Ditto.
generated by cgit v1.1 at 2024-12-04 22:26:41 +0000