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2018-09-13x86: Swap destination/source to encode VEX only if possibleH.J. Lu2-3/+9
When encoding VEX, we can swap destination and source only if there are more than 1 register operand. * config/tc-i386.c (build_vex_prefix): Swap destination and source only if there are more than 1 register operand.
2018-09-13x86: also allow D on 3-operand insnsJan Beulich2-19/+29
For now this is just for VMOVS{D,S}.
2018-09-13x86: use D attribute also for SIMD templatesJan Beulich6-9/+126
Various moves come in load and store forms, and just like on the GPR and FPU sides there would better be only one pattern. In some cases this is not feasible because the opcodes are too different, but quite a few cases follow a similar standard scheme. Introduce Opcode_SIMD_FloatD and Opcode_SIMD_IntD, generalize handling in operand_size_match() (reverse operand handling there simply needs to match "straight" operand one), and fix a long standing, but so far only latent bug with when to zap found_reverse_match. Also once again drop IgnoreSize where pointlessly applied to templates touched anyway as well as *word when redundant with Reg*.
2018-09-13x86: fold ILP32 output of "opts" testsJan Beulich5-1296/+12
The output is identical to that of the LP64 tests. No need to fully spell this out twice.
2018-09-13x86: improve operand reversalJan Beulich6-11/+970
In quite a few cases the .s suffix or {load} / {store} prefixes did not work as intended, or produced errors when they're supposed to be ignored when it is not possible to carry out the request. The change here re-purposes(?) the .s suffix to no longer mean "store" (if that's what 's' did stand for), since the forms used in the base templates are not consistently loads (and we unlikely want to change that). The pseudo prefixes will now fulfill what their names say, i.e. {load} now only ever produces a load form encoding (if available) while {store} only ever produces a store form one (again if available). This requires minimal test suite adjustments, while the majority of the changes there are simply additions.
2018-09-13x86: add code comment on deprecated status of pseudo-suffixesJan Beulich2-1/+7
2018-09-13x86-64: bndmk, bndldx, and bndstx don't allow RIP-relative addressingJan Beulich3-0/+14
2018-09-13Fix the use by the RL78 assembler of an uninitialised field in the expresion ↵Nick Clifton2-0/+22
structure. * dwarf2dbg.c (generic_dwarf2_emit_offset): Use memset to initialise expression structure. (set_or_check_view): Likewise. (out_set_addr): Likewise. (emit_fixed_inc_line_addr): Likewise. (relax_inc_line_addr): Likewise. (out_debug_line): Likewise. (out_debug_ranges): Likewise. (out_debug_aranges): Likewise. (out_debug_info): Likewise.
2018-09-06PR23570, AVR .noinit section defaults to PROGBITSAlan Modra2-19/+5
Revert commit 8744470deab and instead use the standard special_sections support. PR 23570 bfd/ * elf32-avr.c (elf_avr_special_sections): New. (elf_backend_special_sections): Define. gas/ * config/tc-avr.c: Revert 2018-09-03 change.
2018-09-04gas, sparc: Allow non-fpop2 instructions before floating point branchesDaniel Cederman5-5/+44
Sparc V8 does not allow fpop2 instructions (floating point comparisons) immediately before floating point branches. From the SPARC Architecture Manual Version 8, section B.22 "Branch on Floating-point Condition Codes Instructions": "If the instruction executed immediately before an FBfcc is an FPop2 instruction, the result of the FBfcc is undefined. Therefore, at least one non FPop2 instruction should be executed between the FPop2 instruction and the FBfcc instruction." The existing check in GAS, however, does not allow any kind of floating point instruction before the branch. This patch adds an extra condition to only disallow fpop2 instructions. gas/ChangeLog: 2018-09-04 Daniel Cederman <cederman@gaisler.com> * config/tc-sparc.c (md_assemble): Allow non-fpop2 instructions before floating point branches for Sparc V8 and earlier. * testsuite/gas/sparc/sparc.exp: Execute the new test. * testsuite/gas/sparc/v8branch.d: New test. * testsuite/gas/sparc/v8branch.s: New test.
2018-09-03Change the .section directive for the AVR assembler so that the .noinit ↵Nick Clifton2-0/+26
section is always given the ELF NOBITS section type. PR gas/23570 * config/tc-avr.c (md_pseudo_table): Add entry for "secction". (avr_set_section): New function. Ensures that the .noinit section gets the NOBITS ELF section type.
2018-08-31RISC-V: Correct the requirement of compressed floating point instructionsJim Wilson4-0/+15
2018-08-31 Kito Cheng <kito@andestech.com> gas/ * testsuite/gas/riscv/c-fld-fsd-fail.d: New. * testsuite/gas/riscv/c-fld-fsd-fail.l: Likewise. * testsuite/gas/riscv/c-fld-fsd-fail.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for compressed floating point instructions.
2018-08-31gas/elf/section14.d: Change skip to xfailH.J. Lu3-1/+16
We will get an XPASS when h8300 port peculiarities are fixed, and will fix the testsuite too. * testsuite/gas/elf/section14.d: Change skip to xfail. * testsuite/lib/gas-defs.exp (run_dump_test): Add xfail support.
2018-08-31PowerPC64 higher REL16 relocationsAlan Modra3-13/+51
There are occasions where someone might want to build a 64-bit pc-relative offset from 16-bit pieces. This adds the necessary REL16 relocs corresponding to existing ADDR16 relocs that can be used to build 64-bit absolute values. include/ * elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA), (R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA), (R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define. (R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value. bfd/ * reloc.c (BFD_RELOC_PPC64_REL16_HIGH, BFD_RELOC_PPC64_REL16_HIGHA), (BFD_RELOC_PPC64_REL16_HIGHER, BFD_RELOC_PPC64_REL16_HIGHERA), (BFD_RELOC_PPC64_REL16_HIGHEST, BFD_RELOC_PPC64_REL16_HIGHESTA): Define. * elf64-ppc.c (ppc64_elf_howto_raw): Add new REL16 howtos. (ppc64_elf_reloc_type_lookup): Translate new REL16 relocs. (ppc64_elf_check_relocs, ppc64_elf_relocate_section): Handle them. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Allow ADDR16 HIGH, HIGHA, HIGHER, HIGHERA, HIGHEST, and HIGHESTA relocs. Group 16-bit relocs. * config/tc-ppc.c (md_apply_fix): Translate those ADDR16 relocs to REL16 when pcrel. Sort relocs.
2018-08-31gas: Pass -mx86-used-note=no to assemblerH.J. Lu2-1/+10
Since x86 assembler may generate .note.gnu.property section, pass -mx86-used-note=no to assembler for section2 test on ELF/x86 targets to avoid .note.gnu.property section. * testsuite/gas/elf/elf.exp: Pass -mx86-used-note=no to assembler for section2 test on ELF/x86 targets.
2018-08-31x86: pass -mx86-used-note=no to assemblerH.J. Lu2-0/+6
Since cfi/cfi-label.d is ELF/x86 specific, we can pass -mx86-used-note=no to assembler. * testsuite/gas/cfi/cfi-label.d: Pass -mx86-used-note=no to assembler.
2018-08-31x86: Add explicit -mx86-used-note=[yes|no] to testsH.J. Lu19-1/+39
Pass explicit -mx86-used-note=[yes|no] to x86 assembler and update expected outputs from "readelf -n" if needed. binutils/ * testsuite/binutils-all/i386/compressed-1b.d: Pass -mx86-used-note=no to assembler. * testsuite/binutils-all/i386/compressed-1c.d: Likewise. * testsuite/binutils-all/x86-64/compressed-1b.d: Likewise. * testsuite/binutils-all/x86-64/compressed-1c.d: Likewise. * testsuite/binutils-all/i386/empty.d: Pass -mx86-used-note=yes to assembler and update expected output from "readelf -n". * testsuite/binutils-all/i386/ibt.d: Likewise. * testsuite/binutils-all/i386/pr21231a.d: Likewise. * testsuite/binutils-all/i386/pr21231b.d: Likewise. * testsuite/binutils-all/i386/shstk.d: Likewise. * testsuite/binutils-all/x86-64/empty-x32.d: Likewise. * testsuite/binutils-all/x86-64/empty.d: Likewise. * testsuite/binutils-all/x86-64/ibt-x32.d: Likewise. * testsuite/binutils-all/x86-64/ibt.d: Likewise. * testsuite/binutils-all/x86-64/pr21231a.d: Likewise. * testsuite/binutils-all/x86-64/pr21231b.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a.d: Likewise. * testsuite/binutils-all/x86-64/pr23494b-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494b.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e.d: Likewise. * testsuite/binutils-all/x86-64/shstk-x32.d: Likewise. * testsuite/binutils-all/x86-64/shstk.d: Likewise. gas/ * testsuite/gas/i386/bss.d: Pass -mx86-used-note=no to assembler. * testsuite/gas/i386/ilp32/quad.d: Likewise. * testsuite/gas/i386/ilp32/reloc64.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-size-1.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-size-3.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-size-5.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-unwind.d: Likewise. * testsuite/gas/i386/property-1.d: Likewise. * testsuite/gas/i386/relax.d: Likewise. * testsuite/gas/i386/reloc64.d: Likewise. * testsuite/gas/i386/size-1.d: Likewise. * testsuite/gas/i386/size-3.d: Likewise. * testsuite/gas/i386/x86-64-property-1.d: Likewise. * testsuite/gas/i386/x86-64-size-1.d: Likewise. * testsuite/gas/i386/x86-64-size-3.d: Likewise. * testsuite/gas/i386/x86-64-size-5.d: Likewise. * testsuite/gas/i386/x86-64-unwind.d: Likewise. * testsuite/gas/i386/divide.d: Append "#pass". ld/ * testsuite/ld-i386/i386.exp: (ASFLAGS): Save, append -mx86-used-note=no and restore. Pass -mx86-used-note=yes and -mx86-used-note=no to assembler. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-i386/no-plt.exp: Pass -mx86-used-note=yes to assembler. * testsuite/ld-i386/tls.exp: Likewise. * testsuite/ld-x86-64/no-plt.exp: Likewise. * testsuite/ld-x86-64/tls.exp: Likewise. * testsuite/ld-i386/pr23486a.d: Pass -mx86-used-note=no to assembler. * testsuite/ld-i386/pr23486b.d: Likewise. * testsuite/ld-x86-64/bnd-branch-1-now.d: Likewise. * testsuite/ld-x86-64/bnd-ifunc-1-now.d: Likewise. * testsuite/ld-x86-64/bnd-ifunc-2-now.d: Likewise. * testsuite/ld-x86-64/bnd-ifunc-2.d: Likewise. * testsuite/ld-x86-64/bnd-plt-1-now.d: Likewise. * testsuite/ld-x86-64/bnd-plt-1.d: Likewise. * testsuite/ld-x86-64/pr23486a-x32.d: Likewise. * testsuite/ld-x86-64/pr23486a.d: Likewise. * testsuite/ld-x86-64/pr23486b-x32.d: Likewise. * testsuite/ld-x86-64/pr23486b.d: Likewise. * testsuite/ld-i386/property-x86-3.d: Pass -mx86-used-note=yes to assembler and update expected output from "readelf -n". * testsuite/ld-i386/property-x86-4a.d: Likewise. * testsuite/ld-i386/property-x86-ibt1a.d: Likewise. * testsuite/ld-i386/property-x86-ibt1b.d: Likewise. * testsuite/ld-i386/property-x86-ibt2.d: Likewise. * testsuite/ld-i386/property-x86-ibt3a.d: Likewise. * testsuite/ld-i386/property-x86-ibt3b.d: Likewise. * testsuite/ld-i386/property-x86-ibt4.d: Likewise. * testsuite/ld-i386/property-x86-ibt5.d: Likewise. * testsuite/ld-i386/property-x86-shstk1a.d: Likewise. * testsuite/ld-i386/property-x86-shstk1b.d: Likewise. * testsuite/ld-i386/property-x86-shstk2.d: Likewise. * testsuite/ld-i386/property-x86-shstk3a.d: Likewise. * testsuite/ld-i386/property-x86-shstk3b.d: Likewise. * testsuite/ld-i386/property-x86-shstk4.d: Likewise. * testsuite/ld-i386/property-x86-shstk5.d: Likewise. * testsuite/ld-x86-64/property-x86-3-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-3.d: Likewise. * testsuite/ld-x86-64/property-x86-4a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-4a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5.d: Likewise. * testsuite/ld-i386/property-1a.r: New file. * testsuite/ld-i386/property-2a.r: Likewise. * testsuite/ld-i386/property-3a.r: Likewise. * testsuite/ld-i386/property-4a.r: Likewise. * testsuite/ld-i386/property-5a.r: Likewise. * testsuite/ld-i386/property-7a.r: Likewise. * testsuite/ld-x86-64/property-1a.r: Likewise. * testsuite/ld-x86-64/property-2a.r: Likewise. * testsuite/ld-x86-64/property-3a.r: Likewise. * testsuite/ld-x86-64/property-4a.r: Likewise. * testsuite/ld-x86-64/property-5a.r: Likewise. * testsuite/ld-x86-64/property-7a.r: Likewise. * testsuite/ld-x86-64/mpx.exp: Pass -mx86-used-note=no to assembler.
2018-08-31x86: Extend assembler to generate GNU property notesH.J. Lu8-14/+385
Add -mx86-used-note=[yes|no] option to generate (or not) GNU property notes with GNU_PROPERTY_X86_FEATURE_2_USED and GNU_PROPERTY_X86_ISA_1_USED properties. If the assembly input contains no instructions, set the GNU_PROPERTY_X86_UINT32_VALID bit in GNU_PROPERTY_X86_FEATURE_2_USED property. Add a --enable-x86-used-note configure time option to set the default behavior. Set the default if the configure option is not used to "no". * NEWS: Mention -mx86-used-note=[no|yes]. * configure.ac: Add --enable-x86-used-note. Define DEFAULT_X86_USED_NOTE. * config.in: Regenerated. * configure: Likewise. * config/tc-i386.c (x86_isa_1_used): New. (x86_feature_2_used): Likewise. (x86_used_note): Likewise. (_i386_insn): Add has_regmmx, has_regxmm, has_regymm and has_regzmm. (build_modrm_byte): Set i.has_regmmx, i.has_regzmm. i.has_regymm and i.has_regxmm. (x86_cleanup): New function. (output_insn): Update x86_isa_1_used and x86_feature_2_used. (OPTION_X86_USED_NOTE): New. (md_longopts): Add -mx86-used-note=. (md_parse_option): Handle OPTION_X86_USED_NOTE. (md_show_usage): Display -mx86-used-note=. * config/tc-i386.h (x86_cleanup): New prototype. (md_cleanup): New. * doc/c-i386.texi: Document -mx86-used-note=.
2018-08-30sparc: gas: leon.d: disassemble assuming v8 also in sparc64 targets.Jose E. Marchesi2-1/+6
gas/ChangeLog: 2018-08-30 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/sparc/leon.d: Disassemble v8 code also in sparc64 targets.
2018-08-30RISC-V: Allow instruction require more than one extensionJim Wilson2-11/+32
2018-08-29 Kito Cheng <kito@andestech.com> gas/ * config/tc-riscv.c (riscv_subset_supports): New argument: xlen_required. (riscv_multi_subset_supports): New function, able to check more than one extension. (riscv_ip): Use riscv_multi_subset_supports instead of riscv_subset_supports. (riscv_set_arch): Update call-site for riscv_subset_supports. (riscv_after_parse_args): Likewise. include/ *opcode/riscv.h (MAX_SUBSET_NUM): New. (riscv_opcode): Add xlen_requirement field and change type of subset. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Check XLEN by riscv_opcode.xlen_requirement. * riscv-opc.c (riscv_opcodes): Update for struct change.
2018-08-30Skip elf/section14 test for h8300 targetsH.J. Lu2-0/+7
Skip elf/section14 test for h8300 targets since the h8300 port issues a warning message for new sections created without atrributes. * testsuite/gas/elf/section14.d: Skip h8300 targets.
2018-08-30Treat SHT_FINI_ARRAY and SHT_PREINIT_ARRAY as relocatable sectionsH.J. Lu4-0/+35
Since SHT_FINI_ARRAY and SHT_PREINIT_ARRAY sections are relocatable, this patch fixes readelf and adds a testcase. binutils/ * readelf.c (process_section_headers): Treat SHT_FINI_ARRAY and SHT_PREINIT_ARRAY as relocatable sections. gas/ * testsuite/gas/elf/elf.exp: Run section14. * testsuite/gas/elf/section14.d: New file. * testsuite/gas/elf/section14.s: Likewise.
2018-08-29sparc/leon: add support for partial write psr instructionMartin Aberg4-0/+26
Partial write %PSR (PWRPSR) is a SPARC V8e option that allows the WRPSR instruction to only affect the %PSR.ET field. When available it is enabled by setting the rd field of the WRPSR instruction to a value other than 0. For Leon processors with support for partial write %PSR (currently GR740 and GR716) the rd value must be 1. opcodes/ChangeLog: 2018-08-29 Martin Aberg <maberg@gaisler.com> * sparc-opc.c (sparc_opcodes): Add Leon specific partial write psr (PWRPSR) instruction. gas/ChangeLog: 2018-08-29 Daniel Cederman <cederman@gaisler.com> * testsuite/gas/sparc/leon.d: New test. * testsuite/gas/sparc/leon.s: New test. * testsuite/gas/sparc/sparc.exp: Execute the pwrpsr test.
2018-08-29[MIPS] Add Loongson 2K1000 proccessor support.Chenghua Xu3-1/+11
bfd/ * archures.c (bfd_architecture): New machine bfd_mach_mips_gs264e. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_GS264E. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Map bfd_mach_mips_gs264e to bfd_mach_mips_gs464e extension. binutils/ * NEWS: Mention Loongson 2K1000 proccessor support. * readelf.c (get_machine_flags): Handle gs264e. elfcpp/ * mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E. (mips_cpu_info_table): Add gs264e descriptors. * doc/as.texi (march table): Add gs264e. include/ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E. * opcode/mips.h (CPU_XXX): New CPU_GS264E. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination gs264e and gs464e. opcodes/ * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
2018-08-29[MIPS] Add Loongson 3A2000/3A3000 proccessor support.Chenghua Xu3-1/+11
bfd/ * archures.c (bfd_architecture): New machine bfd_mach_mips_gs464e. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_GS464E. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Map bfd_mach_mips_gs464e to bfd_mach_mips_gs464 extension. binutils/ * NEWS: Mention Loongson 3A2000/3A3000 proccessor support. * readelf.c (get_machine_flags): Handle gs464e. elfcpp/ * mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E. (mips_cpu_info_table): Add gs464e descriptors. * doc/as.texi (march table): Add gs464e. include/ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E. * opcode/mips.h (CPU_XXX): New CPU_GS464E. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination gs464e and gs464. opcodes/ * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
2018-08-29[MIPS] Add Loongson 3A1000 proccessor support.Chenghua Xu5-6/+19
bfd/ * archures.c (bfd_architecture): Rename bfd_mach_mips_loongson_3a to bfd_mach_mips_gs464. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Likewise. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Likewise. (bfd_mips_isa_ext_mach): Likewise. (bfd_mips_isa_ext): Likewise. (print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A. binutils/ * NEWS: Mention Loongson 3A1000 proccessor support. * readelf.c (get_machine_flags): Rename loongson-3a to gs464. (print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A. elfcpp/ * mips.c (EF_MIPS_MACH): Rename E_MIPS_MACH_LS3A to E_MIPS_MACH_GS464. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Rename CPU_LOONGSON_3A to CPU_GS464. (mips_cpu_info_table): Add gs464 descriptors, Keep loongson3a as an alias of gs464 for compatibility. * doc/as.texi (march table): Rename loongson3a to gs464. * testsuite/gas/mips/loongson-3a-mmi.d: Set "ISA Extension" flag to None. gold/ * mips.cc (Mips_mach, add_machine_extensions, elf_mips_mach): Rename loongson3a to gs464. (mips_isa_ext_mach, mips_isa_ext): Delete loongson3a. (infer_abiflags): Use ases instead of isa_ext for infer ABI flags. (elf_mips_mach_name): Rename loongson3a to gs464. include/ * elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to E_MIPS_MACH_GS464. (AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A. * opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A. (CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464. * opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Rename loongson3a to gs464. opcodes/ * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep loongson3a as an alias of gs464 for compatibility. * mips-opc.c (mips_opcodes): Change Comments.
2018-08-29[MIPS/GAS] Add Loongson EXT2 Instructions support.Chenghua Xu8-1/+96
bfd/ * elfxx-mips.c (print_mips_ases): Add Loongson EXT2 extension. binutils/ * readelf.c (print_mips_ases): Add Loongson EXT2 extension. gas/ * NEWS: Mention Loongson EXTensions R2 (EXT2) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_EXT2 and OPTION_NO_LOONGSON_EXT2. (md_longopts): Likewise. (mips_ases): Define availability for EXT. (mips_convert_ase_flags): Map ASE_LOONGSON_EXT2 to AFL_ASE_LOONGSON_EXT2. (md_show_usage): Add help for -mloongson-ext2 and -mno-loongson-ext2. * doc/as.texi: Document -mloongson-ext2, -mno-loongson-ext2. * doc/c-mips.texi: Document -mloongson-ext2, -mno-loongson-ext2, .set loongson-ext2 and .set noloongson-ext2. * testsuite/gas/mips/loongson-ext2.d: New test. * testsuite/gas/mips/loongson-ext2.s: New test. * testsuite/gas/mips/mips.exp: Run loongson-ext2 test. include/ * elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2. * opcode/mips.h (ASE_LOONGSON_EXT2): New macro. opcodes/ * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext option. (print_mips_disassembler_options): Document -M loongson-ext. * mips-opc.c (LEXT2): New macro. (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
2018-08-29[MIPS/GAS] Split Loongson EXT Instructions from loongson3a.Chenghua Xu6-2/+58
bfd/ * elfxx-mips.c (infer_mips_abiflags): Use ases instead of isa_ext for infer ABI flags. (print_mips_ases): Add Loongson EXT extension. binutils/ * readelf.c (print_mips_ases): Add Loongson EXT extension. elfcpp/ * mips.h (AFL_ASE_LOONGSON_EXT): New enum. gas/ * NEWS: Mention Loongson EXTensions (EXT) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_EXT and OPTION_NO_LOONGSON_EXT. (md_longopts): Likewise. (mips_ases): Define availability for EXT. (mips_convert_ase_flags): Map ASE_LOONGSON_EXT to AFL_ASE_LOONGSON_EXT. (mips_cpu_info_table): Add ASE_LOONGSON_EXT for loongson3a. (md_show_usage): Add help for -mloongson-ext and -mno-loongson-ext. * doc/as.texi: Document -mloongson-ext, -mno-loongson-ext. * doc/c-mips.texi: Document -mloongson-ext, -mno-loongson-ext, .set loongson-ext and .set noloongson-ext. * testsuite/gas/mips/loongson-mmi.d: Add ASE flag. include/ * elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT. * opcode/mips.h (ASE_LOONGSON_EXT): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add EXT to loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-ext option. (print_mips_disassembler_options): Document -M loongson-ext. * mips-opc.c (IL3A): Delete. * mips-opc.c (LEXT): New macro. (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT instructions.
2018-08-29[MIPS/GAS] Split Loongson CAM Instructions from loongson3aChenghua Xu11-11/+102
bfd/ * elfxx-mips.c (print_mips_ases): Add CAM extension. binutils/ * readelf.c (print_mips_ases): Add CAM extension. gas/ * NEWS: Mention Loongson Content Address Memory (CAM) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_CAM and OPTION_NO_LOONGSON_CAM. (md_longopts): Likewise. (mips_ases): Define availability for CAM. (mips_convert_ase_flags): Map ASE_LOONGSON_CAM to AFL_ASE_LOONGSON_CAM. (mips_cpu_info_table): Add ASE_LOONGSON_CAM for loongson3a. (md_show_usage): Add help for -mloongson-cam and -mno-loongson-cam. * doc/as.texi: Document -mloongson-cam, -mno-loongson-cam. * doc/c-mips.texi: Document -mloongson-cam, -mno-loongson-cam, .set loongson-cam and .set noloongson-cam. * testsuite/gas/mips/loongson-3a-2.d: Move cam test to ... * testsuite/gas/mips/loongson-cam.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-3a-2.s: Move cam test to ... * testsuite/gas/mips/loongson-cam.s: Here. * testsuite/gas/mips/loongson-3a-mmi.d: Add ASE flag. * testsuite/gas/mips/mips.exp: Run loongson-cam test. include/ * elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM. * opcode/mips.h (ASE_LOONGSON_CAM): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add CAM to loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-cam option. (print_mips_disassembler_options): Document -M loongson-cam. * mips-opc.c (LCAM): New macro. (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM instructions.
2018-08-27x86: Don't mask out the GNU_PROPERTY_X86_UINT32_VALID bitH.J. Lu5-0/+57
Since only the GNU_PROPERTY_X86_UINT32_VALID bit may be set in data-only relocatable objects which don't contain any instructions, linker shouldn't mask out the GNU_PROPERTY_X86_UINT32_VALID bit when merging GNU_PROPERTY_X86_XXX bits. Otherwise, linker output doesn't contain GNU_PROPERTY_X86_XXX property with any data-only relocatable inputs. This patch keeps the GNU_PROPERTY_X86_UINT32_VALID bit and updates readelf to print "<None>" if GNU_PROPERTY_X86_XXX property only has the GNU_PROPERTY_X86_UINT32_VALID bit. bfd/ * elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Don't mask out the GNU_PROPERTY_X86_UINT32_VALID bit. binutils/ * readelf.c (decode_x86_isa): Print <None> if bitmask only contains the GNU_PROPERTY_X86_UINT32_VALID bit. (decode_x86_feature_1): Likewise. (decode_x86_feature_2): Likewise. (print_gnu_property_note): Don't mask out the GNU_PROPERTY_X86_UINT32_VALID bit. * testsuite/binutils-all/i386/pr21231b.d: Updated. * testsuite/binutils-all/x86-64/pr21231b.d: Likewise. gas/ * testsuite/gas/i386/i386.exp: Run property-1 and x86-64-property-1. * testsuite/gas/i386/property-1.d: New file. * testsuite/gas/i386/property-1.s: Likewise. * testsuite/gas/i386/x86-64-property-1.d: Likewise. ld/ * testsuite/ld-i386/i386.exp: Run property-x86-5. * testsuite/ld-i386/property-x86-5.d: New file. * testsuite/ld-x86-64/property-x86-5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-5.d: Likewise. * testsuite/ld-x86-64/property-x86-5a.s: Likewise. * testsuite/ld-x86-64/property-x86-5b.s: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run property-x86-5 and property-x86-5-x32.
2018-08-23RISC-V: Reject empty rouding mode and fence operand.Jim Wilson8-0/+34
gas/ 2018-08-23 Kito Cheng <kito@andestech.com> * config/tc-riscv.c (arg_lookup): Checking length before look up. * testsuite/gas/riscv/fence-fail.d: New file. * testsuite/gas/riscv/fence-fail.l: Likewise. * testsuite/gas/riscv/fence-fail.s: Likewise. * testsuite/gas/riscv/rouding-fail.d: Likewise. * testsuite/gas/riscv/rouding-fail.l: Likewise. * testsuite/gas/riscv/rouding-fail.s: Likewise.
2018-08-23Prune BFD warnings for unknown GNU propertiesH.J. Lu3-2/+21
When glibc is enabled with the new GNU_PROPERTY_X86_XXX bits: https://groups.google.com/forum/#!topic/x86-64-abi/-D05GQ3kWrA BFD will issue an unknown GNU property warning like warning: tmpdir/ld1: unsupported GNU_PROPERTY_TYPE (5) type: 0xc0010001 and ignore such GNU properties. This patch adds prune_warnings_extra to prune such warnings on release branches and updates prune_warnings to call prune_warnings_extra. binutils/ PR ld/23536 * Makefile.am (development.exp): New target. (EXTRA_DEJAGNU_SITE_CONFIG): New. (DISTCLEANFILES): Add development.exp. * Makefile.in: Regenerated. * testsuite/binutils-all/objcopy.exp (strip_test): Call prune_warnings to prune BFD output. (strip_test_with_saving_a_symbol): Likewise. (objcopy_test_without_global_symbol): Likewise. * testsuite/lib/binutils-common.exp (prune_warnings_extra): New proc. (prune_warnings): Likewise. gas/ PR ld/23536 * Makefile.am (development.exp): New target. (EXTRA_DEJAGNU_SITE_CONFIG): New. (DISTCLEANFILES): Add development.exp. * Makefile.in: Regenerated. ld/ PR ld/23536 * Makefile.am (development.exp): New target. (EXTRA_DEJAGNU_SITE_CONFIG): New. (DISTCLEANFILES): Add development.exp. * Makefile.in: Regenerated. * testsuite/ld-bootstrap/bootstrap.exp: Call prune_warnings to prune BFD output. * testsuite/ld-plugin/lto.exp: Likewise. * testsuite/lib/ld-lib.exp (prune_warnings): Removed. * testsuite/ld-elf/shared.exp: Allow "\n" in linker warnings.
2018-08-22Fix typo in changelog entry for handling of undocumnented Z80 SLI instruction.Nick Clifton1-1/+1
2018-08-22Re: Pack reloc_howto_structAlan Modra2-2/+6
Fix fallout when using gcc-4. * dw2gencfi.c (emit_expr_encoded, output_fde): Warning fixes.
2018-08-21Fix handling of undocumented SLL instruction for the Z80 target.Arnold Metselaar2-13/+40
* config/tc-z80.c: Correct treatment of undocumented instruction sli/sll. (emit_mr): Add argument unportable. (emit_bit): Adapt call to emit_mr. (emit_mr_z80): New function. (emit_mr_unportable): New function. (instab[]): Replace emit_mr with emit_mr_z80 or emit_mr_unportable as appropriate.
2018-08-21Fix invalid strcpy on unterminated bufferAndreas Schwab2-1/+7
* read.c (do_repeat_with_expander): Use memmove instead of strcpy on unterminated string buffer.
2018-08-21Use operand->extract to provide defaults for optional PowerPC operandsAlan Modra2-78/+81
Most optional operands to powerpc instructions use a default value of zero, but there are a few exceptions. Those have been handled by PPC_OPERAND_OPTIONAL_VALUE and an entry in the powerpc_operands table for the default value, smuggled in the shift field. This patch changes that to using the operand extract function to provide non-zero defaults. I've also moved the code determining whether optional operands are provided or omitted, to the point the first optional operand is seen, and allowed for the possibility of optional base register operands in a future patch. The patch does change the error you get on invalid assembly like ld 3,4 You'll now see "missing operand" rather than "syntax error; end of line, expected `('". gas/ * config/tc-ppc.c (md_assemble): Delay counting of optional operands until one is encountered. Allow for the possibility of optional base regs, ie. PPC_OPERAND_PARENS. Call ppc_optional_operand_value with extra args. include/ * opcode/ppc.h (struct powerpc_operand): Correct "insert" comment. Mention use of "extract" function to provide default value. (PPC_OPERAND_OPTIONAL_VALUE): Delete. (ppc_optional_operand_value): Rewrite to use extract function. opcodes/ * ppc-dis.c (operand_value_powerpc): Init "invalid". (skip_optional_operands): Count optional operands, and update ppc_optional_operand_value call. * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg. (extract_vlensi): Likewise. (extract_fxm): Return default value for missing optional operand. (extract_ls, extract_raq, extract_tbr): Likewise. (insert_sxl, extract_sxl): New functions. (insert_esync, extract_esync): Remove Power9 handling and simplify. (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE flag and extra entry. (powerpc_operands <SXL>): Likewise, and use insert_sxl and extract_sxl.
2018-08-21Fix s12z test regexpsAlan Modra2-6/+10
Fixes ERROR: tcl error sourcing .../gas/testsuite/gas/s12z/s12z.exp. ERROR: couldn't compile regular expression pattern: quantifier operand invalid run_dump_test expected output lines are regexps. * testsuite/gas/s12z/bit-manip-invalid.d: Correct regexps.
2018-08-20Tidy bit twiddlingAlan Modra1-3/+3
* sh-opc.h (MASK): Simplify.
2018-08-18Opcodes: (BRCLR / BRSET) Disassemble reserved codes instead of aborting.John Darrington4-0/+37
Bit manipulation instructions which are not normally generated by the assembler, should nevertheless be decoded by the disassembler. opcodes/ * s12z-dis.c: BM_RESERVED1 to behave like BM_OPR_REG, and BM_RESERVED0 like BM_REG_IMM.
2018-08-18S12Z: Move opcode header to public include directory.John Darrington1-1/+1
opcodes/ * s12z.h: Delete. * s12z-dis.c: Adjust path of included file. include/ * opcode/s12z.h: New file. gas/ * config/tc-s12z.c: Adjust path of included file.
2018-08-14x86-64: Display eiz for address with the addr32 prefixH.J. Lu7-14/+34
In 64-bit mode, display eiz for address with the addr32 prefix and without base nor index registers. For mov -0xccddef(,%eiz,), %rax disassembler now displays: 67 48 8b 04 25 11 22 33 ff mov -0xccddef(,%eiz,1),%rax instead of 67 48 8b 04 25 11 22 33 ff addr32 mov 0xffffffffff332211,%rax gas/ * testsuite/gas/i386/evex-no-scale-64.d: Updated. * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/x86-64-addr32.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise. * testsuite/gas/i386/x86-64-addr32.s: Add %eiz tests. opcodes/ * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for address with the addr32 prefix and without base nor index registers.
2018-08-14When the assembler reports that the input and output are the same, report ↵Robert Yang2-7/+24
the file names involved, in order to help debugging. Also do not equate two files are the same if the have the same inode value but reside on different file systems. * as.c (main): Improve check for input file matching output file.
2018-08-11x86: Add CpuCMOV and CpuFXSRH.J. Lu3-3/+20
There are separate CPUID feature bits for fxsave/fxrstor and cmovCC instructions. This patch adds CpuCMOV and CpuFXSR to replace Cpu686 on corresponding instructions. gas/ * config/tc-i386.c (cpu_arch): Add .cmov and .fxsr. (cpu_noarch): Add nocmov and nofxsr. * doc/c-i386.texi: Document cmov and fxsr. opcodes/ * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS, CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS. (cpu_flags): Add CpuCMOV and CpuFXSR. * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64, fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2018-08-10x86: Don't display --32/--64/--x32 without BFD64H.J. Lu3-3/+17
For 32-bit x86 assembler, --64 and --x32 are unsupported if BFD64 is undefined. Even if BFD64 is defined, --64 and --x32 still may not be supported if x86-64 support isn't compiled in: [hjl@gnu-hsw-1 gas]$ ./as-new --64 -o x.o x.s Assembler messages: Fatal error: no compiled in support for x86_64 [hjl@gnu-hsw-1 gas]$ ./as-new --x32 -o x.o x.s Assembler messages: Fatal error: no compiled in support for 32bit x86_64 [hjl@gnu-hsw-1 gas]$ This patch removes --32/--64/--x32 from md_show_usage if BFD64 is undefined and runs code64-inval only if BFD64 is undefined. * config/tc-i386.c (md_show_usage): Don't display --32/--64/--x32 if BFD64 is undefined. * testsuite/gas/i386/i386.exp (gas_bfd64_check): New. Run code64-inval if gas_bfd64_check fails.
2018-08-10x86: Replace evex-no-scale.s with evex-no-scale-[32|64].sH.J. Lu5-12/+16
.if is_64bit vmovaps -1024(%rip), %zmm0 vmovaps 64(,%rax), %zmm0 vmovaps 64(,%riz), %zmm0 .endif doesn't with i686-elf cross binutils on 64-bit hosts: evex-no-scale.s: Assembler messages: evex-no-scale.s:10: Error: bad register name `%rip)' evex-no-scale.s:11: Error: bad register name `%rax)' evex-no-scale.s:12: Error: bad register name `%riz)' This patch replaces evex-no-scale.s with evex-no-scale-32.s and evex-no-scale-64.s. * testsuite/gas/i386/evex-no-scale-32.d: Don't use evex-no-scale.s. * testsuite/gas/i386/evex-no-scale-64.d: Likewise. * testsuite/gas/i386/evex-no-scale-32.s: New file. * testsuite/gas/i386/evex-no-scale-64.s: Likewise. * testsuite/gas/i386/evex-no-scale.s: Removed.
2018-08-09as --help: Display default option for --elf-stt-common=H.J. Lu2-1/+10
* as.c (show_usage): Display default option for --elf-stt-common=.
2018-08-09x86: Display default x86-specific options for "as --help"H.J. Lu2-12/+31
* config/tc-i386.c (md_show_usage): Display default options.
2018-08-07Correct the parsing of derferred register addressing in the PDP11 assembler.James Patrick Conlon5-6/+49
PR 23481 * config/tc-pdp11.c (parse_op_noreg): Check for deferred register addressing before assuming non-deferred addressing. * testsuite/gas/pdp11/pr23481.s: New test source file. * testsuite/gas/pdp11/pr23481.d: New test driver file. * testsuite/gas/pdp11/pdp11.exp: Run the new test.
2018-08-06[ARC] Check if an input asm file is rf16 compliantclaziss5-0/+50
Check if an input asm file is rf16 compliant; if not, and the tag says otherwise, fix the tag and emit a warning. gas/ 2017-09-20 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (rf16_only): New static variable. (autodetect_attributes): Check if we are rf16 compliant. (arc_set_public_attributes): Fix and emit the warning is required. * testsuite/gas/arc/attr-rf16.d: New file. * testsuite/gas/arc/attr-rf16.err: Likewise. * testsuite/gas/arc/attr-rf16.s: Likewise.
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