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2018-08-06[ARC] Add Tag_ARC_ATR_version.claziss31-1/+69
Add a new tag (Tag_ARC_ATR_version) used to indicate if current attributes are interpreted in GNU way. This attribute is used by Synopsys custom compiler to correctly identify and interpret the object attributes section as generated by GNU tools. gas/ 2017-08-02 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (arc_set_public_attributes): Add Tag_ARC_ATR_version. (arc_convert_symbolic_attribute): Likewise. * testsuite/gas/arc/attr-arc600.d: Update test. * testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc600_norm.d: Likewise. * testsuite/gas/arc/attr-arc601.d: Likewise. * testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc601_mul64.d: Likewise. * testsuite/gas/arc/attr-arc601_norm.d: Likewise. * testsuite/gas/arc/attr-arc700.d: Likewise. * testsuite/gas/arc/attr-arcem.d: Likewise. * testsuite/gas/arc/attr-archs.d: Likewise. * testsuite/gas/arc/attr-autodetect-1.d: Likewise. * testsuite/gas/arc/attr-cpu-a601.d: Likewise. * testsuite/gas/arc/attr-cpu-a700.d: Likewise. * testsuite/gas/arc/attr-cpu-em.d: Likewise. * testsuite/gas/arc/attr-cpu-hs.d: Likewise. * testsuite/gas/arc/attr-em.d: Likewise. * testsuite/gas/arc/attr-em4.d: Likewise. * testsuite/gas/arc/attr-em4_dmips.d: Likewise. * testsuite/gas/arc/attr-em4_fpuda.d: Likewise. * testsuite/gas/arc/attr-em4_fpus.d: Likewise. * testsuite/gas/arc/attr-hs.d: Likewise. * testsuite/gas/arc/attr-hs34.d: Likewise. * testsuite/gas/arc/attr-hs38.d: Likewise. * testsuite/gas/arc/attr-hs38_linux.d: Likewise. * testsuite/gas/arc/attr-mul64.d: Likewise. * testsuite/gas/arc/attr-name.d: Likewise. * testsuite/gas/arc/attr-nps400.d: Likewise. * testsuite/gas/arc/attr-override-mcpu.d: Likewise. * testsuite/gas/arc/attr-quarkse_em.d: Likewise. bfd/ 2017-08-02 Claudiu Zissulescu <claziss@synopsys.com> * elf32-arc.c (arc_elf_merge_attributes): Handle Tag_ARC_ATR_version. binutils/ 2017-08-02 Claudiu Zissulescu <claziss@synopsys.com> * readelf.c (display_arc_attribute): Print Tag_ARC_ATR_version. include/ 2017-08-02 Claudiu Zissulescu <claziss@synopsys.com> * elf/arc.h (Tag_ARC_ATR_version): New tag. ld/ 2017-08-02 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/ld-arc/attr-merge-0.d: Update test. * testsuite/ld-arc/attr-merge-1.d: Likewise. * testsuite/ld-arc/attr-merge-2.d: Likewise. * testsuite/ld-arc/attr-merge-3.d: Likewise. * testsuite/ld-arc/attr-merge-5.d: Likewise.
2018-08-06[ARC] Update handling AUX-registers.claziss5-169/+18
Update aux-registers data-base, and accept aux-registers names with upper/lowercase names. opcode/ 2017-07-18 Claudiu Zissulescu <claziss@synopsys.com> * arc-regs.h: Update aux-registers. gas/ 2017-07-18 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (find_opcode_match): Accept uppercase aux-regs names. * testsuite/gas/arc/ld2.d: Update test. * testsuite/gas/arc/taux.d: Likewise. * testsuite/gas/arc/taux.s: Likewise. include/ 2017-07-18 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (ARC_OPCODE_ARCV1): Define.
2018-08-06x86: fold RegEip/RegRip and RegEiz/RegRizJan Beulich4-63/+45
This allows to simplify the code in a number of places.
2018-08-05x86: Update assembler tests for non-ELF targetsH.J. Lu6-2/+21
evex-no-scale.s has ELF directive: .section .probe, "", @progbits and non-ELF targets may pad text sections. * testsuite/gas/i386/i386.exp: Run evex-no-scale-32 and evex-no-scale-64 only for ELF targets. * testsuite/gas/i386/prefix32.s: Append ".p2align 4,0". * testsuite/gas/i386/prefix64.s: Likewise. * testsuite/gas/i386/prefix32.l: Updated. * testsuite/gas/i386/prefix64.l: Likewise.
2018-08-05R_PPC64_REL24_NOTOC supportAlan Modra2-0/+8
R_PPC64_REL24_NOTOC is used on calls like "bl foo@notoc" to tell the linker that linkage stubs for PLT calls or long branches can't use r2 for pic addressing. Instead, new stubs that generate pc-relative addresses are used. One complication is that pc-relative offsets to the PLT may need to be 64-bit in large programs, in contrast to the toc-relative addressing used by older PLT linkage stubs where a 32-bit offset is sufficient until the PLT itself exceeds 2G in size. .eh_frame info to cover the _notoc stubs is yet to be implemented. bfd/ * elf64-ppc.c (ADDI_R12_R11, ADDI_R12_R12, LIS_R12), (ADDIS_R12_R11, ORIS_R12_R12_0, ORI_R12_R12_0), (SLDI_R12_R12_32, LDX_R12_R11_R12, ADD_R12_R11_R12): Define. (ppc64_elf_howto_raw): Add R_PPC64_REL24_NOTOC entry. (ppc64_elf_reloc_type_lookup): Support R_PPC64_REL24_NOTOC. (ppc_stub_type): Add ppc_stub_long_branch_notoc, ppc_stub_long_branch_both, ppc_stub_plt_branch_notoc, ppc_stub_plt_branch_both, ppc_stub_plt_call_notoc, and ppc_stub_plt_call_both. (is_branch_reloc): Add R_PPC64_REL24_NOTOC. (build_offset, size_offset): New functions. (plt_stub_size): Support plt_call_notoc and plt_call_both. (ppc_build_one_stub, ppc_size_one_stub): Support new stubs. (toc_adjusting_stub_needed): Handle R_PPC64_REL24_NOTOC. (ppc64_elf_size_stubs): Likewise, and new stubs. (ppc64_elf_build_stubs, ppc64_elf_relocate_section): Likewise. * reloc.c: Add BFD_RELOC_PPC64_REL24_NOTOC. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.c (ppc_elf_suffix): Support @notoc. (ppc_force_relocation, ppc_fix_adjustable): Handle REL24_NOTOC. ld/ * testsuite/ld-powerpc/ext.d, * testsuite/ld-powerpc/ext.s, * testsuite/ld-powerpc/ext.lnk, * testsuite/ld-powerpc/notoc.d, * testsuite/ld-powerpc/notoc.s: New tests. * testsuite/ld-powerpc/powerpc.exp: Run them.
2018-08-03Update PRU assembler to corect hardware register numbering for DWARF.Dimitar Dimitrov3-6/+35
A small rework of the PRU GCC port exposed that CIE data alignment is erroneously set to 4 for PRU in GAS. In fact PRU stack must be aligned to 1. Set the macro to -1, to allow output from GCC to be assembled without errors. Also, while at it, set DWARF2 HW register numbering to follow latest * config/tc-pru.c (pru_regname_to_dw2regnum): Return the starting HW byte-register number. (pru_frame_initial_instructions): Use byte-numbering for FP index. * config/tc-pru.h (DWARF2_DEFAULT_RETURN_COLUMN): Use number from latest GCC. (DWARF2_CIE_DATA_ALIGNMENT): Set to -1.
2018-08-03x86: drop "mem" operand type attributeJan Beulich3-8/+24
No template specifies this bit, so there's no point recording it in the templates. Use a flags[] bit instead.
2018-08-01Fix bug in PDP11 assembler when handling a JSr instruction with deferred ↵James Patrick Conlon5-3/+57
auto increment. PR 14480 * config/tc-pdp11.c (parse_op_noreg): Check for and handle auto increment deferred. * testsuite/gas/pdp11/pr14480.d: New test driver file. * testsuite/gas/pdp11/pr14480.s: New test source file file. * testsuite/gas/pdp11/pdp11.exp: Run the new test.
2018-08-01Fix compile time warning problem with gcc 8 and the NS32K assembler sources.Nick Clifton2-1/+7
* config/tc-ns32k.c (addr_mode): Replace "Drop through" comment with "Fall through" so that it will be recognised by gcc's switch statment error checker.
2018-08-01csky regenAlan Modra2-0/+10
bfd/ * po/SRC-POTFILES.in: Regenerate. gas/ * po/POTFILES.in: Regenerate. ld/ * po/BLD-POTFILES.in: Regenerate. opcodes/ * po/POTFILES.in: Regenerate.
2018-07-31x86: also optimize KXOR{D,Q} and KANDN{D,Q}Jan Beulich6-1/+43
These can be converted to 2-byte VEX encoding when both source registers are the same, by using KXORW / KANDNW as replacement.
2018-07-31x86: fold various AVX512 templates with so far differing Masking attributesJan Beulich2-6/+37
There's no insn allowing ZEROING_MASKING alone. Re-purpose its value for handling the not uncommon case of insns allowing either form of masking with register operands, but only merging masking with a memory operand.
2018-07-31x86: add more exhaustive tests for invalid AVX512 zeroing-maskingJan Beulich3-0/+414
Before changing how things get handled, install a full set of tests, such that it can be demonstrated that the subsequent change doesn't break things.
2018-07-31x86/Intel: correct permitted operand sizes for AVX512 scatter/gatherJan Beulich10-507/+610
AVX gather insns correctly allow the element size to be specified rather than the full vector size. Make AVX512 ones match.
2018-07-31x86: don't abort() upon DATA16 prefix on (E)VEX encoded insnJan Beulich7-5/+142
Instead of hitting the abort() in output_insn() (commented by "There should be no other prefixes for instructions with VEX prefix"), report a proper diagnostic instead, just like we do e.g. for invalid REP prefixes.
2018-07-31x86: drop CpuVREXJan Beulich2-1/+6
It is fully redundant with CpuAVX512F.
2018-07-30x86: don't mistakenly scale non-8-bit displacementsJan Beulich6-1/+60
In commit b5014f7af2 I've removed (instead of replaced) a conditional, resulting in addressing forms not allowing 8-bit displacements to now get their displacements scaled under certain circumstances. Re-add the missing conditional.
2018-07-30Add support for the C_SKY series of processors.Andrew Jenner87-1/+10976
This patch series is a new binutils port for C-SKY processors, including support for both the V1 and V2 processor variants. V1 is derived from the MCore architecture while V2 is substantially different, with mixed 16- and 32-bit instructions, a larger register set, a different (but overlapping) ABI, etc. There is support for bare-metal ELF targets and Linux with both glibc and uClibc. This code is being contributed jointly by C-SKY Microsystems and Mentor Graphics. C-SKY is responsible for the technical content and has proposed Lifang Xia and Yunhai Shang as port maintainers. (Note that C-SKY does have a corporate copyright assignment on file with the FSF.) Mentor Graphics' role has been cleaning up the code, adding documentation and additional test cases, etc, to address issues we anticipated reviewers would complain about. bfd * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY. (BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise. * Makefile.in: Regenerated. * archures.c (enum bfd_architecture): Add bfd_arch_csky and related bfd_mach defines. (bfd_csky_arch): Declare. (bfd_archures_list): Add C-SKY. * bfd-in.h (elf32_csky_build_stubs): Declare. (elf32_csky_size_stubs): Declare. (elf32_csky_next_input_section: Declare. (elf32_csky_setup_section_lists): Declare. * bfd-in2.h: Regenerated. * config.bfd: Add C-SKY. * configure.ac: Likewise. * configure: Regenerated. * cpu-csky.c: New file. * elf-bfd.h (enum elf_target_id): Add C-SKY. * elf32-csky.c: New file. * libbfd.h: Regenerated. * reloc.c: Add C-SKY relocations. * targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare. (_bfd_target_vector): Add C-SKY target vector entries. binutils* readelf.c: Include elf/csky.h. (guess_is_rela): Handle EM_CSKY. (dump_relocations): Likewise. (get_machine_name): Likewise. (is_32bit_abs_reloc): Likewise. include * dis-asm.h (csky_symbol_is_valid): Declare. * opcode/csky.h: New file. opcodes * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c. * Makefile.in: Regenerated. * configure.ac: Add C-SKY. * configure: Regenerated. * csky-dis.c: New file. * csky-opc.h: New file. * disassemble.c (ARCH_csky): Define. (disassembler, disassemble_init_for_target): Add case for ARCH_csky. * disassemble.h (print_insn_csky, csky_get_disassembler): Declare. gas * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY. (TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise. * Makefile.in: Regenerated. * config/tc-csky.c: New file. * config/tc-csky.h: New file. * config/te-csky_abiv1.h: New file. * config/te-csky_abiv1_linux.h: New file. * config/te-csky_abiv2.h: New file. * config/te-csky_abiv2_linux.h: New file. * configure.tgt: Add C-SKY. * doc/Makefile.am (CPU_DOCS): Add entry for C-SKY. * doc/Makefile.in: Regenerated. * doc/all.texi: Set CSKY feature. * doc/as.texi (Overview): Add C-SKY options. (Machine Dependencies): Likewise. * doc/c-csky.texi: New file. * testsuite/gas/csky/*: New test cases. ld * Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations. (ecskyelf.c, ecskyelf_linux.c): New rules. * Makefile.in: Regenerated. * configure.tgt: Add C-SKY. * emulparams/cskyelf.sh: New file. * emulparams/cskyelf_linux.sh: New file. * emultempl/cskyelf.em: New file. * gen-doc.texi: Add C-SKY. * ld.texi: Likewise. (Options specific to C-SKY targets): New section. * testsuite/ld-csky/*: New tests.
2018-07-29Fix unwind offset for start_symbol.John David Anglin2-1/+9
* config/tc-hppa.c: Include "struc-symbol.h". (pa_build_unwind_subspace): Use call_info->start_symbol->sy_frag instead of frag_now for local symbol replacement.
2018-07-27RISC-V: Fix gas configure support for riscv*-*-*.Jim Wilson2-1/+5
gas/ * configure.tgt (riscv*): Accept as alias for riscv32*.
2018-07-27x86: Check for more than 2 memory referencesH.J. Lu6-0/+32
For movsd (%esi), %ss:(%edi), %ss:(%eax) we got [hjl@gnu-tools-1 tmp]$ as -o x.o x.s x.s: Assembler messages: x.s:1: Error: too many memory references for `movsd' munmap_chunk(): invalid pointer x.s:1: Internal error (Aborted). Please report this bug. [hjl@gnu-tools-1 tmp]$ struct _i386_insn has const seg_entry *seg[2]; 3 memory references will overflow the seg array. We should issue an error if there are more than 2 memory references. PR gas/23453 * config/tc-i386.c (parse_operands): Check for more than 2 memory references. * testsuite/gas/i386/inval.s: Add a movsd test with 3 memory references. * testsuite/gas/i386/x86-64-inval.s: Likewise. * testsuite/gas/i386/inval.l: Updated. * testsuite/gas/i386/x86-64-inval.l: Likewise.
2018-07-26x86: Initialize broadcast_op.bytes to 0H.J. Lu2-0/+6
* config/tc-i386.c (check_VecOperations): Initialize broadcast_op.bytes to 0.
2018-07-26PowerPC Improve support for Gekko & BroadwayAlex Chadwick7-7/+229
This is a relatively straightforward patch to improve support for the IBM Gekko and IBM Broadway processors. Broadway is functionally equivalent to the IBM 750CL, while Gekko's functionality is a subset of theirs. The patch simplifies this reality and adds -mgekko and -mbroadway as aliases for -m750cl. I didn't feel it was worth wasting a PPC_OPCODE_* bit to differentiate Gekko. The patch adds a number of simplified mnemonics for special purpose register access. Notably, Broadway adds 4 additional IBAT and DBAT registers but these are not assigned sequential SPR numbers. gas/ * config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway. * doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * testsuite/gas/ppc/broadway.d, * testsuite/gas/ppc/broadway.s: New test for broadway. * testsuite/gas/ppc/ppc.exp: Run new test. include/ * opcode/ppc.h (PPC_OPCODE_750): Adjust comment. opcodes/ * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway. (powerpc_init_dialect): Handle bfd_mach_ppc_750. * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to support disjointed BAT. (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR. (XSPRGQR_MASK, GEKKO, BROADWAY): Define. (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
2018-07-26Implement PowerPC64 .localentry for value 1Alan Modra2-4/+19
This adds support for ".localentry 1", a new st_other STO_PPC64_LOCAL_MASK encoding that signifies a function with a single entry point like ".localentry 0", but unlike a ".localentry 0" function does not preserve r2. include/ * elf/ppc64.h: Specify byte offset to local entry for values of two to six in STO_PPC64_LOCAL_MASK. Clarify r2 return value for such functions when entering via global entry point. Specify meaning of a value of one in STO_PPC64_LOCAL_MASK. bfd/ * elf64-ppc.c (ppc64_elf_size_stubs): Use a ppc_stub_long_branch_r2off for calls to symbols with STO_PPC64_LOCAL_MASK bits set to 1. gas/ * config/tc-ppc.c (ppc_elf_localentry): Allow .localentry values of 1 and 7 to directly set value into STO_PPC64_LOCAL_MASK bits. ld/testsuite/ * ld-powerpc/elfv2.s: Add .localentry f5,1 testcase. * ld-powerpc/elfv2exe.d: Update. * ld-powerpc/elfv2so.d: Update.
2018-07-25x86: Expand Broadcast to 3 bitsH.J. Lu2-11/+42
Expand Broadcast to 3 bits so that the number of bytes to broadcast can be computed as 1 << (Broadcast - 1). Use it to simplify x86 assembler. gas/ * config/tc-i386.c (Broadcast_Operation): Add bytes. (build_evex_prefix): Use i.broadcast->bytes. (match_broadcast_size): New function. (check_VecOperands): Use the broadcast field to compute the number of bytes to broadcast directly. Set i.broadcast->bytes. Use match_broadcast_size. opcodes/ * i386-gen.c (adjust_broadcast_modifier): New function. (process_i386_opcode_modifier): Add an argument for operands. Adjust the Broadcast value based on operands. (output_i386_opcode): Pass operand_types to process_i386_opcode_modifier. (process_i386_opcodes): Pass NULL as operands to process_i386_opcode_modifier. * i386-opc.h (BYTE_BROADCAST): New. (WORD_BROADCAST): Likewise. (DWORD_BROADCAST): Likewise. (QWORD_BROADCAST): Likewise. (i386_opcode_modifier): Expand broadcast to 3 bits. * i386-tbl.h: Regenerated.
2018-07-25Clarify doc for .arch/.cpuThomas Preud'homme2-2/+10
Documentation for .arch and .cpu directives currently says that it accepts the same name as -march/-mcpu command-line options respectively. However it only accept the architecture/CPU part of those options: it does not accept specifying an extension which is done via .arch_extension. This patch clarifies that the extension is not accepted. 2018-07-25 Thomas Preud'homme <thomas.preudhomme@linaro.org> gas/ * doc/c-arm.texi (.arch directive): Clarify that name must not include an extension. (.cpu directive): Likewise.
2018-07-24x86: Use unsigned int to iterate through vector operandsH.J. Lu2-5/+11
Use unsigned int to iterate through multi-length vector operands to avoid sign-extension. * config/tc-i386.c (build_vex_prefix): Use unsigned int to iterate through multi-length vector operands. (build_evex_prefix): Likewise.
2018-07-24x86-64: correct AVX512F vcvtsi2s{d,s} handlingJan Beulich11-364/+405
Just like for their AVX counterparts and CVTSI2S{D,S}, a memory source here is ambiguous and hence - in source files should be qualified with a suitable suffix or operand size specifier (not doing so is an error in Intel mode, and will gain a diagnostic in AT&T mode in the future), - in disassembly should be properly suffixed (the Intel operand size specifiers were emitted correctly already).
2018-07-23x86: Add a test for missing broadcastH.J. Lu5-0/+19
For .intel_syntax noprefix vcvtps2qq xmm0, DWORD PTR [rax] we should get Error: broadcast is needed for operand of such type for `vcvtps2qq' * testsuite/gas/i386/inval-avx512f.s: Add a test for missing broadcast. * testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise. * testsuite/gas/i386/inval-avx512f.l: Updated. * testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise.
2018-07-23x86: Remove broadcast_not_on_src_operandH.J. Lu2-4/+6
Remove broadcast_not_on_src_operand since it is unused. * config/tc-i386.c (i386_error): Remove broadcast_not_on_src_operand. (match_template): Likewse.
2018-07-23[ARC] Fix decoding of w6 signed short immediate.Claudiu Zissulescu2-1/+5
gas/ Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/st.d: Fix test. opcodes/ Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (extract_w6): Fix extending the sign.
2018-07-23[ARC] Fix case-sensitivity for extension instructions.claziss4-0/+26
In ARC assembler, we accept case insensitive mnemonics, but this was not the case for extension instruction, fix it and add a test. gas/ Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (tokenize_extinsn): Convert to lower case the name of extension instructions. * testsuite/gas/arc/textinsn_case.d: New file. * testsuite/gas/arc/textinsn_case.s: Likewise.
2018-07-22x86: Determine vector length from the last vector operandH.J. Lu2-10/+31
Determine VEX/EVEXE vector length from the last multi-length vector operand. * config/tc-i386.c (build_vex_prefix): Determine vector length from the last multi-length vector operand. (build_evex_prefix): Likewise.
2018-07-21gas/config/tc-i386.c: Break long lineH.J. Lu2-4/+11
* config/tc-i386.c (match_simd_size): Break long line. (match_mem_size): Likewise.
2018-07-20x86: Rename match_reg_size to match_operand_sizeH.J. Lu2-11/+22
match_reg_size checks size for both memory and register operands. This patch renamed match_reg_size to match_operand_size and updated comments for commit 3ac21baa8498d3aa9951f79e2c3336d532eeff7b Author: Jan Beulich <jbeulich@novell.com> Date: Mon Jul 16 08:19:21 2018 +0200 x86: fix operand size checking which added one argument to match_reg_size, match_simd_size and match_mem_size. * config/tc-i386.c (match_reg_size): Renamed to ... (match_operand_size): This. Update comments. (match_simd_size): Update comments. Replace match_reg_size with match_operand_size. (match_mem_size): Likewise. (operand_size_match): Replace match_reg_size with match_operand_size.
2018-07-20MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3aChenghua Xu14-339/+460
The MMI instruction set has been implemented in many Loongson processors. There is a lot of software optimized for MMI. This patch splits MMI from loongson2f/3a, and adds GAS and disassembler options for MMI instructions. 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com> Maciej W. Rozycki <macro@mips.com> bfd/ * elfxx-mips.c (print_mips_ases): Add MMI extension. binutils/ * readelf.c (print_mips_ases): Add MMI extension. gas/ * NEWS: Mention MultiMedia extensions Instructions (MMI) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_MMI and OPTION_NO_LOONGSON_MMI. (md_longopts): Likewise. (mips_ases): Define availability for MMI. (mips_convert_ase_flags): Map ASE_LOONGSON_MMI to AFL_ASE_LOONGSON_MMI. (mips_cpu_info_table): Add ASE_LOONGSON_MMI for loongson2f/3a. (md_show_usage): Add help for -mloongson-mmi and -mno-loongson-mmi. * doc/as.texi: Document -mloongson-mmi, -mno-loongson-mmi. * doc/c-mips.texi: Document -mloongson-mmi, -mno-loongson-mmi, .set loongson-mmi and .set noloongson-mmi. * testsuite/gas/mips/loongson-2f.d: Move mmi test to ... * testsuite/gas/mips/loongson-2f-mmi.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-2f.s: Move mmi test to ... * testsuite/gas/mips/loongson-2f-mmi.s: Here. * testsuite/gas/mips/loongson-3a.d: Move mmi test to ... * testsuite/gas/mips/loongson-3a-mmi.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-3a.s: Move mmi test to ... * testsuite/gas/mips/loongson-3a-mmi.s: Here. * testsuite/gas/mips/mips.exp: Run loongson-2f-mmi and loongson-3a-mmi tests. include/ * elf/mips.h (AFL_ASE_MMI): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI. * opcode/mips.h (ASE_LOONGSON_MMI): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-mmi option. (print_mips_disassembler_options): Document -M loongson-mmi. * mips-opc.c (LMMI): New macro. (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI instructions.
2018-07-20Specify architecture for SPARC gas testsRainer Orth2-23/+62
A couple of SPARC gas tests FAIL on Solaris/SPARC (both sparc-sun-solaris2.11 and sparcv9-sun-solaris2.11): FAIL: sparc PAUSE FAIL: sparc CBCOND FAIL: sparc CFR FAIL: sparc CRYPTO FAIL: sparc HPC+VIS3 FAIL: sparc IMA FAIL: sparc OSA2015 %mwait asr and MWAIT instruction FAIL: sparc OSA2015 %mcdper asr FAIL: sparc SPARC5 and VIS4.0 FAIL: OSA2015 crypto instructions FAIL: SPARC6 FAIL: FPCMPSHL OSA2017 instructions FAIL: OSA2017 ONADD/ONSUB/ONMUL/ONDIV instructions. FAIL: OSA2017 RLE instructions FAIL: sparc64 rdasr FAIL: sparc64 rdpr FAIL: sparc64 rdhpr FAIL: sparc64 wrasr FAIL: sparc64 wrpr It turns out there's a common pattern here: failures happen for all tests that use SPARC ISA extensions beyond sparcv9, e.g. for the sparc PAUSE test: regexp_diff match failure regexp "^ 0: b7 80 40 02 wr %g1, %g2, %pause$" line " 0: b7 80 40 02 wr %g1, %g2, %asr27" [...] regexp_diff match failure regexp "^ 8: b7 80 20 08 pause 8$" line " 8: b7 80 20 08 wr 8, %asr27" [...] The fix is easy, actually: just as the tests specify the ISA extension to use as a gas flag, the same needs to be done for objdump. For the test above, which has -Av9v, this means passing -msparc:v9v to objdump. Doing so makes all but two (unrelated; to be reported separately) failures go away. This doesn't happen on Linux/SPARC, where gas emits GNU object attributes matching the hardcare capabilities used. Since gas doesn't yet implement Solaris-style object capabilites, the explicit -march is needed, but only passed on Solaris. Tested on both sparc-sun-solaris2.11 and sparcv9-sun-solaris2.11. * testsuite/gas/sparc/sparc.exp (set_tests_arch): New proc. Prefix v9c, v9d, v9v, v9m, v9m8 tests with corresponding set_tests_arch.
2018-07-19x86: fold VFPCLASSP{D,S} templatesJan Beulich2-1/+26
These are special because they may not have a register operand to derive the vector length from, which requires to also deal with the braodcast case when determining vector length in build_evex_prefix(). Also drop IgnoreSize (and the now redundant size specifiers) from their suffixed counterparts.
2018-07-19x86: fold various AVX512BW templatesJan Beulich2-2/+6
2018-07-19x86: fold various AVX512VL templates into their AVX512F counterpartsJan Beulich3-4/+53
2018-07-18MIPS/GAS/testsuite: Correct whitespace issues with Loongson testsMaciej W. Rozycki12-294/+296
Remove CR characters, trailing whitespace and space characters appearing immediately before a tab character, and replace spaces with tabs, all across Loongson GAS tests. gas/ * testsuite/gas/mips/loongson-2e.d: Correct whitespace issues. * testsuite/gas/mips/loongson-2f.d: Likewise. * testsuite/gas/mips/loongson-2f-2.d: Likewise. * testsuite/gas/mips/loongson-2f-3.d: Likewise. * testsuite/gas/mips/loongson-3a.d: Likewise. * testsuite/gas/mips/loongson-3a-2.d: Likewise. * testsuite/gas/mips/loongson-2e.s: Likewise. * testsuite/gas/mips/loongson-2f.s: Likewise. * testsuite/gas/mips/loongson-2f-3.s: Likewise. * testsuite/gas/mips/loongson-3a.s: Likewise. * testsuite/gas/mips/loongson-3a-2.s: Likewise.
2018-07-18x86: Split vcvtps2{,u}qq and vcvttps2{,u}qqH.J. Lu3-0/+16
After commit 1b54b8d7e4fc8055f9220a5287e8a94d8a65a88d Author: Jan Beulich <jbeulich@novell.com> Date: Mon Dec 18 09:36:14 2017 +0100 x86: fold RegXMM/RegYMM/RegZMM into RegSIMD ... qualified by their respective sizes, allowing to drop FirstXmm0 at the same time. folded RegXMM, RegYMM and RegZMM into RegSIMD, it's no longer impossible to distinguish if Xmmword can represent a memory reference when operand specification contains SIMD register. For example, template operands specification like these RegXMM|...|Xmmword|... and RegXMM|... The Xmmword bitfield is always set by RegXMM which is represented by "RegSIMD|Xmmword". This patch splits each of vcvtps2qq, vcvtps2uqq, vcvttps2qq and vcvttps2uqq into 2 templates: one template only has RegXMM source operand and the other only has mempry source operand. gas/ PR gas/23418 * testsuite/gas/i386/xmmword.s: Add tests for vcvtps2qq, vcvtps2uqq, vcvttps2qq and vcvttps2uqq. * testsuite/gas/i386/xmmword.l: Updated. opcodes/ PR gas/23418 * i386-opc.h (Byte): Update comments. (Word): Likewise. (Dword): Likewise. (Fword): Likewise. (Qword): Likewise. (Tbyte): Likewise. (Xmmword): Likewise. (Ymmword): Likewise. (Zmmword): Likewise. * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and vcvttps2uqq. * i386-tbl.h: Regenerated.
2018-07-16x86: fix operand size checkingJan Beulich4-86/+123
Currently mov to/from control, debug, and test register insns accept any size GPR operand (general pattern: templates with D set and both operands being registers in distinct register files). This is due to improper checking of the reverse case, including not informing the caller whether a straight and/or reverse match was successful. The helper functions need to be told two indexes: One to index the given operand types array, and the other to index the template one. The caller must attempt a further straight match only if the function reported a straight match (and respectively for reverse matches).
2018-07-13Add a test that relocs are correctly generated for missing build notes.Nick Clifton4-0/+30
* testsuite/gas/elf/missing-build-notes.s: New test. Checks that relocs are correctly generated for missing build notes. * testsuite/gas/elf/missing-build-notes.d: New file. Expected output from objdump. * testsuite/gas/elf/elf.exp: Run the new test.
2018-07-13Allow bit-patterns in the immediate field of ARM neon mov instructions.Nick Clifton4-4/+33
* config/tc-arm.c (do_neon_mov): When converting an integer immediate into a floating point value, check that the conversion is valid. Also warn if the immediate is valid as both a floating point value and a bit pattern. * testsuite/gas/arm/vfp-mov-enc.s: Add instructions that use floating point bit patterns. * testsuite/gas/arm/vfp-mov-enc.d: Add regexps for the disassembly of the new insns.
2018-07-12This patch adds support for the SSBB and PSSBB speculation barrier ↵Nick Clifton3-363/+374
instructions to the AArch64 assembler and disassembler. For more details see: https://static.docs.arm.com/ddi0596/a/DDI_0596_ARM_a64_instruction_set_architecture.pdf opcodes * aarch64-tbl.h (aarch64_opcode_table): Add entry for ssbb and pssbb and update dsb flags to F_HAS_ALIAS. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas * testsuite/gas/aarch64/system.s: Add test for ssbb and pssbb. * testsuite/gas/aarch64/system.d: Update accordingly and remove explicit addresses.
2018-07-12Add remainder of Em16 restrictions for AArch64 gas.Tamar Christina4-0/+205
This adds the missing Em16 constraints the rest of the instructions requiring them and also adds a testcase to test all the instructions so these are checked from now on. The Em16 operand constrains the valid registers to the lower 16 registers when used with a half precision qualifier. The list has been cross checked (by hand) through the Arm ARM version Ca. opcodes/ PR binutils/23192 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2, mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal, umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull, sqdmulh, sqrdmulh): Use Em16. gas/ PR binutils/23192 * testsuite/gas/aarch64/illegal-by-element.s: New. * testsuite/gas/aarch64/illegal-by-element.d: New. * testsuite/gas/aarch64/illegal-by-element.l: New.
2018-07-11Adds the speculation barrier instructions to the ARM assembler and disassembler.Sudakshina Das8-6/+29
See: https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/download-the-whitepaper opcodes * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move csdb together with them. (thumb32_opcodes): Likewise. gas * config/tc-arm.c (insns): Add new ssbb and pssbb instructions. * testsuite/gas/arm/csdb.s: Add new tests for ssbb and pssbb. * testsuite/gas/arm/csdb.d: Likewise * testsuite/gas/arm/thumb2_it_bad.s: Likewise. * testsuite/gas/arm/thumb2_it_bad.l: Likewise. * testsuite/gas/arm/barrier.d: Update with ssbb. * testsuite/gas/arm/barrier-thumb.d: Likewise.
2018-07-11x86: drop {,reg16_}inoutportreg variablesJan Beulich2-7/+8
The checking against reg16_inoutportreg can be had with a simple test of a bit, and the value setting from inoutportreg can be replaced by using the actual register's reg_type field. Note that the so far redundant 2nd instance of OPERAND_TYPE_INOUTPORTREG is left in place, for its use in type_names[].
2018-07-11x86: simplify legacy prefix emissionJan Beulich2-10/+9
The check_prefix label was bogus from the beginning: The special checking is supposed to happen for PadLock insns only; no 3-opcode-byte insn should go this path.
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