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2006-07-24Fix spelling typosNick Clifton19-56/+65
2006-07-21* config/tc-sh.c (md_longopts): Add -EL and -EB for use by the linker testsuite.Nick Clifton2-0/+9
2006-07-20Update amd family 10 instructions to add appropriate alignment for cygwinMichael Meissner5-0/+18
2006-07-20 * config/tc-mips.c (md_parse_option): Don't infer optimisationThiemo Seufer2-5/+6
options from debug options.
2006-07-20 [ bfd/ChangeLog ]Thiemo Seufer2-5/+9
* elf32-mips.c (mips16_jump_reloc): Remove function. (elf_mips16_howto_table_rel): Use _bfd_mips_elf_generic_reloc instead of mips16_jump_reloc. * elf64_mips.c, wlfn32-mips.c (mips16_jump_reloc): Remove function. (elf_mips16_howto_table_rel, elf_mips16_howto_table_rela): Use _bfd_mips_elf_generic_reloc instead of mips16_jump_reloc. [ gas/ChangeLog ] * config/tc-mips.c (mips_fix_adjustable): Handle BFD_RELOC_MIPS16_JMP. (tc_gen_reloc): Handle mips16 jumps to section symbol offsets. [ ld/testsuite/ChangeLog ] * ld-mips-elf/mips16-call-global-1.s, ld-mips-elf/mips16-call-global-2.s, ld-mips-elf/mips16-call-global-3.s, ld-mips-elf/mips16-call-global.d: Test linking of external mips16 jumps. * ld-mips-elf/mips-elf.exp: Run new test.
2006-07-192006-07-19 Paul Brook <paul@codesourcery.com>Paul Brook4-5/+13
gas/ * config/tc-arm.c (insns): Fix rbit Arm opcode. gas/testsuite/ * gas/arm/archv6t2.d: Adjust expected output for rbit. opcodes/ * armd-dis.c (arm_opcodes): Fix rbit opcode.
2006-07-18gas/testsuite/H.J. Lu5-1/+52
2006-07-18 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/opcode.s: Add sldt, smsw and str. * gas/i386/x86-64-opcode.s: Likewise. * gas/i386/opcode.d: Updated. * gas/i386/x86-64-opcode.d: Likewise. opcodes/ 2006-07-18 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to "sldt", "str" and "smsw".
2006-07-182006-07-18 Paul Brook <paul@codesourcery.com>Paul Brook5-13/+90
bfd/ * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * reloc.c: Add BFD_RELOC_ARM_T32_ADD_IMM. gas/ * tc-arm.c (do_t_add_sub): Use addw/subw when source is PC. (md_convert_frag): Use correct reloc for add_pc. Use BFD_RELOC_ARM_T32_ADD_IMM for normal add/sum. (md_apply_fix): Handle BFD_RELOC_ARM_T32_ADD_IMM. (arm_force_relocation): Handle BFD_RELOC_ARM_T32_ADD_IMM. gas/testsuite/ * gas/arm/thumb2_add.d: New test. * gas/arm/thumb2_add.s: New test.
2006-07-18 * gas/mips/mips4.s, gas/mips/mips4.d: Enable the "pref" test. ChangeThiemo Seufer3-17/+19
arguments for "madd.s" so that the instruction is correct for mips1 and still matches "bc3*".
2006-07-17 * symbols.c (report_op_error): Fix pasto. Don't use as_bad_whereAlan Modra2-6/+9
when file and line unknown.
2006-07-17 * read.c (s_struct): Use IS_ELF.Thiemo Seufer3-27/+33
* config/tc-mips.c (md_begin, mips16_mark_labels, mips_ip, md_parse_option, s_change_sec, pic_need_relax, mips_fix_adjustable, tc_gen_reloc, mips_frob_file_after_relocs, s_mips_end, s_mips_frame, s_mips_mask): Likewise.
2006-07-16 * read.c (s_struct): Handle ELF section changing.Thiemo Seufer2-0/+14
* config/tc-mips.c (s_align): Leave enabling auto-align to the generic code. (s_change_sec): Try section changing only if we output ELF.
2006-07-152006-07-15 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu3-60/+67
* config/tc-i386.c (cpu_arch): Remove Cpu086, CpuAthlon and CpuAmdFam10. (smallest_imm_type): Remove Cpu086. (i386_target_format): Likewise. * config/tc-i386.h: Remove Cpu086, CpuAthlon and CpuAmdFam10. Update CpuXXX.
2006-07-13Add amdfam10 instructionsMichael Meissner9-11/+194
2006-07-132006-07-13 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-1/+5
* config/tc-i386.h (Size64): Fix a typo in comment.
2006-07-12Fix grammatical error in ChangeLog entryNick Clifton1-1/+1
2006-07-12* config/tc-sh.c (md_apply_fix): Do not allow the generic code inNick Clifton6-0/+68
fixup_segment() to repeat a range check on a value that have already been checked here. * gas/sh/basic.exp: Run "too_large" dump test. * gas/sh/too_large.s: New test file. Check that .byte directives do not generate a bogus overflow message. * gas/sh/too_large.s: New test control file.
2006-07-07Add Broadcom SB-1A support.Jim Wilson2-0/+7
* config/tc-mips.c (mips_cpu_info_table): Add sb1a.
2006-07-06PR binutils/2877Nick Clifton4-28/+40
* doc/as.texi: Fix spelling typo: branchs => branches. * doc/c-m68hc11.texi: Likewise. * config/tc-m68hc11.c: Likewise. Support old spelling of command line switch for backwards compatibility.
2006-07-05 * gas/arm/vfp-neon-syntax.d: Tweak expected fmsrr syntax.Julian Brown5-8/+15
* gas/arm/vfp-neon-syntax_t2.d: Likewise. * gas/arm/vfp2.d: Likewise. * gas/arm/vfp2_t2.d: Likewise.
2006-07-04 * config/tc-mips.c (s_is_linkonce): New function.Thiemo Seufer2-22/+41
(mips16_mark_labels): Don't adjust mips16 symbol addresses for weak, external, and linkonce symbols. (pic_need_relax): Use s_is_linkonce.
2006-07-04 * gas/mips/e32-rel2.d, gas/mips/e32-rel4.d: Use -mabi=32 for as.Thiemo Seufer4-14/+16
* gas/mips/mips.exp: Move mips16e testcase to ELF only tests. Run elf{el}-rel2 and elf-rel4 for all arches with gpr64. Run e32-rel2 and e32-rel4 also for 64 bit configurations.
2006-06-242006-06-24 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-2/+7
* doc/as.texinfo (Org): Remove space. (P2align): Add "@var{abs-expr},".
2006-06-23gas/H.J. Lu19-27/+2545
2006-06-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch_tune_set): New. (cpu_arch_isa): Likewise. (i386_align_code): Use xchg %ax,%ax for 2 byte nop. Optimize nops with short or long nop sequences based on -march=/.arch and -mtune=. (set_cpu_arch): Set cpu_arch_isa. If cpu_arch_tune_set is 0, set cpu_arch_tune and cpu_arch_tune_flags. (md_parse_option): For -march=, set cpu_arch_isa and set cpu_arch_tune and cpu_arch_tune_flags if cpu_arch_tune_set is 0. Set cpu_arch_tune_set to 1 for -mtune=. (i386_target_format): Don't set cpu_arch_tune. gas/testsuite/ 2006-06-23 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run nops-1, nops-1-i386, nops-1-i686, nops-1-merom, nops-2, nops-2-i386, nops-2-merom, x86-64-nops-1, x86-64-nops-1-k8, x86-64-nops-1-nocona and x86-64-nops-1-merom. * gas/i386/nops-1.s: New file. * gas/i386/nops-2.s: Likewise. * gas/i386/nops-1-i386.d: Likewise. * gas/i386/nops-1-i686.d: Likewise. * gas/i386/nops-1-merom.d: Likewise. * gas/i386/nops-1.d: Likewise. * gas/i386/nops-2-i386.d: Likewise. * gas/i386/nops-2-merom.d: Likewise. * gas/i386/nops-2.d: Likewise. * gas/i386/x86-64-nops-1.s: Likewise. * gas/i386/x86-64-nops-1-k8.d: Likewise. * gas/i386/x86-64-nops-1-merom.d: Likewise. * gas/i386/x86-64-nops-1-nocona.d: Likewise. * gas/i386/x86-64-nops-1.d: Likewise. * gas/i386/sse2.d: Updated to expect xchg %ax,%ax as 2 byte nop.
2006-06-23 * config/tc-mips.c (nopic_need_relax): Handle -fdata-sectionsThiemo Seufer2-0/+7
generated .sbss.* and .gnu.linkonce.sb.*.
2006-06-23 * config/tc-mips.h (TC_SEGMENT_INFO_TYPE): Declare per-segmentThiemo Seufer3-28/+67
label_list. * config/tc-mips.c (label_list): Define per-segment label_list. (mips_clear_insn_labels, mips_move_labels, mips16_mark_labels, append_insn, s_align, s_cons, s_float_cons, s_gpword, s_gpdword, mips_from_file_after_relocs, mips_define_label): Use per-segment label_list.
2006-06-22 * config/tc-mips.c (ISA_SUPPORTS_MIPS16E): New macro.Thiemo Seufer2-19/+31
(append_insn): Use it. (md_apply_fix): Whitespace formatting. (md_begin, append_insn, macro, macro2, mips16_immed, mips_align, mips16_extended_frag): Remove register specifier. (md_convert_frag): Likewise. Use TRUE ans FALSE instead of numeric constants.
2006-06-21Corrected typo in date.Mark Shinwell1-1/+1
2006-06-21gas/Mark Shinwell3-5/+93
* config/tc-arm.c (s_arm_unwind_save_vfp_armv6): New. Parse a directive saving VFP registers for ARMv6 or later. (s_arm_unwind_save): Add parameter arch_v6 and call s_arm_unwind_save_vfp or s_arm_unwind_save_vfp_armv6 as appropriate. (md_pseudo_table): Add entry for new "vsave" directive. * doc/c-arm.texi: Correct error in example for "save" directive (fstmdf -> fstmdx). Also document "vsave" directive.
2006-06-20 * gas/mips/mips.exp: Explicitly specify o32 ABI.Thiemo Seufer4-3/+9
* gas/mips/mips64-dsp.d: Dump o32 register names. * gas/mips/smartmips.d: Explicitly specify o32 ABI.
2006-06-19 * config/tc-avr.c (mcu_types): Add support for atmega165p, atmega169pDenis Chertykov3-7/+22
and atmega644p devices. Rename atmega164/atmega324 devices to atmega164p/atmega324p. * doc/c-avr.texi: Document new mcu and arch options.
2006-06-18Skip for non-ELF targets.Nick Clifton13-0/+27
2006-06-17(enum parse_operand_result): Move outside of #ifdef OBJ_ELF so that non-ELFNick Clifton2-7/+12
targeted ARM ports can build.
2006-06-162006-06-16 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu5-42/+255
* config/tc-i386.h (processor_type): New. (arch_entry): Add type. * config/tc-i386.c (cpu_arch_tune): New. (cpu_arch_tune_flags): Likewise. (cpu_arch_isa_flags): Likewise. (cpu_arch): Updated. (set_cpu_arch): Also update cpu_arch_isa_flags. (md_assemble): Update cpu_arch_isa_flags. (OPTION_MARCH): New. (OPTION_MTUNE): Likewise. (md_longopts): Add -march= and -mtune=. (md_parse_option): Support -march= and -mtune=. (md_show_usage): Add -march=CPU/-mtune=CPU. (i386_target_format): Also update cpu_arch_isa_flags, cpu_arch_tune and cpu_arch_tune_flags. * doc/as.texinfo: Add -march=CPU/-mtune=CPU. * doc/c-i386.texi: Document -march=CPU/-mtune=CPU.
2006-06-15 * include/elf/arm.h: Correct names of R_ARM_LDC_G{0,1,2}Mark Shinwell35-67/+3932
to R_ARM_LDC_SB_G{0,1,2} respectively. bfd/ * bfd-in2.h: Regenerate. * elf32-arm.c (R_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0, R_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1, R_ARM_ALU_PC_G2, R_ARM_LDR_PC_G1, R_ARM_LDR_PC_G2, R_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G2, R_ARM_LDC_PC_G0, R_ARM_LDC_PC_G1, R_ARM_LDC_PC_G2, R_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0, R_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1, R_ARM_ALU_SB_G2, R_ARM_LDR_SB_G0, R_ARM_LDR_SB_G1, R_ARM_LDR_SB_G2, R_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G2, R_ARM_LDC_SB_G0, R_ARM_LDC_SB_G1, R_ARM_LDC_SB_G2): New relocation types. (R_ARM_PC13): Rename to AAELF name R_ARM_LDR_PC_G0 and adjust HOWTO entry to be consistent with R_ARM_LDR_PC_G1 and friends. (elf32_arm_howto_table_3): Delete; contents merged into elf32_arm_howto_table_2. (elf32_arm_howto_from_type): Adjust correspondingly. (elf32_arm_reloc_map): Extend with the above relocations. (calculate_group_reloc_mask): New function. (identify_add_or_sub): New function. (elf32_arm_final_link_relocate): Support for the above relocations. * reloc.c: Add enumeration entries for BFD_RELOC_ARM_... codes to correspond to the above relocations. gas/ * config/tc-arm.c (enum parse_operand_result): New. (struct group_reloc_table_entry): New. (enum group_reloc_type): New. (group_reloc_table): New array. (find_group_reloc_table_entry): New function. (parse_shifter_operand_group_reloc): New function. (parse_address_main): New function, incorporating code from the old parse_address function. To be used via... (parse_address): wrapper for parse_address_main; and (parse_address_group_reloc): new function, likewise. (enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR, OP_ADDRGLDRS, OP_ADDRGLDC. (parse_operands): Support for these new operand codes. New macro po_misc_or_fail_no_backtrack. (encode_arm_cp_address): Preserve group relocations. (insns): Modify to use the above operand codes where group relocations are permitted. (md_apply_fix): Handle the group relocations ALU_PC_G0_NC through LDC_SB_G2. (tc_gen_reloc): Likewise. (arm_force_relocation): Leave group relocations for the linker. (arm_fix_adjustable): Likewise. gas/testsuite/ * gas/arm/group-reloc-alu.d: New test. * gas/arm/group-reloc-alu-encoding-bad.d: New test. * gas/arm/group-reloc-alu-encoding-bad.l: New test. * gas/arm/group-reloc-alu-encoding-bad.s: New test. * gas/arm/group-reloc-alu-parsing-bad.d: New test. * gas/arm/group-reloc-alu-parsing-bad.l: New test. * gas/arm/group-reloc-alu-parsing-bad.s: New test. * gas/arm/group-reloc-alu.s: New test. * gas/arm/group-reloc-ldc.d: New test. * gas/arm/group-reloc-ldc-encoding-bad.d: New test. * gas/arm/group-reloc-ldc-encoding-bad.l: New test. * gas/arm/group-reloc-ldc-encoding-bad.s: New test. * gas/arm/group-reloc-ldc-parsing-bad.d: New test. * gas/arm/group-reloc-ldc-parsing-bad.l: New test. * gas/arm/group-reloc-ldc-parsing-bad.s: New test. * gas/arm/group-reloc-ldc.s: New test. * gas/arm/group-reloc-ldr.d: New test. * gas/arm/group-reloc-ldr-encoding-bad.d: New test. * gas/arm/group-reloc-ldr-encoding-bad.l: New test. * gas/arm/group-reloc-ldr-encoding-bad.s: New test. * gas/arm/group-reloc-ldr-parsing-bad.d: New test. * gas/arm/group-reloc-ldr-parsing-bad.l: New test. * gas/arm/group-reloc-ldr-parsing-bad.s: New test. * gas/arm/group-reloc-ldr.s: New test. * gas/arm/group-reloc-ldrs.d: New test. * gas/arm/group-reloc-ldrs-encoding-bad.d: New test. * gas/arm/group-reloc-ldrs-encoding-bad.l: New test. * gas/arm/group-reloc-ldrs-encoding-bad.s: New test. * gas/arm/group-reloc-ldrs-parsing-bad.d: New test. * gas/arm/group-reloc-ldrs-parsing-bad.l: New test. * gas/arm/group-reloc-ldrs-parsing-bad.s: New test. * gas/arm/group-reloc-ldrs.s: New test. ld/testsuite/ * ld-arm/group-relocs-alu-bad.d: New test. * ld-arm/group-relocs-alu-bad.s: New test. * ld-arm/group-relocs.d: New test. * ld-arm/group-relocs-ldc-bad.d: New test. * ld-arm/group-relocs-ldc-bad.s: New test. * ld-arm/group-relocs-ldr-bad.d: New test. * ld-arm/group-relocs-ldr-bad.s: New test. * ld-arm/group-relocs-ldrs-bad.d: New test. * ld-arm/group-relocs-ldrs-bad.s: New test. * ld-arm/group-relocs.s: New test. * ld-arm/arm-elf.exp: Wire in new tests.
2006-06-15 * config/tc-arm.c (do_vfp_nsyn_ldr_str): Remove, fold into...Julian Brown2-52/+13
(do_neon_ldr_str): Always defer to VFP encoding routines, which handle relocs properly.
2006-06-14 * gas/mips/elf-rel6.d, gas/mips/elf-rel6.s: Extend testcase.Thiemo Seufer6-2/+52
* gas/mips/elf-rel6.d-n32.d, gas/mips/elf-rel6-n64.d: New files. * gas/mips/mips.exp: Run new testcases.
2006-06-14 * gas/mips/mips16e-jrc.d, gas/mips/mips16e-save.d,Thiemo Seufer5-4/+10
gas/mips/mips32-dsp.d, gas/mips/mips32-mt.d: Explicitly specify o32 ABI.
2006-06-12gas/testsuite/H.J. Lu6-0/+69
2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run nops and x86-64-nops. * gas/i386/nops.d: New file. * gas/i386/nops.s: Likewise. * gas/i386/x86-64-nops.d: Likewise. * gas/i386/x86-64-nops.s: Likewise. include/opcode/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Add "nop" with memory reference. opcodes/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f. (twobyte_has_modrm): Set 1 for 0x1f.
2006-06-12gas/H.J. Lu7-4/+40
2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_suffix): Don't add rex64 for "xchg %rax,%rax". gas/testsuite/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/opcode.s: Add "xchg %ax,%ax". * gas/i386/opcode.d: Updated. * gas/i386/x86-64-opcode.s: Add xchg %ax,%ax, xchg %eax,%eax, xchg %rax,%rax, rex64 xchg %rax,%rax and xchg %rax,%r8. * gas/i386/x86-64-opcode.d: Updated. include/opcode/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Update comment for 64bit NOP. opcodes/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (NOP_Fixup): Removed. (NOP_Fixup1): New. (NOP_Fixup2): Likewise. (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
2006-06-09Lost bit belonging to the last commit.Thiemo Seufer1-0/+1
2006-06-09 [ gas/ChangeLog ]Thiemo Seufer5-0/+46
* config/tc-mips.c (mips_ip): Maintain argument count. [ gas/testsuite/ChangeLog ] * gas/mips/mips32-sf32.s, gas/mips/mips32-sf32.d: New test for odd single precision FPRs on MIPS32. * gas/mips/mips.exp: Run them.
2006-06-09 * config/tc-iq2000.c: Include sb.h.Alan Modra2-0/+5
2006-06-08 * gas/mips/mips32.s: Added cop2 branches with explicit conditionThiemo Seufer3-0/+25
code register numbers. * gas/mips/mips32.d: Likewise.
2006-06-08 * config/tc-mips.c (mips_pseudo_table): Add "origin" and "repeat"Thiemo Seufer2-0/+7
aliases for better compatibility with SGI tools.
2006-06-08 * configure.in (BFDLIB, BFDVER_H, ALL_OBJ_DEPS): Delete.Alan Modra7-1871/+1761
* Makefile.am (GASLIBS): Expand @BFDLIB@. (BFDVER_H): Delete. (OBJS): Expand @ALL_OBJ_DEPS@. Depend on all fopen-*.h variants. (obj-aout.o): Depend on $(DEP_@target_get_type@_aout) (obj-coff.o, obj-ecoff.o, obj-elf.o): Similarly. Run "make dep-am". * dep-in.sed: Don't substitute bfdver.h. Do remove symcat.h. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * configure: Regenerate.
2006-06-07bfd/doc:Joseph Myers2-1/+5
* bfd.texinfo: Remove local @tex code. bfd: * po/Make-in (pdf, ps): New dummy targets. binutils: * po/Make-in (pdf, ps): New dummy targets. gas: * po/Make-in (pdf, ps): New dummy targets. gprof: * po/Make-in (pdf, ps): New dummy targets. ld: * po/Make-in (pdf, ps): New dummy targets. opcodes: * po/Make-in (pdf, ps): New dummy targets.
2006-06-07 * config/tc-arm.c (stdarg.h): include.Julian Brown2-503/+1557
(arm_it): Add uncond_value field. Add isvec and issingle to operand array. (arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and REG_TYPE_NSDQ (single, double or quad vector reg). (reg_expected_msgs): Update. (BAD_FPU): Add macro for unsupported FPU instruction error. (parse_neon_type): Support 'd' as an alias for .f64. (parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ sets of registers. (parse_vfp_reg_list): Don't update first arg on error. (parse_neon_mov): Support extra syntax for VFP moves. (operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO, OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ. (parse_operands): Support isvec, issingle operands fields, new parse codes above. (do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs, msr variants. (do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above. (NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez. (NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros. (NEON_SHAPE_DEF): New macro. Define table of possible instruction shapes. (neon_shape): Redefine in terms of above. (neon_shape_class): New enumeration, table of shape classes. (neon_shape_el): New enumeration. One element of a shape. (neon_shape_el_size): Register widths of above, where appropriate. (neon_shape_info): New struct. Info for shape table. (neon_shape_tab): New array. (neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL. (neon_check_shape): Rewrite as... (neon_select_shape): New function to classify instruction shapes, driven by new table neon_shape_tab array. (neon_quad): New function. Return 1 if shape should set Q flag in instructions (or equivalent), 0 otherwise. (type_chk_of_el_type): Support F64. (el_type_of_type_chk): Likewise. (neon_check_type): Add support for VFP type checking (VFP data elements fill their containing registers). (do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE in thumb mode for VFP instructions. (do_vfp_nsyn_opcode): New function. Look up the opcode in argument, and encode the current instruction as if it were that opcode. (try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS arguments, call function in PFN. (do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul) (do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str) (do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul) (do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push) (do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions. Redirect Neon-syntax VFP instructions to VFP instruction handlers. (do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm) (do_neon_qshl_imm, do_neon_logic, do_neon_bitfield) (neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh) (do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri) (do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext) (do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn) (do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long) (do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt) (do_neon_swp): Use neon_select_shape not neon_check_shape. Use neon_quad. (vfp_or_neon_is_neon): New function. Call if a mnemonic shared between VFP and Neon turns out to belong to Neon. Perform architecture check and fill in condition field if appropriate. (do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg) (do_neon_cvt): Add support for VFP variants of instructions. (neon_cvt_flavour): Extend to cover VFP conversions. (do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP vmov variants. (do_neon_ldr_str): Handle single-precision VFP load/store. (do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use NS_NULL not NS_IGNORE. (opcode_tag): Add OT_csuffixF for operands which either take a conditional suffix, or have 0xF in the condition field. (md_assemble): Add support for OT_csuffixF. (NCE): Replace macro with... (NCE_tag, NCE, NCEF): New macros. (nCE): Replace macro with... (nCE_tag, nCE, nCEF): New macros. (insns): Add support for VFP insns or VFP versions of insns msr, mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop, vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia, vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared VFP/Neon insns together.
2006-06-07 * gas/arm/itblock.s: New file. Helper macro for making all-true ITJulian Brown13-0/+758
blocks. * gas/arm/neon-cond-bad-inc.s: New test. Make sure unconditional Neon instructions are rejected... * gas/arm/neon-cond-bad.s: In ARM mode, and... * gas/arm/neon-cond-bad_t2.s: Accepted in Thumb mode (with IT). * gas/arm/neon-cond-bad.l: Expected error output in ARM mode. * gas/arm/neon-cond-bad.d: Control ARM mode test. * gas/arm/neon-cond-bad_t2.d: Expected output in Thumb mode. * gas/arm/vfp-neon-syntax-inc.s: Test VFP Neon-style syntax. * gas/arm/vfp-neon-syntax.s: ...in ARM mode. * gas/arm/vfp-neon-syntax_t2.s: ...and Thumb mode. * gas/arm/vfp-neon-syntax.d: Expected output in ARM mode. * gas/arm/vfp-neon-syntax_t2.d: Expected output in Thumb mode.
2006-06-072006-06-06 Paul Brook <paul@codesourcery.com>Paul Brook5-224/+229
opcodes/ * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm instructions. (neon_opcodes): Add conditional execution specifiers. (thumb_opcodes): Ditto. (thumb32_opcodes): Ditto. (arm_conditional): Change 0xe to "al" and add "" to end. (ifthen_state, ifthen_next_state, ifthen_address): New. (IFTHEN_COND): Define. (print_insn_coprocessor, print_insn_neon): Print thumb conditions. (print_insn_arm): Change %c to use new values of arm_conditional. (print_insn_thumb16): Print thumb conditions. Add %I. (print_insn_thumb32): Print thumb conditions. (find_ifthen_state): New function. (print_insn): Track IT block state. gas/testsuite/ * gas/arm/thumb2_bcond.d: Update expected output. * gas/arm/thumb32.d: Ditto. * gas/arm/vfp1_t2.d: Ditto. * gas/arm/vfp1xD_t2.d: Ditto. binutils/testsuite/ * binutils-all/arm/objdump.exp: New file. * binutils-all/arm/thumb2-cond.s: New test.
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