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2021-11-11aarch64: Fix scbnds validationAlex Coplan7-2/+114
2021-09-24aarch64: Mark purecap object files with EF_AARCH64_CHERI_PURECAPAlex Coplan2-0/+10
2021-09-24morello: Fix encoding of ldtr/sttrAlex Coplan7-31/+83
2021-08-10gas: Add whitespace in morello-capinit test output regexpMatthew Malcomson1-3/+3
2021-08-10gas: ADR_LO21_PCREL accounts for LSB in symbolMatthew Malcomson4-48/+46
2021-08-10gas: Remove requirement of getting a target symbolMatthew Malcomson5-15/+49
2021-08-10gas: Allow MORELLO branch relocations to addresses with LSB setMatthew Malcomson4-4/+122
2021-08-04Apply changes to allow compiling with -ansiMatthew Malcomson1-2/+3
2021-07-30gas: aarch64: Accept `purecap` and `hybrid` ABI parametersMatthew Malcomson4-1/+48
2021-07-29gas: aarch64: Make chericap and capinit auto-alignMatthew Malcomson4-0/+39
2021-07-29Fixing missed ChangeLog entries.Matthew Malcomson1-0/+21
2021-07-29gas: aarch64: Require 16 bytes for Morello capinit relocationMatthew Malcomson4-2/+24
2021-07-29gas: aarch64: Introduce the chericap directiveMatthew Malcomson3-0/+172
2021-07-29gas: aarch64: Fixing expression calculation using C64 symbolsMatthew Malcomson3-0/+107
2021-07-20gas: Use correct data type in parse_operandsMatthew Malcomson2-1/+6
2021-07-13gas: Fix uninitialized c64 member of aarch64_fix structAlex Coplan2-2/+10
2020-10-20[Morello] TLS Descriptor supportSiddhesh Poyarekar4-6/+48
2020-10-20[Morello] Capability support for exception headersSiddhesh Poyarekar6-14/+152
2020-10-20[Morello] Implement branch relocationsSiddhesh Poyarekar2-6/+35
2020-10-20[Morello] GOT RelocationsSiddhesh Poyarekar4-3/+40
2020-10-20[Morello] Allow lo12 relocations for alternate base ld/stSiddhesh Poyarekar4-7/+64
2020-10-20[Morello] Capability data relocationsSiddhesh Poyarekar4-0/+121
2020-10-20[Morello] Add Morello relocations for ADRPSiddhesh Poyarekar3-5/+88
2020-10-20[Morello] Make DC, IC capability aware in C64.Siddhesh Poyarekar5-0/+73
2020-10-20[Morello] Add Morello system registersSiddhesh Poyarekar5-3/+258
2020-10-20[Morello] ADR, ADRP and ADRDPSiddhesh Poyarekar5-5/+64
2020-10-20[Morello] Implement LDUR/STUR fallback for LDR/STR in altbase modeSiddhesh Poyarekar5-24/+150
2020-10-20[Morello] altbase: Remaining LD/STSiddhesh Poyarekar4-0/+40
2020-10-20[Morello] altbase: LDUR/STURSiddhesh Poyarekar5-0/+225
2020-10-20[Morello] altbase: LDR/STRSiddhesh Poyarekar5-0/+121
2020-10-20[Morello] Loads and stores with alternate baseSiddhesh Poyarekar5-0/+53
2020-10-20[Morello] All remaining load and store instructionsSiddhesh Poyarekar5-0/+237
2020-10-20[Morello] LDR immediateSiddhesh Poyarekar2-3/+40
2020-10-20[Morello] Load and store instructions.Siddhesh Poyarekar5-1/+245
2020-10-20[Morello] Load and branch instructionsSiddhesh Poyarekar5-1/+134
2020-10-20[Morello] Capability sealing and unsealing instructionsSiddhesh Poyarekar5-1/+40
2020-10-20[Morello] Capability construction and modification instructionsSiddhesh Poyarekar5-2/+168
2020-10-20[Morello] CLRTAG, CLRPERMSiddhesh Poyarekar5-2/+107
2020-10-20[Morello] Miscellaneous Morello InstructionsSiddhesh Poyarekar7-3/+530
2020-10-20[Morello] Branch and return instructionsSiddhesh Poyarekar5-0/+83
2020-10-20[Morello] Add BICFLGSSiddhesh Poyarekar5-0/+73
2020-10-20[Morello] ADD and SUB instructionsSiddhesh Poyarekar5-4/+167
2020-10-20[Morello] Add MOV and CPY instructions for capabilitiesSiddhesh Poyarekar5-3/+68
2020-10-20[Morello] Identify branch source and target using mapping symbolsSiddhesh Poyarekar3-4/+47
2020-10-20[Morello] Set LSB for c64 symbols in object codeSiddhesh Poyarekar3-2/+94
2020-10-20[Morello] Add mapping symbol to identify C64 code sectionsSiddhesh Poyarekar4-19/+48
2020-10-20[AArch64] Initial commit for Morello architectureSiddhesh Poyarekar6-3/+86
2020-10-20[AArch64] Prefer error messages from opcodes enabled in CPU_VARIANTSiddhesh Poyarekar4-24/+56
2020-10-17gas: Add a -gdwarf-5 debug_line test with .s fileH.J. Lu4-0/+62
2020-10-17gas: Replace dwarf5-line-2.S with dwarf5-line-3.SH.J. Lu3-4/+12
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