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2022-07-09gas: arm -mwarn-syms duplicatesAlan Modra2-5/+3
arm gas is only supposed to warn once per symbol for -mwarn-syms, but doesn't because the str_hash_find added with commit 629310abec88 always returns NULL. That's so because the str_hash_insert inserts a NULL value for the key,value pair. Let str_hash_insert do the job instead. * config/tc-arm.c (arm_tc_equal_in_insn): Correct already_warned logic. * testsuite/gas/arm/pr18347.s: Modify to generate duplicate warning without this patch.
2022-07-09Regenerate with automake-1.15.1Alan Modra3-733/+379
Until we update the recommended versions of autoconf/automake, files should be regenerated with automake-1.15.1 and autoconf-2.69. That's not because we think those versions are golden, and newer versions are bad. It's simply because maintainers want to be able to update configury files without trouble, and if someone regenerates files with automake-1.16.5 then --enable-maintainer-mode builds will hit errors: checking that generated files are newer than configure... configure.ac:26: error: version mismatch. This is Automake 1.15.1, configure.ac:26: but the definition used by this AM_INIT_AUTOMAKE configure.ac:26: comes from Automake 1.16.5. You should recreate configure.ac:26: aclocal.m4 with aclocal and run automake again. WARNING: 'automake-1.15' is probably too old. Correcting this requires regenerating the files by hand.
2022-07-08Update version to 2.39.50 and regenerate filesNick Clifton4-2371/+2751
2022-07-08Add markers for 2.39 branchNick Clifton2-0/+6
2022-07-07RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI13-32/+64
This commit adds Zfhmin and Zhinxmin extensions (subsets of Zfh and Zhinx extensions, respectively). In the process supporting Zfhmin and Zhinxmin extension, this commit also changes how instructions are categorized considering Zfhmin, Zhinx and Zhinxmin extensions. Detailed changes, * From INSN_CLASS_ZFH to INSN_CLASS_ZFHMIN: flh, fsh, fmv.x.h and fmv.h.x. * From INSN_CLASS_ZFH to INSN_CLASS_ZFH_OR_ZHINX: fmv.h. * From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFH_OR_ZHINX: fneg.h, fabs.h, fsgnj.h, fsgnjn.h, fsgnjx.h, fadd.h, fsub.h, fmul.h, fdiv.h, fsqrt.h, fmin.h, fmax.h, fmadd.h, fnmadd.h, fmsub.h, fnmsub.h, fcvt.w.h, fcvt.wu.h, fcvt.h.w, fcvt.h.wu, fcvt.l.h, fcvt.lu.h, fcvt.h.l, fcvt.h.lu, feq.h, flt.h, fle.h, fgt.h, fge.h, fclass.h. * From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFHMIN_OR_ZHINXMIN: fcvt.s.h and fcvt.h.s. * From INSN_CLASS_D_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_D: fcvt.d.h and fcvt.h.d. * From INSN_CLASS_Q_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_Q: fcvt.q.h and fcvt.h.q. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Change implicit subsets. Zfh->Zicsr is not needed and Zfh->F is replaced with Zfh->Zfhmin and Zfhmin->F. Zhinx->Zicsr is not needed and Zhinx->Zfinx is replaced with Zhinx->Zhinxmin and Zhinxmin->Zfinx. (riscv_supported_std_z_ext): Added zfhmin and zhinxmin. (riscv_multi_subset_supports): Rewrite handling for new instruction classes. (riscv_multi_subset_supports_ext): Updated. (riscv_parse_check_conflicts): Change error message to include zfh and zfhmin extensions. gas/ChangeLog: * testsuite/gas/riscv/zfhmin-d-insn-class-fail.s: New complex error handling test. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l: Likewise. * testsuite/gas/riscv/zhinx.d: Renamed from fp-zhinx-insns.d and refactored. * testsuite/gas/riscv/zhinx.s: Likewise. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Removed INSN_CLASS_ZFH, INSN_CLASS_D_AND_ZFH_INX and INSN_CLASS_Q_AND_ZFH_INX. Added INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, INSN_CLASS_ZFHMIN_AND_D and INSN_CLASS_ZFHMIN_AND_Q. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Change instruction classes for Zfh and Zfhmin instructions. Fix `fcvt.h.lu' instruction (two operand variant) mask.
2022-07-07RISC-V: Fix disassembling Zfinx with -M numericTsukasa OI2-0/+12
This commit fixes floating point operand register names from ABI ones to dynamically set ones. gas/ChangeLog: * testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of Zfinx extension and -M numeric disassembler option. * testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR names to disassemble Zfinx instructions.
2022-07-07RISC-V: Fix requirement handling on Zhinx+{D,Q}Tsukasa OI1-1/+1
This commit fixes how instructions are masked on Zhinx+Z{d,q}inx. fcvt.h.d and fcvt.d.h require ((D&&Zfh)||(Zdinx&&Zhinx)) and fcvt.h.q and fcvt.q.h require ((Q&&Zfh)||(Zqinx&&Zhinx)). bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Fix feature gate on INSN_CLASS_{D,Q}_AND_ZFH_INX. (riscv_multi_subset_supports_ext): Fix feature gate diagnostics on INSN_CLASS_{D,Q}_AND_ZFH_INX. gas/ChangeLog: * testsuite/gas/riscv/fp-zhinx-insns.d: Add Zqinx to -march for proper testing.
2022-07-07PR29320, 'struct obstack' declared inside parameter listAlan Modra2-2/+2
PR 29320 * frags.h: Move declaration of struct obstack.. * as.h: ..to here.
2022-07-06x86: make D attribute usable for XOP and FMA4 insnsJan Beulich1-7/+35
This once again allows to reduce redundancy in (and size of) the opcode table. Don't go as far as also making D work on the two 5-operand XOP insns: This would significantly complicate the code, as there the first (immediate) operand would need special treatment in several places. Note that the .s suffix isn't being enabled to have any effect, for being deprecated. Whereas neither {load} nor {store} pseudo prefixes make sense here, as the respective operands are inputs (loads) only anyway, regardless of order. Hence there is (as before) no way for the programmer to request the alternative encoding to be used for register- only insns. Note further that it is always the first original template which is retained (and altered), to make sure the same encoding as before is used for register-only insns. This has the slightly odd (but pre- existing) effect of XOP register-only insns having XOP.W clear, but FMA4 ones having VEX.W set.
2022-07-06x86: fold two switch() statements in match_template()Jan Beulich1-16/+3
I don't see why two of them were introduced (very long ago) using similar fall-through logic.
2022-07-06x86: fix 3-operand insn reverse-matchingJan Beulich3-18/+19
The middle operand would have gone entirely unchecked, allowing e.g. vmovss %xmm0, %esp, %xmm2 to assemble successfully, or e.g. vmovss %xmm0, $4, %xmm2 causing an internal error. Alongside dealing with this also drop a related comment, which hasn't been applicable anymore since the introduction of 3-operand patterns with D set (and which perhaps never had been logical to be there, as reverse-matched insns don't make it there in the first place).
2022-07-06x86: introduce a state stack for .archJan Beulich5-2/+159
When using just slightly non-trivial combinations of .arch, it can be quite useful to be able to go back to prior state without needing to re-invoke perhaps many earlier directives and without needing to invoke perhaps many "negative" ones. Like some other architectures allow saving (pushing) and restoring (popping) present/prior state. For now require the same .code<N> to be in effect for ".arch pop" that was in effect for the corresponding ".arch push". Also change the global "no_cond_jump_promotion" to be bool, to match the new struct field.
2022-07-06x86: generalize disabling of sub-architecturesJan Beulich1-235/+179
I never really understood upon what basis ".arch .no*" options were made available. Let's not have any "criteria" at all, and simply allow disabling of all of them. Then we also have all data for a sub-arch in a single place, as we now only need a single table.
2022-07-06x86: permit "default" with .archJan Beulich5-8/+85
So far there was no way to reset the architecture to that assembly would start with in the absence of any overrides (command line or directives). Note that for Intel MCU "default" is merely an alias of "iamcu". While there also zap a stray @item from the doc section, as noticed when inspecting the generated output (which still has some quirks, but those aren't easy to address without re-flowing almost the entire section).
2022-07-06x86: don't leak sub-architecture accumulated stringsJan Beulich1-0/+3
While it may not be necessary in i386_target_format() (but then setting the variable to NULL also wouldn't be necessary), at least in the other cases strings may already have accumulated.
2022-07-05x86: introduce fake processor type to mark sub-arch entries in cpu_arch[]Jan Beulich2-4/+10
This is in preparation of dropping the leading . from the strings. While there also move PROCESSOR_GENERIC{32,64} from the middle of AMD entries to near the top.
2022-07-05x86: macro-ize cpu_arch[] entriesJan Beulich1-308/+164
Putting individual elements behind macros, besides (imo) improving readability, will make subsequent (and likely also future) changes less intrusive. Utilize this right away to pack the table a little more tightly, by converting "skip" to bool and putting it earlier in a group of bitfields together with "len".
2022-07-05x86: de-duplicate sub-architecture strings accumulationJan Beulich1-38/+14
Introduce a helper function to replace 4 instances of similar code. Use reconcat() to cover the previously explicit free().
2022-07-04alloc gas seginfo on notes obstackAlan Modra3-18/+62
Lots of memory used in gas should go on this obstack. The patch also frees all the gas obstacks on exit, which isn't a completely trivial task. * subsegs.c (alloc_seginfo): New function. (subseg_change, subseg_get): Use it. (subsegs_end): New function. * as.h (subsegs_end): Declare. * output-file.c: Include subsegs.h (stash_frchain_obs): New function. (output_file_close): Save obstacks attached to output bfd before closing. Call subsegs_end with the array of obstacks.
2022-07-04gas/testsuite: properly exclude aout in all/weakref1uJan Beulich1-1/+1
Use the (wider) predicate rather than a triplet. This eliminates the sole i386-msdos failure in the testsuite.
2022-07-04x86: fold Disp32S and Disp32Jan Beulich2-75/+42
The only case where 64-bit code uses non-sign-extended (can also be considered zero-extended) displacements is when an address size override is in place for a memory operand (i.e. particularly excluding displacements of direct branches, which - if at all - are controlled by operand size, and then are still sign-extended, just from 16 bits). Hence the distinction in templates is unnecessary, allowing code to be simplified in a number of places. The only place where logic becomes more complicated is when signed-ness of relocations is determined in output_disp(). The other caveat is that Disp64 cannot be specified anymore in an insn template at the same time as Disp32. Unlike for non-64-bit mode, templates don't specify displacements for both possible addressing modes; the necessary adjustment to the expected ones has already been done in match_template() anyway (but of course the logic there needs tweaking now). Hence the single template so far doing so is split.
2022-07-04x86: restore masking of displacement kindsJan Beulich1-16/+15
Commit 7d5e4556a375 rendered the check near the end of what is now i386_finalize_displacement() entirely dead for AT&T mode, since for operands involving a displacement .unspecified will always be set. But the logic there is bogus anyway - Intel syntax operand size specifiers are of no interest there either. The only thing which matters in the "displacement only" determination is .baseindex. Of course when masking displacement kinds we should not at the same time also mask off other attributes. Furthermore the type mask returned by lex_got() also needs to be adjusted: The only case where we want Disp32 (rather than Disp32S) is when dealing with 32-bit addressing mode in 64-bit code.
2022-07-04x86-64: improve handling of branches to absolute addressesJan Beulich5-2/+53
There are two related problems here: The use of "addr32" on a direct branch would, besides causing a warning, result in operands to be permitted which mistakenly are refused without "addr32". Plus at some point not too long ago I'm afraid it may have been me who regressed the relocation addends emitted for such branches. Correct both problems, adding a testcase to guard against regressing this again.
2022-06-29opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess7-57/+67
The function aarch64_print_operand (aarch64-opc.c) is responsible for converting an instruction operand into the textual representation of that operand. In some cases, a comment is included in the operand representation, though this (currently) only happens for the last operand of the instruction. In a future commit I would like to enable the new libopcodes styling for AArch64, this will allow objdump and GDB[1] to syntax highlight the disassembler output, however, having operands and comments combined in a single string like this makes such styling harder. In this commit, I propose to extend aarch64_print_operand to take a second buffer. Any comments for the instruction are written into this extra buffer. The two callers of aarch64_print_operand are then updated to pass an extra buffer, and print any resulting comment. In this commit no styling is added, that will come later. However, I have adjusted the output slightly. Before this commit some comments would be separated from the instruction operands with a tab character, while in other cases the comment was separated with two single spaces. After this commit I use a single tab character in all cases. This means a few test cases needed updated. If people would prefer me to move everyone to use the two spaces, then just let me know. Or maybe there was a good reason why we used a mix of styles, I could probably figure out a way to maintain the old output exactly if that is critical. Other than that, there should be no user visible changes after this commit. [1] GDB patches have not been merged yet, but have been posted to the GDB mailing list: https://sourceware.org/pipermail/gdb-patches/2022-June/190142.html
2022-06-28RISC-V: Add 'Sstc' extension and its CSRsTsukasa OI12-0/+125
This commit adds "stimecmp / vstimecmp" Extension (Sstc) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Sstc' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Sstc' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_STIMECMP, CSR_STIMECMPH, CSR_VSTIMECMP, CSR_VSTIMECMPH): New CSR macros.
2022-06-28RISC-V: Add 'Sscofpmf' extension with its CSRsTsukasa OI12-0/+817
This commit adds Count Overflow and Mode-Based Filtering Extension (Sscofpmf) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Sscofpmf' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Sscofpmf' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_SCOUNTOVF, CSR_MHPMEVENT3H, CSR_MHPMEVENT4H, CSR_MHPMEVENT5H, CSR_MHPMEVENT6H, CSR_MHPMEVENT7H, CSR_MHPMEVENT8H, CSR_MHPMEVENT9H, CSR_MHPMEVENT10H, CSR_MHPMEVENT11H, CSR_MHPMEVENT12H, CSR_MHPMEVENT13H, CSR_MHPMEVENT14H, CSR_MHPMEVENT15H, CSR_MHPMEVENT16H, CSR_MHPMEVENT17H, CSR_MHPMEVENT18H, CSR_MHPMEVENT19H, CSR_MHPMEVENT20H, CSR_MHPMEVENT21H, CSR_MHPMEVENT22H, CSR_MHPMEVENT23H, CSR_MHPMEVENT24H, CSR_MHPMEVENT25H, CSR_MHPMEVENT26H, CSR_MHPMEVENT27H, CSR_MHPMEVENT28H, CSR_MHPMEVENT29H, CSR_MHPMEVENT30H, CSR_MHPMEVENT31H): New CSR macros.
2022-06-28RISC-V: Add 'Smstateen' extension and its CSRsTsukasa OI12-0/+525
This commit adds State Enable Extension (Smstateen) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Smstateen' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Smstateen' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_MSTATEEN0, CSR_MSTATEEN1, CSR_MSTATEEN2, CSR_MSTATEEN3, CSR_SSTATEEN0, CSR_SSTATEEN1, CSR_SSTATEEN2, CSR_SSTATEEN3, CSR_HSTATEEN0, CSR_HSTATEEN1, CSR_HSTATEEN2, CSR_HSTATEEN3, CSR_MSTATEEN0H, CSR_MSTATEEN1H, CSR_MSTATEEN2H, CSR_MSTATEEN3H, CSR_HSTATEEN0H, CSR_HSTATEEN1H, CSR_HSTATEEN2H, CSR_HSTATEEN3H): New CSR macros.
2022-06-28RISC-V: Add new CSR feature gate handling (RV32,H)Tsukasa OI1-4/+7
To support feature gate like Smstateen && H, this commit adds certain CSR feature gate handling. It also changes how RV32-only CSRs are handled for cleanliness. gas/ChangeLog: * config/tc-riscv.c (riscv_csr_address): Add CSR feature gate handling for H. Change handling on RV32.
2022-06-27drop XC16x bitsJan Beulich55-2676/+0
Commit 04f096fb9e25 ("Move the xc16x target to the obsolete list") moved the architecture from the "obsolete but still available" to the "obsolete / support removed" list in config.bfd, making the architecture impossible to enable (except maybe via "enable everything" options"). Note that I didn't touch */po/*.po{,t} on the assumption that these would be updated by some (half)automatic means.
2022-06-22RISC-V: Reorder the prefixed extensions which are out of order.Nelson Chu6-15/+0
This patch has been pending for almost a year... However, I noticed that llvm can already re-order the extensions, even if they are out of orders. Not really sure if they can also re-order the single letter extensions, but at least we can do this for the multi-letter extensions in binutils. bfd/ * elfxx-riscv.c (riscv_parse_prefixed_ext): Removed the code which are used to check the prefixed extension orders. gas/ * testsuite/gas/riscv/march-fail-order-x-z.d: Removed since we will help tp reorder the prefixed extensions for now. * testsuite/gas/riscv/march-fail-order-x-z.l: Likewise. * testsuite/gas/riscv/march-fail-order-x.d: Likewise. * testsuite/gas/riscv/march-fail-order-x.l: Likewise. * testsuite/gas/riscv/march-fail-order-z.d: Likewise. * testsuite/gas/riscv/march-fail-order-z.l: Likewise.
2022-06-22RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu12-309/+361
According to the picture 28.1 in the current ISA spec, h is no larger the multi-letter extension, it is a single extension after v. Therefore, this patch fix the implementation, and use the single h to control hypervisor CSRs and instructions, which we promised to do before. bfd/ * elfxx-riscv.c (riscv_supported_std_ext): Added h with version 1.0 after v. (riscv_supported_std_h_ext): Removed. (riscv_all_supported_ext): Updated since riscv_supported_std_h_ext is removed. (riscv_prefix_ext_class): Removed RV_ISA_CLASS_H. (parse_config): Updated since riscv_prefix_ext_class is removed. (riscv_recognized_prefixed_ext): Likewise. (riscv_get_default_ext_version): Likewise. (riscv_multi_subset_supports): Handle INSN_CLASS_H for hypervisor instructions. (riscv_multi_subset_supports_ext): Likewise. gas/ * config/tc-riscv.c (riscv_csr_class): Added CSR_CLASS_H and CSR_CLASS_H_32 for hypervisor CSRs. (riscv_csr_address): Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Updated since hypervisor CSRs are controlled by single h extension for now. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/h-ext-32.d: Added h to architecture string. * testsuite/gas/riscv/h-ext-64.d: Likewise. * testsuite/gas/riscv/march-fail-single-prefix-h: Removed since h is no longer multi-letter extension. * testsuite/gas/riscv/march-fail-unknown-h.d: Likewise. include/ * opcode/riscv-opc.h: Control hypervisor CSRs by h extension, rather than the privileged spec verisons. * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_H. opcodes/ * riscv-opc.c (riscv_opcodes): Control hypervisor instructions by h extension.
2022-06-22RISC-V: Fix inconsistent error message (range)Tsukasa OI1-1/+1
This commit fixes inconsistent error message format involving compressed funct<n> fields. In specific, funct6 had an error message with range 0..2^<n> ("0..64") unlike other funct<n> fields with 0..2^<n>-1 (e.g. funct4 with "0..15"). gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Fix inconsistent error message.
2022-06-17PR29256, memory leak in obj_elf_section_nameAlan Modra1-14/+18
When handling section names in quotes obj_elf_section_name calls demand_copy_C_string, which puts the name on the gas notes obstack. Such strings aren't usually freed, since obstack_free frees all more recently allocated objects as well as its arg. When handling non-quoted names, obj_elf_section_name mallocs the name. Due to the mix of allocation strategies it isn't possible for callers to free names, if that was desirable. Partially fix this by always creating names on the obstack, which is more efficient anyway. (You still can't obstack_free on error paths due to the xtensa tc_canonicalize_section_name.) Also remove a couple of cases where the name is dup'd for no good reason as far as I know. PR 29256 * config/obj-elf.c (obj_elf_section_name): Create name on notes obstack. (obj_elf_attach_to_group): Don't strdup group name. (obj_elf_section): Likewise. (obj_elf_vendor_attribute): Use xmemdup0 rather than xstrndup.
2022-06-16use of uninitialised value in input_file_openAlan Modra1-7/+7
Triggered by a file containing just "#N" or "#A". fgets when hitting EOF before reading anything returns NULL and does not write to buf. strchr (buf, '\n') then is reading from uninitialised memory. * input-file.c (input_file_open): Don't assume buf contains zero string terminator when fgets returns NULL.
2022-06-16Restore readelf -wFAlan Modra1-1/+1
Commit 94585d6d4495 resulted in readelf -wF failing with Unrecognized debug letter option 'F' binutils/ * dwarf.c (debug_dump_long_opts): Add letter. (debug_option_table): New, replacing.. (opts_table, letter_table): ..these. (dwarf_select_sections_by_names): Adjust to suit. Set do_debug_frames outside of loop. (dwarf_select_sections_by_letters): Similarly. gas/ * testsuite/gas/i386/ehinterp.d: Use readelf -wF.
2022-06-16PR29250, readelf erases CIE initial register stateAlan Modra3-1/+56
PR 29250 binutils/ * dwarf.c (display_debug_frames): Set col_type[reg] on sizing pass over FDE to cie->col_type[reg] if CIE specifies reg. Handle DW_CFA_restore and DW_CFA_restore_extended on second pass using the same logic. Remove unnecessary casts. Don't call frame_need_space on second pass over FDE. gas/ * testsuite/gas/i386/ehinterp.d, * testsuite/gas/i386/ehinterp.s: New test. * testsuite/gas/i386/i386.exp: Run it.
2022-06-14BFD_RELOC_MIPS_16Alan Modra1-8/+8
MIPS should not be using BFD_RELOC_16 for its R_MIPS_16 relocation, since R_MIPS_16 specifies a 16-bit field in a 32-bit word. BFD_RELOC_16, emitted by generic code to handle fixups on 16-bit data directives, expects fixups to operate on the whole of a 16-bit word. This patch corrects the problem by using BFD_RELOC_MIPS_16, a new bfd reloc that is used to generate R_MIPS_16. BFD_RELOC_16 is handled in md_apply_fix for cases where the fixup can be applied at assembly time. Like BFD_RELOC_8, BFD_RELOC_16 now has no corresponding object file relocation, and thus .half, .hword, .short and .dc.w must be resolved at assembly time. BFD_RELOC_MIPS_REL16 is removed by this patch since it isn't used. PR 3243 PR 26542 * reloc.c (BFD_RELOC_MIPS_16): Rename from BFD_RELOC_MIPS_REL16. * elf32-mips.c (mips_reloc_map): Map BFD_RELOC_MIPS_16 to R_MIPS_16. * elf64-mips.c (mips_reloc_map): Likewise, delete BFD_RELOC_MIPS_REL16. * elfn32-mips.c (mips_reloc_map): Likewise. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-mips.c (append_insn): Handle BFD_RELOC_MIPS_16. (macro_build): Likewise. (mips_percent_op <%half>): Generate BFD_RELOC_MIPS_16. (md_apply_fix): Handle BFD_RELOC_16 and BFD_RELOC_MIPS_16 when fx_done. ld/ * testsuite/ld-mips-elf/reloc-local-overflow.d, * testsuite/ld-mips-elf/reloc-local-overflow.s: Rewrite.
2022-06-14gas dwarf2dbg.c tidyAlan Modra5-41/+81
Make it a little more obvious that remap_debug_filename returns an allocated string (that should be freed) by returning a char * rather than const char *. Free a few missed cases in dwarf2dbg.c, and free other memory allocated in dwarf2dbg.c. Also remove static initialisation of variables and initialise in dwarf2_init instead, in order to ensure gas state is saner for oss-fuzz. * remap.c (remap_debug_filename): Remove const from return. * as.h (remap_debug_filename): Update prototype. * config/obj-elf.c (obj_elf_ident): Simplify free of remap_debug_filename output. * stabs.c (stabs_generate_asm_file): Likewise. * dwarf2dbg.c (dirs, dirs_in_use, dirs_allocated, current): Don't initialise statically.. (dwarf2_init): ..do so here, along with most other static vars. (assign_file_to_slot): Don't set files_allocated until we succeed in allocating memory. (purge_generated_debug): Add bool param, free more stuff if true. (dwarf2_directive_filename): Adjust purge_generated_debug call. (process_entries): Don't free line_entry here.. (dwarf2_cleanup): ..do so here instead, new function. (dwarf2_finish): Call dwarf2_cleanup. When chaining together subseg line entries, unhook entries from old subseg list. (dwarf2_directive_loc): Free remap_debug_filename string. (out_dir_and_file_list): Likewise. (out_debug_str): Likewise.
2022-06-08asan: double free sb_killAlan Modra1-2/+1
oss-fuzz hits a flaky crash with a double-free. I think this is due to gas static state not being reinitialised between testcases, a bug with oss-fuzz not gas. Anyway, this patch should avoid the problem. * input-scrub.c (input_scrub_push): Move init of sb_index.. (input_scrub_reinit): ..to here.
2022-06-03Re: ubsan: undefined shift in frag_align_codeAlan Modra1-1/+2
This one needs the same fix too. * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Avoid signed integer overflow.
2022-06-03x86: exclude certain ISA extensions from v3/v4 ISAJan Beulich8-4/+43
Like TBM and LWP, XOP and FMA4 also shouldn't be included in v3. Like AVX512-4VNNIW, AVX512-4FMAPS also shouldn't be included in v4.
2022-06-02Re: ubsan: signed integer overflow in atof_genericAlan Modra1-0/+1
Oops. * atof-generic.c: Include limits.h.
2022-06-02ubsan: signed integer overflow in atof_genericAlan Modra1-8/+8
Fix the signed overflows by using unsigned variables and detect overflow at BUG! comment. * atof-generic.c (atof_generic): Avoid signed integer overflow. Return ERROR_EXPONENT_OVERFLOW if exponent overflows a long.
2022-06-02ubsan: undefined shift in frag_align_codeAlan Modra1-1/+1
* frags.c (MAX_MEM_FOR_RS_ALIGN_CODE): Avoid signed integer overflow.
2022-06-02gas read_a_source_file #APP processingAlan Modra1-91/+10
This fixes some horrible code using do_scrub_chars. What we had ran text through do_scrub_chars twice, directly in read_a_source_file and again via the input_scrub_include_sb call. That's silly, and since do_scrub_chars is a state machine, possibly wrong. More silliness is evident in the temporary malloc'd buffer for do_scrub_chars output, which should have been written directly to sbuf. So, get rid of the do_scrub_chars call and support functions, leaving scrubbing to input_scrub_include_sb. I did wonder about #NO_APP overlapping input_scrub_next_buffer buffers, but that should only happen if the string starts in one file and finishes in another. * read.c (scrub_string, scrub_string_end): Delete. (scrub_from_string): Delete. (read_a_source_file): Rewrite #APP processing.
2022-06-02sb_scrub_and_add_sb not draining input string bufferAlan Modra1-2/+14
It is possible for sb_scrub_and_add_sb to not consume all of the input string buffer. If this happens for reasons explained in the comment, do_scrub_chars can leave pointers to the string buffer for the next call. This patch fixes that by ensuring the input is drained. Note that the behaviour for an empty string buffer is also changed, avoiding another do_scrub_chars bug where empty input and single char sized output buffers could result in a write past the end of the output. sb.c (sb_scrub_and_add_sb): Loop until all of input sb is consumed.
2022-06-02asan: heap buffer overflow in dwarf2_directive_filenameAlan Modra1-3/+5
Seen with .file 4294967289 "xxx.c" * dwarf2dbg.c (assign_file_to_slot): Catch more cases of integer overflow. Make param i an unsigned int.
2022-05-31ia64 gas: Remove unnecessary initAlan Modra1-2/+0
The whole struct is cleared by alloc_record. * config/tc-ia64.c (output_prologue, output_prologue_gr): Don't zero r.record.r.mask.
2022-05-31Trailing spaces in objdump -r headerAlan Modra106-142/+142
git commit 202be274a4 went a little wild in removing trailing spaces in gas/testsuite/gas/i386/{secidx.d,secrel.d}, causing x86_64-w64-mingw32 +FAIL: i386 secrel reloc x86_64-w64-mingw32 +FAIL: i386 secidx reloc I could have just replaced the trailing space, but let's fix the objdump output instead. Touches lots of testsuite files.
2022-05-30Fix failing test for armeb-gnu-eabiLuis Machado1-18/+2
The following test fails on the armeb-gnu-eabi target: FAIL: Unwind information for Armv8.1-M.Mainline PACBTI extension This patch adjusts the expected output for big endian.
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