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2020-10-21aarch64: Add testcase for HCR_EL2 system registerPrzemyslaw Wirkus2-0/+11
HCR_EL2 is a 64-bit Hypervisor Configuration Register. gas/ChangeLog: 2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * testsuite/gas/aarch64/sysreg-6.d: New test. * testsuite/gas/aarch64/sysreg-6.s: New test.
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian18-3/+263
gas/ * config/tc-i386.c (cpu_arch): Add CPU_ZNVER3_FLAGS flags. (i386_align_code): Add PROCESSOR_ZNVER cases. * doc/c-i386.texi: Add znver3, snp, invlpgb and tlbsync. * gas/i386/i386.exp: Add new znver3 test cases. * gas/i386/arch-14-znver3.d: New. * gas/i386/arch-14.d: New. * gas/i386/arch-14.s: New. * gas/i386/invlpgb.d: New. * gas/i386/invlpgb64.d: New. * gas/i386/invlpgb.s: New. * gas/i386/snp.d: New. * gas/i386/snp64.d: New. * gas/i386/snp.s: New. * gas/i386/tlbsync.d: New. * gas/i386/tlbsync.s: New. * gas/i386/x86-64-arch-4-znver3.d: New. * gas/i386/x86-64-arch-4.d: New. * gas/i386/x86-64-arch-4.s: New. opcodes/ * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb. * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS, CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS. Add CPU_ZNVER3_FLAGS. (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP. * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP. * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate, rmpupdate, rmpadjust. * i386-init.h: Re-generated. * i386-tbl.h: Re-generated.
2020-10-17gas: Add a -gdwarf-5 debug_line test with .s fileH.J. Lu4-0/+62
PR gas/25878 PR gas/26740 * testsuite/gas/i386/dwarf5-line-4.d: New file. * testsuite/gas/i386/dwarf5-line-4.s: Likewise. * testsuite/gas/i386/i386.exp: Run dwarf5-line-4.
2020-10-17gas: Replace dwarf5-line-2.S with dwarf5-line-3.SH.J. Lu3-4/+12
PR gas/25878 PR gas/26740 * testsuite/gas/i386/dwarf5-line-3.s: Replace dwarf5-line-2.S with dwarf5-line-3.S. * testsuite/gas/i386/dwarf5-line-3.d: Updated.
2020-10-17gas: Always use as_where for preprocessed assembly codesH.J. Lu7-19/+155
Always clear the slot 1 if it was assigned to the input file before the first .file <NUMBER> directive has been seen. Always use as_where to generate the correct debug infor for preprocessed assembly codes. PR gas/25878 PR gas/26740 * dwarf2dbg.c (allocate_filename_to_slot): Don't reuse the slot 1 here. (dwarf2_where): Restore as_where. (dwarf2_directive_filename): Clear the slot 1 if it was assigned to the input file. * testsuite/gas/i386/dwarf5-line-2.d: New file. * testsuite/gas/i386/dwarf5-line-2.s: Likewise. * testsuite/gas/i386/dwarf5-line-3.d: Likewise. * testsuite/gas/i386/dwarf5-line-3.s: Likewise. * testsuite/gas/i386/i386.exp: Run dwarf5-line-2 and dwarf5-line-3.
2020-10-16gas: Reuse the input file entry in the file tableH.J. Lu5-19/+84
Some instructions can be emitted (dwarf2_emit_insn is called) before the first .file <NUMBER> directive has been seen, which allocates the input file as the first file entry. Reuse the input file entry in the file table. PR gas/25878 PR gas/26740 * dwarf2dbg.c (file_entry): Remove auto_assigned. (assign_file_to_slot): Remove the auto_assign argument. (allocate_filenum): Updated. (allocate_filename_to_slot): Reuse the input file entry in the file table. (dwarf2_where): Replace as_where with as_where_physical. * testsuite/gas/i386/dwarf5-line-1.d: New file. * testsuite/gas/i386/dwarf5-line-1.s: Likewise. * testsuite/gas/i386/i386.exp: Run dwarf5-line-1.
2020-10-16Enhancement for avx-vnni patchCui,Lili11-28/+41
1. Rename CpuVEX_PREFIX to PseudoVexPrefix and move it from cpu_flags to opcode_modifiers. 2. Delete {vex2} invalid test. 3. Use VexW0 and VexVVVV in the AVX-VNNI instructions. gas/ * config/tc-i386.c: Move Pseudo Prefix check to match_template. * testsuite/gas/i386/avx-vnni-inval.l: New file. * testsuite/gas/i386/avx-vnni-inval.s: Likewise. * testsuite/gas/i386/avx-vnni.d: Delete invalid {vex2} test. * testsuite/gas/i386/avx-vnni.s: Likewise. * testsuite/gas/i386/i386.exp: Add AVX VNNI invalid tests. * testsuite/gas/i386/x86-64-avx-vnni-inval.l: New file. * testsuite/gas/i386/x86-64-avx-vnni-inval.s: Likewise. * testsuite/gas/i386/x86-64-avx-vnni.d: Delete invalid {vex2} test. * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise. opcodes/ * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix and move it from cpu_flags to opcode_modifiers. Use VexW0 and VexVVVV in the AVX-VNNI instructions. * i386-gen.c: Likewise. * i386-opc.h: Likewise. * i386-opc.h: Likewise. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2020-10-14x86: Support Intel AVX VNNIH.J. Lu9-2/+171
Intel AVX VNNI instructions are marked with CpuVEX_PREFIX. Without the pseudo {vex} prefix, mnemonics of Intel VNNI instructions are encoded with the EVEX prefix. The pseudo {vex} prefix can be used to encode mnemonics of Intel VNNI instructions with the VEX prefix. gas/ * NEWS: Add Intel AVX VNNI. * config/tc-i386.c (cpu_arch): Add .avx_vnni and noavx_vnni. (cpu_flags_match): Support CpuVEX_PREFIX. * doc/c-i386.texi: Document .avx_vnni, noavx_vnni and how to encode Intel VNNI instructions with VEX prefix. * testsuite/gas/i386/avx-vnni.d: New file. * testsuite/gas/i386/avx-vnni.s: Likewise. * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise. * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX VNNI tests. opcodes/ * i386-dis.c (PREFIX_VEX_0F3850): New. (PREFIX_VEX_0F3851): Likewise. (PREFIX_VEX_0F3852): Likewise. (PREFIX_VEX_0F3853): Likewise. (VEX_W_0F3850_P_2): Likewise. (VEX_W_0F3851_P_2): Likewise. (VEX_W_0F3852_P_2): Likewise. (VEX_W_0F3853_P_2): Likewise. (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851, PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853. (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2, VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2. (putop): Add support for "XV" to print "{vex3}" pseudo prefix. * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and CPU_ANY_AVX_VNNI_FLAGS. (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX. * i386-opc.h (CpuAVX_VNNI): New. (CpuVEX_PREFIX): Likewise. (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix. * i386-opc.tbl: Add Intel AVX VNNI instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2020-10-14x86: Add support for Intel HRESET instructionLili Cui8-1/+50
gas/ * NEWS: Add Intel HRESET. * config/tc-i386.c (cpu_arch): Add .hreset. (cpu_noarch): Likewise. * doc/c-i386.texi: Document .hreset, nohreset. * testsuite/gas/i386/i386.exp: Run HRESET tests. * testsuite/gas/i386/hreset.d: New file. * testsuite/gas/i386/x86-64-hreset.d: Likewise. * testsuite/gas/i386/hreset.s: Likewise. opcodes/ * i386-dis.c (PREFIX_0F3A0F): New. (MOD_0F3A0F_PREFIX_1): Likewise. (REG_0F3A0F_PREFIX_1_MOD_3): Likewise. (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise. (prefix_table): Add PREFIX_0F3A0F. (mod_table): Add MOD_0F3A0F_PREFIX_1. (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3. (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0. * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS, CPU_ANY_HRESET_FLAGS. (cpu_flags): Add CpuHRESET. (output_i386_opcode): Allow 4 byte base_opcode. * i386-opc.h (enum): Add CpuHRESET. (i386_cpu_flags): Add cpuhreset. * i386-opc.tbl: Add Intel HRESET instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-10-14x86: Support Intel UINTRLili Cui7-1/+46
gas/ * NEWS: Add Intel UINTR. * config/tc-i386.c (cpu_arch): Add .uintr. (cpu_noarch): Likewise. * doc/c-i386.texi: Document .uintr and nouintr. * testsuite/gas/i386/i386.exp: Run UINTR tests. * testsuite/gas/i386/x86-64-uintr.d: Likewise. * testsuite/gas/i386/x86-64-uintr.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_MOD_3_0F01_REG_5_RM_4, PREFIX_MOD_3_0F01_REG_5_RM_5, PREFIX_MOD_3_0F01_REG_5_RM_6, PREFIX_MOD_3_0F01_REG_5_RM_7, X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1, X86_64_0FC7_REG_6_MOD_3_PREFIX_1. (prefix_table): New instructions (see prefixes above). (rm_table): Likewise * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS, CPU_ANY_UINTR_FLAGS. (cpu_flags): Add CpuUINTR. * i386-opc.h (enum): Add CpuUINTR. (i386_cpu_flags): Add cpuuintr. * i386-opc.tbl: Add UINTR insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-10-14x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu2-24/+29
Replace the prefix byte in non-VEX/EVEX base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3. gas/ * config/tc-i386.c (load_insn_p): Check opcodeprefix == 0 for base_opcode == 0xfc7. (match_template): Likewise. (process_suffix): Check opcodeprefix == PREFIX_0XF2 for CRC32. (check_byte_reg): Likewise. (output_insn): Don't add the 0xf3 prefix twice for PadLock instructions. Don't add prefix from non-VEX/EVEX base_opcode. opcodes/ * i386-gen.c (process_i386_opcode_modifier): Return 1 for non-VEX/EVEX/prefix encoding. (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode has a prefix byte. * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3. * i386-tbl.h: Regenerated.
2020-10-13x86: Rename VexOpcode to OpcodePrefixH.J. Lu2-30/+53
Rename VexOpcode to OpcodePrefix so that OpcodePrefix can be used for regular encoding prefix. gas/ * config/tc-i386.c (build_vex_prefix): Replace vexopcode with opcodeprefix. (build_evex_prefix): Likewise. (is_any_vex_encoding): Don't check vexopcode. (output_insn): Handle opcodeprefix. opcodes/ * i386-gen.c (opcode_modifiers): Replace VexOpcode with OpcodePrefix. * i386-opc.h (VexOpcode): Renamed to ... (OpcodePrefix): This. (PREFIX_NONE): New. (PREFIX_0X66): Likewise. (PREFIX_0XF2): Likewise. (PREFIX_0XF3): Likewise. * i386-opc.tbl (Prefix_0X66): New. (Prefix_0XF2): Likewise. (Prefix_0XF3): Likewise. Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd. Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq. * i386-tbl.h: Regenerated.
2020-10-09x86: Support GNU_PROPERTY_X86_ISA_1_V[234] markerH.J. Lu34-123/+218
GCC 11 supports -march=x86-64-v[234] to enable x86 micro-architecture ISA levels: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97250 Update GNU_PROPERTY_X86_ISA_1_XXX macros: https://gitlab.com/x86-psABIs/x86-64-ABI/-/merge_requests/13 in x86 ELF binaries to indicate that micro-architecture ISA levels required to execute the binary: #define GNU_PROPERTY_X86_ISA_1_NEEDED (GNU_PROPERTY_X86_UINT32_OR_LO + 2) #define GNU_PROPERTY_X86_ISA_1_USED (GNU_PROPERTY_X86_UINT32_OR_AND_LO + 2) #define GNU_PROPERTY_X86_ISA_1_V2 (1U << 0) #define GNU_PROPERTY_X86_ISA_1_V3 (1U << 1) #define GNU_PROPERTY_X86_ISA_1_V4 (1U << 2) The previous GNU_PROPERTY_X86_ISA_1_XXX macros are deprecated and renamed to GNU_PROPERTY_X86_COMPAT_2_ISA_1_XXX. In addition to EM_X86_64, GNU_PROPERTY_X86_ISA_1_V[234] marker can be used by ld.so to detect the x86-64-v4 shared library placed in an x86-64-v2 directory by mistake on an x86-64-v2 machine to avoid crashes on x86-64-v4 instructions. Add -z x86-64-v[234] linker command line option to mark x86-64-v[234] ISA level as needed. Also add #define GNU_PROPERTY_X86_FEATURE_2_MASK (1U << 11) for mask registers. bfd/ PR gas/26703 * elf-linker-x86.h (elf_linker_x86_params): Add isa_level. * elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Merge GNU_PROPERTY_X86_ISA_1_V[234]. (_bfd_x86_elf_link_setup_gnu_properties): Generate GNU_PROPERTY_X86_ISA_1_V[234] for -z x86-64-v[234]. binutils/ PR gas/26703 * readelf.c (decode_x86_compat_2_isa): New function. (decode_x86_isa): Updated for new X86_ISA_1_XXX bits. (decode_x86_feature_1): Handle GNU_PROPERTY_X86_FEATURE_2_MASK. (print_gnu_property_note): Handle X86_COMPAT_2_ISA_1_USED, and X86_COMPAT_2_ISA_1_NEEDED. * testsuite/binutils-all/i386/pr21231b.s: Updated to the current GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_ISA_1_NEEDED values. * testsuite/binutils-all/x86-64/pr21231b.s: Likewise. * testsuite/binutils-all/x86-64/pr23494a.s: Likewise. * testsuite/binutils-all/x86-64/pr23494b.s: Likewise. * testsuite/binutils-all/x86-64/pr23494c.s: Likewise. * testsuite/binutils-all/i386/empty.d: Updated. * testsuite/binutils-all/i386/ibt.d: Likewise. * testsuite/binutils-all/i386/pr21231a.d: Likewise. * testsuite/binutils-all/i386/pr21231b.d: Likewise. * testsuite/binutils-all/i386/shstk.d: Likewise. * testsuite/binutils-all/x86-64/empty-x32.d: Likewise. * testsuite/binutils-all/x86-64/empty.d: Likewise. * testsuite/binutils-all/x86-64/ibt-x32.d: Likewise. * testsuite/binutils-all/x86-64/ibt.d: Likewise. * testsuite/binutils-all/x86-64/pr21231a.d: Likewise. * testsuite/binutils-all/x86-64/pr21231b.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e.d: Likewise. * testsuite/binutils-all/x86-64/shstk-x32.d: Likewise. * testsuite/binutils-all/x86-64/shstk.d: Likewise. gas/ PR gas/26703 * config/tc-i386.c (xstate): Add xstate_mask. (md_assemble): Check i.types[j], instead of i.tm.operand_types[j], for xstate. Set xstate_mask, instead of xstate_zmm, for RegMask. (output_insn): Update for GNU_PROPERTY_X86_ISA_1_V[234]. Update xstate for mask register and VSIB. * testsuite/gas/i386/i386.exp: Run more GNU_PROPERTY tests. * testsuite/gas/i386/property-1.s: Updated to the current GNU_PROPERTY_X86_ISA_1_USED value. * testsuite/gas/i386/property-2.s: Only keep cmove. * testsuite/gas/i386/property-3.s: Changed to addsubpd. * testsuite/gas/i386/property-1.d: Updated. * testsuite/gas/i386/property-2.d: Likewise. * testsuite/gas/i386/property-3.d: Likewise. * testsuite/gas/i386/property-4.d: Likewise. * testsuite/gas/i386/property-5.d: Likewise. * testsuite/gas/i386/property-6.d: Likewise. * testsuite/gas/i386/x86-64-property-1.d: Likewise. * testsuite/gas/i386/x86-64-property-2.d: Likewise. * testsuite/gas/i386/x86-64-property-3.d: Likewise. * testsuite/gas/i386/x86-64-property-4.d: Likewise. * testsuite/gas/i386/x86-64-property-5.d: Likewise. * testsuite/gas/i386/x86-64-property-6.d: Likewise. * testsuite/gas/i386/x86-64-property-7.d: Likewise. * testsuite/gas/i386/x86-64-property-8.d: Likewise. * testsuite/gas/i386/x86-64-property-9.d: Likewise. * testsuite/gas/i386/property-11.d: New file. * testsuite/gas/i386/property-11.s: Likewise. * testsuite/gas/i386/property-12.d: Likewise. * testsuite/gas/i386/property-12.s: Likewise. * testsuite/gas/i386/property-13.d: Likewise. * testsuite/gas/i386/property-13.s: Likewise. * testsuite/gas/i386/x86-64-property-11.d: Likewise. * testsuite/gas/i386/x86-64-property-12.d: Likewise. * testsuite/gas/i386/x86-64-property-13.d: Likewise. * testsuite/gas/i386/x86-64-property-14.d: Likewise. * testsuite/gas/i386/x86-64-property-14.s: Likewise. include/ PR gas/26703 * elf/common.h (GNU_PROPERTY_X86_ISA_1_USED): Renamed to ... (GNU_PROPERTY_X86_COMPAT_2_ISA_1_USED): This. (GNU_PROPERTY_X86_ISA_1_NEEDED): Renamed to ... (GNU_PROPERTY_X86_COMPAT_2_ISA_1_NEEDED): This. (GNU_PROPERTY_X86_ISA_1_XXX): Renamed to ... (GNU_PROPERTY_X86_COMPAT_2_ISA_1_XXX): This. (GNU_PROPERTY_X86_ISA_1_NEEDED): New. (GNU_PROPERTY_X86_ISA_1_USED): Likewise. (GNU_PROPERTY_X86_ISA_1_V2): Likewise. (GNU_PROPERTY_X86_ISA_1_V3): Likewise. (GNU_PROPERTY_X86_ISA_1_V4): Likewise. (GNU_PROPERTY_X86_FEATURE_2_MASK): Likewise. ld/ PR gas/26703 * NEWS: Mention -z x86-64-v[234]. * ld.texi: Document -z x86-64-v[234]. * emulparams/elf32_x86_64.sh: Use x86-64-level.sh. * emulparams/elf_i386.sh: Likewise. * emulparams/elf_x86_64.sh: Likewise. * emulparams/x86-64-level.sh: New file. * testsuite/ld-elf/x86-feature-1a.rd: Update. * testsuite/ld-elf/x86-feature-1b.rd: Likewise. * testsuite/ld-elf/x86-feature-1c.rd: Likewise. * testsuite/ld-elf/x86-feature-1d.rd: Likewise. * testsuite/ld-elf/x86-feature-1e.rd: Likewise. * testsuite/ld-i386/pr23372c.d: Likewise. * testsuite/ld-i386/pr23486c.d: Likewise. * testsuite/ld-i386/pr23486d.d: Likewise. * testsuite/ld-i386/pr24322a.d: Likewise. * testsuite/ld-i386/pr24322b.d: Likewise. * testsuite/ld-i386/property-1a.r: Likewise. * testsuite/ld-i386/property-2a.r: Likewise. * testsuite/ld-i386/property-3.r: Likewise. * testsuite/ld-i386/property-3a.r: Likewise. * testsuite/ld-i386/property-4.r: Likewise. * testsuite/ld-i386/property-4a.r: Likewise. * testsuite/ld-i386/property-5.r: Likewise. * testsuite/ld-i386/property-5a.r: Likewise. * testsuite/ld-i386/property-7a.r: Likewise. * testsuite/ld-i386/property-x86-3.d: Likewise. * testsuite/ld-i386/property-x86-4a.d: Likewise. * testsuite/ld-i386/property-x86-5.d: Likewise. * testsuite/ld-i386/property-x86-cet1.d: Likewise. * testsuite/ld-i386/property-x86-cet2a.d: Likewise. * testsuite/ld-i386/property-x86-cet5a.d: Likewise. * testsuite/ld-i386/property-x86-cet5b.d: Likewise. * testsuite/ld-i386/property-x86-ibt1a.d: Likewise. * testsuite/ld-i386/property-x86-ibt1b.d: Likewise. * testsuite/ld-i386/property-x86-ibt2.d: Likewise. * testsuite/ld-i386/property-x86-ibt3a.d: Likewise. * testsuite/ld-i386/property-x86-ibt3b.d: Likewise. * testsuite/ld-i386/property-x86-ibt4.d: Likewise. * testsuite/ld-i386/property-x86-ibt5.d: Likewise. * testsuite/ld-i386/property-x86-shstk1a.d: Likewise. * testsuite/ld-i386/property-x86-shstk1b.d: Likewise. * testsuite/ld-i386/property-x86-shstk2.d: Likewise. * testsuite/ld-i386/property-x86-shstk3a.d: Likewise. * testsuite/ld-i386/property-x86-shstk3b.d: Likewise. * testsuite/ld-i386/property-x86-shstk4.d: Likewise. * testsuite/ld-i386/property-x86-shstk5.d: Likewise. * testsuite/ld-x86-64/pr23372c-x32.d: Likewise. * testsuite/ld-x86-64/pr23372c.d: Likewise. * testsuite/ld-x86-64/pr23486c.d: Likewise. * testsuite/ld-x86-64/pr23486d-x32.d: Likewise. * testsuite/ld-x86-64/pr23486d.d: Likewise. * testsuite/ld-x86-64/pr24322a-x32.d: Likewise. * testsuite/ld-x86-64/pr24322a.d: Likewise. * testsuite/ld-x86-64/pr24322b-x32.d: Likewise. * testsuite/ld-x86-64/pr24322b.d: Likewise. * testsuite/ld-x86-64/pr24458a-x32.d: Likewise. * testsuite/ld-x86-64/pr24458a.d: Likewise. * testsuite/ld-x86-64/pr24458b-x32.d: Likewise. * testsuite/ld-x86-64/pr24458b.d: Likewise. * testsuite/ld-x86-64/pr24458c-x32.d: Likewise. * testsuite/ld-x86-64/pr24458c.d: Likewise. * testsuite/ld-x86-64/property-1a.r: Likewise. * testsuite/ld-x86-64/property-2a.r: Likewise. * testsuite/ld-x86-64/property-3.r: Likewise. * testsuite/ld-x86-64/property-3a.r: Likewise. * testsuite/ld-x86-64/property-4.r: Likewise. * testsuite/ld-x86-64/property-4a.r: Likewise. * testsuite/ld-x86-64/property-5.r: Likewise. * testsuite/ld-x86-64/property-5a.r: Likewise. * testsuite/ld-x86-64/property-7a.r: Likewise. * testsuite/ld-x86-64/property-x86-3-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-3.d: Likewise. * testsuite/ld-x86-64/property-x86-4a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-4a.d: Likewise. * testsuite/ld-x86-64/property-x86-5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-5.d: Likewise. * testsuite/ld-x86-64/property-x86-cet1-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet1.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5.d: Likewise. * testsuite/ld-i386/i386.exp: Run property-x86-6, property-x86-isa1, property-x86-isa2 and property-x86-isa3. * testsuite/ld-i386/property-x86-1.S: Updated to the current GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_ISA_1_NEEDED values. * testsuite/ld-i386/property-x86-2.S: Likewise. * testsuite/ld-i386/property-x86-3.s: Likewise. * testsuite/ld-x86-64/pr23372d.s: Likewise. * testsuite/ld-x86-64/pr23372e.s: Likewise. * testsuite/ld-x86-64/pr23372f.s: Likewise. * testsuite/ld-x86-64/pr23486c.s: Likewise. * testsuite/ld-x86-64/pr23486d.s: Likewise. * testsuite/ld-x86-64/property-x86-1.S: Likewise. * testsuite/ld-x86-64/property-x86-2.S: Likewise. * testsuite/ld-x86-64/property-x86-3.s: Likewise. * testsuite/ld-x86-64/property-x86-5a.s: Likewise. * testsuite/ld-x86-64/property-x86-5b.s: Likewise. * testsuite/ld-i386/property-x86-6.d: New file. * testsuite/ld-i386/property-x86-isa1.d: Likewise. * testsuite/ld-i386/property-x86-isa2.d: Likewise. * testsuite/ld-i386/property-x86-isa3.d: Likewise. * testsuite/ld-x86-64/property-x86-6-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-6.d: Likewise. * testsuite/ld-x86-64/property-x86-6.s: Likewise. * testsuite/ld-x86-64/property-x86-isa1-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-isa1.d: Likewise. * testsuite/ld-x86-64/property-x86-isa1.s: Likewise. * testsuite/ld-x86-64/property-x86-isa2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-isa2.d: Likewise. * testsuite/ld-x86-64/property-x86-isa3-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-isa3.d: Likewise. * testsuite/ld-x86-64/simple.s: Likewise. * ld/testsuite/ld-x86-64/x86-64.exp: Run property-x86-6, property-x86-6-x32, property-x86-isa1, property-x86-isa1-x32, property-x86-isa2, property-x86-isa2-x32, property-x86-isa3-x32 and property-x86-isa3.
2020-10-06aarch64: Fix bogus type punning in parse_barrier() [PR26699]Alex Coplan4-7/+11
This patch fixes a bogus use of type punning in parse_barrier() which was causing an assembly failure on big endian LP64 hosts when attempting to assemble "isb sy" for AArch64. The type of the entries in aarch64_barrier_opt_hsh is aarch64_name_value_pair. We were incorrectly casting this to the locally-defined asm_barrier_opt which has a wider type (on LP64) for the second member. This happened to work on little-endian hosts but fails on LP64 big endian. The fix is to use the correct type in parse_barrier(). This makes the locally-defined asm_barrier_opt redundant, so remove it. gas/ChangeLog: * config/tc-aarch64.c (asm_barrier_opt): Delete. (parse_barrier): Fix bogus type punning. * testsuite/gas/aarch64/system.d: Update disassembly. * testsuite/gas/aarch64/system.s: Add isb sy test.
2020-10-06A small set of code improvements for the Z80 assembler.Sergey Belyashav2-7/+33
PR 26692 * config/tc-z80.c (md_begin): Ensure that xpressions are empty before using them. (unify_indexed): Likewise. (z80_start_line_hook): Improve hash sign handling when SDCC compatibility mode enabled. (md_parse_exp_not_indexed): Improve indirect addressing detection. (md_pseudo_table): Accept hd64 as an alias of z810.
2020-10-06Fix gas sh-link-zero test for hppa64-hpuxAlan Modra2-7/+11
* testsuite/gas/elf/sh-link-zero.s: Don't start directives in first column. Don't use numeric labels.
2020-10-05[PATCH][GAS][AArch64] Update Cortex-X1 feature flagsPrzemyslaw Wirkus1-2/+6
This is feature flags update for Cortex-X1 CPU. For more information about this processor, see [0]. [0] : https://www.arm.com/products/cortex-x gas/ChangeLog: 2020-10-05 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * config/tc-aarch64.c: Update Cortex-X1 feature flags.
2020-10-05[PATCH][GAS][arm] Update Cortex-X1 feature flagsPrzemyslaw Wirkus1-1/+1
This is feature flags update for Cortex-X1 CPU. For more information about this processor, see [0]. [0] : https://www.arm.com/products/cortex-x gas/ChangeLog: 2020-10-05 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * config/tc-arm.c: Update Cortex-X1 feature flags.
2020-10-05Add NetBSD AArch64 GAS support.Kamil Rytarowski2-0/+5
gas * configure.tgt (aarch64*-*-netbsd*): Add target.
2020-10-05Fix spelling mistakesSamanta Navarro3-2/+7
2020-10-05i386: Allow non-absolute segment values for lcall/ljmpT.K. Chia8-6/+67
Allow an unresolved or non-absolute symbol as the segment operand of an immediate far jump (`ljmp SEG, OFF') or far call (`lcall SEG, OFF'). gas/ 2020-10-05 T.K. Chia <u1049321969@caramail.com> PR gas/26694 * NEWS: Updated for i386 lcall and ljmp change. * config/tc-i386.c (output_interseg_jump): Allow non-absolute segment operand for immediate lcall and ljmp. * testsuite/gas/i386/jump.d, * testsuite/gas/i386/jump.s, * testsuite/gas/i386/jump16.d, * testsuite/gas/i386/jump16.e, * testsuite/gas/i386/jump16.s: Add tests for non-absolute segment operand for immediate ljmp. ld/ 2020-10-05 T.K. Chia <u1049321969@caramail.com> PR gas/26694 * testsuite/ld-i386/ljmp.s, * testsuite/ld-i386/ljmp1.d, * testsuite/ld-i386/ljmp1.s, * testsuite/ld-i386/ljmp2.d, * testsuite/ld-i386/ljmp2.s, * testsuite/ld-x86-64/ljmp1.d, * testsuite/ld-x86-64/ljmp2.d: New testcases. * testsuite/ld-i386/i386.exp, * testsuite/ld-x86-64/x86-64.exp: Run them.
2020-10-05x86-64: Always display suffix for %LQ in 64bitH.J. Lu5-4/+13
In 64bit, assembler generates a warning for "sysret": $ echo sysret | as --64 -o x.o - {standard input}: Assembler messages: {standard input}:1: Warning: no instruction mnemonic suffix given and no register operands; using default for `sysret' Always display suffix for %LQ in 64bit to display "sysretl". gas/ PR binutils/26704 * testsuite/gas/i386/noreg64-data16.d: Expect sysretl instead of sysret. * testsuite/gas/i386/noreg64.d: Likewise. * testsuite/gas/i386/x86-64-intel64.d: Likewise. * testsuite/gas/i386/x86-64-opcode.d: Likewise. opcodes/ PR binutils/26704 * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
2020-10-05x86: Clear modrm if not neededH.J. Lu4-0/+14
The MODRM byte can be checked to display the instruction name only if the MODRM byte needed. Clear modrm if the MODRM byte isn't needed so that modrm field checks in putop like, modrm.mod == N with N != 0, can be done without checking need_modrm. gas/ PR binutils/26705 * testsuite/gas/i386/x86-64-suffix.s: Add "mov %rsp,%rbp" before sysretq. * testsuite/gas/i386/x86-64-suffix-intel.d: Updated. * testsuite/gas/i386/x86-64-suffix.d: Likewise. opcodes/ PR binutils/26705 * i386-dis.c (print_insn): Clear modrm if not needed. (putop): Check need_modrm for modrm.mod != 3. Don't check need_modrm for modrm.mod == 3.
2020-10-05GAS: Update the .section directive so that a numeric section index can be ↵Nick Clifton9-33/+86
provided when the "o" flag is used. PR 26253 gas * config/obj-elf.c (obj_elf_section): Accept a numeric value for the "o" section flag. Interpret it as a section index. Allow an index of zero. * doc/as.texi: Document the new behaviour. * NEWS: Mention the new feature. Tidy entries. * testsuite/gas/elf/sh-link-zero.s: New test. * testsuite/gas/elf/sh-link-zero.d: New test driver. * testsuite/gas/elf/elf.exp: Run the new test. * testsuite/gas/elf/section21.l: Updated expected assembler output. bfd * elf.c (_bfd_elf_setup_sections): Do not complain about an sh_link value of zero when the SLF_LINK_ORDER flag is set. (assign_section_numbers): Likewise.
2020-10-03x86: Update register operand check for AddrPrefixOpRegH.J. Lu19-60/+196
When the address size prefix applies to both the memory and the register operand, we need to extract the address size prefix from the register operand if the memory operand has no real registers, like symbol, DISP or symbol(%rip). NB: GCC always generates symbol(%rip) for RIP-relative addressing for both x32 and x86-64. Move the .code16 tests in movdir.s to movdir-16bit to show the correct output from objdump. PR gas/26685 * config/tc-i386.c (process_suffix): Also check the register operand for the address size prefix if the memory operand has no real registers. * testsuite/gas/i386/enqcmd-16bit.d: New file. * testsuite/gas/i386/enqcmd-16bit.s: Likewise. * testsuite/gas/i386/movdir-16bit.d: Likewise. * testsuite/gas/i386/movdir-16bit.s: Likewise. * testsuite/gas/i386/enqcmd.s: Add tests with symbol and DISP. * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. * testsuite/gas/i386/x86-64-movdir.s: Likewise. * testsuite/gas/i386/movdir.s: Add tests with symbol and DISP. Remove the .code16 test. * testsuite/gas/i386/i386.exp: Run movdir-16bit and enqcmd-16bit. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise. * testsuite/gas/i386/enqcmd-intel.d: Likewise. * testsuite/gas/i386/enqcmd.d: Likewise. * testsuite/gas/i386/movdir-intel.d: Likewise. * testsuite/gas/i386/movdir.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise.
2020-10-02arm: add support for Cortex-A78 and Cortex-A78AEPrzemyslaw Wirkus5-0/+22
bfd/ChangeLog: 2020-09-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * cpu-arm.c: Add cortex-a78 and cortex-a78ae. gas/ChangeLog: 2020-09-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * config/tc-arm.c: Add cortex-a78 and cortex-a78ae cores. * doc/c-arm.texi: Update docs. * NEWS: Update news. * testsuite/gas/arm/cpu-cortex-a78.d: New test. * testsuite/gas/arm/cpu-cortex-a78ae.d: New test.
2020-10-02Fix the mve-vcvtne-it assembler test for the arm-*-pe targets.Nick Clifton2-1/+7
* testsuite/gas/arm/mve-vcvtne-it.d: Allow for padding inserted by PE based targets.
2020-10-01Add new directive to GAS: .attach_to_group.Nick Clifton11-1/+108
* config/obj-elf (elf_pseudo_table): Add attach_to_group. (obj_elf_attach_to_group): New function. * doc/as.texi: Document the new directive. * NEWS: Mention the new feature. * testsuite/gas/elf/attach-1.s: New test. * testsuite/gas/elf/attach-1.d: New test driver. * testsuite/gas/elf/attach-2.s: New test. * testsuite/gas/elf/attach-2.d: New test driver. * testsuite/gas/elf/attach-err.s: New test. * testsuite/gas/elf/attach-err.d: New test driver. * testsuite/gas/elf/attach-err.err: New test error output. * testsuite/gas/elf/elf.exp: Run the new tests.
2020-09-30x86: Check register operand for AddrPrefixOpRegH.J. Lu8-34/+114
If the address prefix changes the register operand, we need to check the register operand when the memory operand is RIP-relative. PR gas/26685 * config/tc-i386.c (process_suffix): Check the register operand for the address size prefix if the memory operand is symbol(%rip). * testsuite/gas/i386/x86-64-enqcmd.s: Add tests with RIP-relative addressing. * testsuite/gas/i386/x86-64-movdir.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise.
2020-09-30[GAS][AArch64] Add support for Cortex-A78 and Cortex-A78AEPrzemyslaw Wirkus4-0/+24
* config/tc-aarch64.c: Add Cortex-A78 and Cortex-A78AE cores. * doc/c-aarch64.texi: Update docs. * NEWS: Update news.
2020-09-30NEWS: Mention recent Arm CPU supportAlex Coplan2-0/+9
Mentions Armv8-R AArch64, Cortex-R82, Neoverse V1, and Neoverse N2. gas/ChangeLog: 2020-09-30 Alex Coplan <alex.coplan@arm.com> * NEWS: Mention recent Arm processor support.
2020-09-30aarch64: Add support for Neoverse N2 CPUAlex Coplan3-0/+16
This patch adds support for Arm's Neoverse N2 CPU to AArch64 binutils. gas/ChangeLog: * config/tc-aarch64.c (aarch64_cpus): Add neoverse-n2. * doc/c-aarch64.texi: Document support for Neoverse N2.
2020-09-30gcc-4.4.7 warning fixesAlan Modra3-3/+10
* config/obj-elf.c (obj_elf_change_section): Rename variable to avoid shadowing warning. * symbols.c (symbol_entry_find): Init all symbol_flags fields.
2020-09-29Add a note about recent changes to the AArch64 assembler: TRBE, ETE and ↵Przemyslaw Wirkus2-0/+15
ETMv4 system registers and Cortex-X1 enablement. gas * NEWS: TRBE, ETE, ETMv4 and Cortex-X1 news updates.
2020-09-28This patch adds support for Cortex-X1 for ARM.Przemyslaw Wirkus4-0/+16
bfd * cpu-arm.c: (processors) Add Cortex-X1. gas * config/tc-arm.c: (arm_cpus): Add Cortex-X1. * doc/c-arm.texi: Document -mcpu=cortex-x1. * testsuite/gas/arm/cpu-cortex-x1.d: New test.
2020-09-28This patch introduces ETMv4 (Embedded Trace Macrocell) system registers for ↵Przemyslaw Wirkus14-9/+933
the AArch64 architecture. gas * testsuite/gas/aarch64/etm-ro-invalid.d: New test. * testsuite/gas/aarch64/etm-ro-invalid.l: New test. * testsuite/gas/aarch64/etm-ro-invalid.s: New test. * testsuite/gas/aarch64/etm-ro.s: New test. * testsuite/gas/aarch64/etm-wo-invalid.d: New test. * testsuite/gas/aarch64/etm-wo-invalid.l: New test. * testsuite/gas/aarch64/etm-wo-invalid.s: New test. * testsuite/gas/aarch64/etm-wo.s: New test. * testsuite/gas/aarch64/etm.s: New test. * testsuite/gas/aarch64/sysreg.d: system register s2_1_c0_c3_0 disassembled now to trcstatr. opcodes * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn, TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1, TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET, TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1, TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R, TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4, TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12, TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3, TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn, TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn, TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR, TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR, TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
2020-09-28This patch adds support for Cortex-X1Przemyslaw Wirkus3-1/+10
gas * config/tc-aarch64.c: (aarch64_cpus): Add Cortex-X1. * doc/c-aarch64.texi: Document -mcpu=cortex-x1.
2020-09-28This patch introduces ETE (Embedded Trace Extension) system registers for ↵Przemyslaw Wirkus3-0/+38
the AArch64 architecture. gas * testsuite/gas/aarch64/ete.d: New test. * testsuite/gas/aarch64/ete.s: New test. opcodes * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
2020-09-28This patch introduces TRBE (Trace Buffer Extension) system registers for the ↵Przemyslaw Wirkus6-0/+52
AArch64 architecture. gas * testsuite/gas/aarch64/trbe-invalid.d: New test. * testsuite/gas/aarch64/trbe-invalid.l: New test. * testsuite/gas/aarch64/trbe-invalid.s: New test. * testsuite/gas/aarch64/trbe.d: New test. * testsuite/gas/aarch64/trbe.s: New test. opcodes * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 , TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
2020-09-28arm: Add missing Neoverse V1 featureAlex Coplan2-1/+7
This simple follow-on patch adds a feature bit (FP16) that was missing from the initial Neoverse V1 support. gas/ChangeLog: * config/tc-arm.c (arm_cpus): Add FP16 to Neoverse V1.
2020-09-28aarch64: Neoverse V1 tweaksAlex Coplan2-8/+14
This simple follow-on patch groups the Neoverse cores together and adds a missing feature bit (F16) to the entry for Neoverse V1. gas/ChangeLog: * config/tc-aarch64.c (aarch64_cpus): Group Neoverse cores together, add missing F16 bit to Neoverse V1.
2020-09-26ubsan: opcodes/csky-opc.h:929 shift exponent 536870912Alan Modra2-48/+51
opcodes/ * csky-opc.h: Formatting. (GENERAL_REG_BANK): Correct spelling. Update use throughout file. (get_register_name): Mask arch with CSKY_ARCH_MASK for shift, and shift 1u. (get_register_number): Likewise. * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag. gas/ * config/tc-csky.c (parse_type_ctrlreg): Don't mask mach_flag for csky_get_control_regno. (csky_get_reg_val): Likewise when calling csky_get_general_regno.
2020-09-24RISC-V: Error for relaxable branch in absolute section.Jim Wilson5-0/+23
Emit an error instead of crashing in frag_new, handling this same as the i386 port. gas/ PR 26400 * config/tc-riscv.c (append_insn): If in absolute section, emit error before add_relaxed_insn call. * testsuite/gas/riscv/absolute-sec.d: New. * testsuite/gas/riscv/absolute-sec.l: New. * testsuite/gas/riscv/absolute-sec.s: New.
2020-09-24readelf: Show Unit Type for DWARF5Mark Wielaard2-0/+5
binutils/ChangeLog: * dwarf.c (process_debug_info): Print Unit Type for DWARF5. * testsuite/binutils-all/dw5.W: Adjust expected output. * testsuite/binutils-all/dwarf-attributes.W: Likewise. gas/ChangeLog: * testsuite/gas/elf/dwarf-5-cu.d: Adjust expected output.
2020-09-24arm: Add support for Neoverse V1 CPUAlex Coplan3-0/+9
This patch adds support for Arm's Neoverse V1 CPU to AArch32 binutils. gas/ChangeLog: 2020-09-24 Alex Coplan <alex.coplan@arm.com> * config/tc-arm.c (arm_cpus): Add Neoverse V1. * doc/c-arm.texi: Document Neoverse V1 support.
2020-09-24aarch64: Add support for Neoverse V1 CPUAlex Coplan3-0/+14
This adds support for Arm's Neoverse V1 CPU to AArch64 binutils. gas/ChangeLog: 2020-09-24 Alex Coplan <alex.coplan@arm.com> * config/tc-aarch64.c (aarch64_cpu_option_table): Add Neoverse V1. * doc/c-aarch64.texi: Document Neoverse V1 support.
2020-09-24arm: Add support for Neoverse N2 CPUAlex Coplan3-0/+11
This adds support for Arm's Neoverse N2 CPU to AArch32 binutils. The Neoverse N2 CPU builds AArch32 at EL0 and therefore needs support in the AArch32 assembler. gas/ChangeLog: 2020-09-24 Alex Coplan <alex.coplan@arm.com> * config/tc-arm.c (arm_cpus): Add Neoverse N2. * doc/c-arm.texi: Document -mcpu=neoverse-n2.
2020-09-24Add support for Intel TDX instructions.Cui,Lili9-1/+62
gas/ * NEWS: Add TDX. * config/tc-i386.c (cpu_arch): Add .tdx. (cpu_noarch): Likewise. * doc/c-i386.texi: Document tdx. * testsuite/gas/i386/i386.exp: Run tdx tests. * testsuite/gas/i386/tdx.d: Likewise. * testsuite/gas/i386/tdx.s: Likewise. * testsuite/gas/i386/x86-64-tdx.d: Likewise. * testsuite/gas/i386/x86-64-tdx.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5, PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7, X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2, X86_64_0F01_REG_1_RM_7_P_2. (prefix_table): Likewise. (x86_64_table): Likewise. (rm_table): Likewise. * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS and CPU_ANY_TDX_FLAGS. (cpu_flags): Add CpuTDX. * i386-opc.h (enum): Add CpuTDX. (i386_cpu_flags): Add cputdx. * i386-opc.tbl: Add TDX insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-09-23CSKY: Add objdump option -M abi-names.Cooper Qu7-416/+327
Add option parser for disassembler, and refine the codes of parse register operand and disassemble register operand. While strengthen the operands legality check of some instructions. Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com> gas/ * config/tc-csky.c (parse_type_ctrlreg): Use function csky_get_control_regno to operand. (csky_get_reg_val): Likewise. (is_reg_sp_with_bracket): Use function csky_get_reg_val to parse operand. (is_reg_sp): Refine. (is_oimm_within_range): Fix, report error when operand is not constant. (parse_type_cpreg): Refine. (parse_type_cpcreg): Refine. (get_operand_value): Add handle of OPRND_TYPE_IMM5b_LS. (md_assemble): Fix no error reporting somtimes when operands number are not fit. (csky_addc64): Refine. (csky_subc64): Refine. (csky_or64): Refine. (v1_work_fpu_fo): Refine. (v1_work_fpu_read): Refine. (v1_work_fpu_writed): Refine. (v1_work_fpu_readd): Refine. (v2_work_addc): New function, strengthen the operands legality check of addc. * gas/testsuite/gas/csky/all.d : Use register number format when disassemble register name by default. * gas/testsuite/gas/csky/cskyv2_all.d : Likewise. * gas/testsuite/gas/csky/trust.d: Likewise. * gas/testsuite/gas/csky/cskyv2_ck860.d : Fix. * gas/testsuite/gas/csky/trust.s : Fix. opcodes/ * csky-dis.c (using_abi): New. (parse_csky_dis_options): New function. (get_gr_name): New function. (get_cr_name): New function. (csky_output_operand): Use get_gr_name and get_cr_name to disassemble and add handle of OPRND_TYPE_IMM5b_LS. (print_insn_csky): Parse disassembler options. * opcodes/csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum. (GENARAL_REG_BANK): Define. (REG_SUPPORT_ALL): Define. (REG_SUPPORT_ALL): New. (ASH): Define. (REG_SUPPORT_A): Define. (REG_SUPPORT_B): Define. (REG_SUPPORT_C): Define. (REG_SUPPORT_D): Define. (REG_SUPPORT_E): Define. (csky_abiv1_general_regs): New. (csky_abiv1_control_regs): New. (csky_abiv2_general_regs): New. (csky_abiv2_control_regs): New. (get_register_name): New function. (get_register_number): New function. (csky_get_general_reg_name): New function. (csky_get_general_regno): New function. (csky_get_control_reg_name): New function. (csky_get_control_regno): New function. (csky_v2_opcodes): Prefer two oprerans format for bclri and bseti, strengthen the operands legality check of addc, zext and sext.
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo14-1/+263
gas/ * NEWS: Add Key Locker. * config/tc-i386.c (cpu_arch): Add .kl and .wide_kl. (cpu_noarch): Likewise. * doc/c-i386.texi: Document kl and wide_kl. * testsuite/gas/i386/i386.exp: Run keylocker tests. * testsuite/gas/i386/keylocker-intel.d: New test. * testsuite/gas/i386/keylocker.d: Likewise. * testsuite/gas/i386/keylocker.s: Likewise. * testsuite/gas/i386/x86-64-keylocker-intel.d: Likewise. * testsuite/gas/i386/x86-64-keylocker.d: Likewise. * testsuite/gas/i386/x86-64-keylocker.s: Likewise. * testsuite/gas/i386/x86-64-property-10.d: Likewise. * testsuite/gas/i386/property-10.d: Likewise. * testsuite/gas/i386/property-10.s: Likewise. opcodes/ * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1, MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1, MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1, MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1, PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB. (reg_table): New instructions (see prefixes above). (prefix_table): Likewise. (three_byte_table): Likewise. (mod_table): Likewise * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS, CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS. (cpu_flags): Likewise. (operand_type_init): Likewise. * i386-opc.h (enum): Add CpuKL and CpuWide_KL. (i386_cpu_flags): Add cpukl and cpuwide_kl. * i386-opc.tbl: Add KL and WIDE_KL insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
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