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2022-07-09gas: target string hash tablesAlan Modra9-81/+45
This allocates entries added to the string hash tables on the notes obstack, so that at least those do not leak. A followup patch will switch over the str_hash allocation to notes_calloc, which is why I haven't implemented deleting all the target string hash tables. * config/obj-coff-seh.c (get_pxdata_name, alloc_pxdata_item): Use notes obstack for string hash table entries. * config/tc-alpha.c (get_alpha_reloc_tag, md_begin): Likewise. * config/tc-h8300.c (md_begin): Likewise. * config/tc-ia64.c (dot_rot, dot_pred_rel, dot_alias): Likewise. * config/tc-nds32.c (nds32_relax_hint): Likewise. * config/tc-riscv.c (riscv_init_csr_hash): Likewise. * config/tc-score.c (s3_insert_reg): Likewise. (s3_build_score_ops_hsh, s3_build_dependency_insn_hsh): Likewise. * config/tc-score7.c (s7_build_score_ops_hsh): Likewise. (s7_build_dependency_insn_hsh): Likewise. * config/tc-tic4x.c (tic4x_asg): Likewise.
2022-07-09arc gas: don't leak arc_opcode_hash memoryAlan Modra2-1/+23
The arc opcode hash table has entries that have a realloc'd field. This doesn't lend itself to obstack allocation, so freeing must be done with a purpose built hashtab del_f. * config/tc-arc.c (arc_opcode_free): New function. (md_begin): Pass the above as del_f to htab_create_alloc. (arc_md_end): New function. * config/tc-arc.h (arc_md_end): Declare. (md_end): Define.
2022-07-09i386 gas: don't leak op_hash or reg_hash memoryAlan Modra3-3/+13
This tidies memory used by the two x86 gas string hash tables before exiting. I'm using a two-pronged approach, firstly the obvious call to htab_delete plus telling the libiberty/hashtab.c infrastructure to free tuples generated by str_hash_insert, and secondly putting the x86 core_optab memory on the notes obstack. It would be possible to free core_optab memory by using a custom hash table del_f on x86, as I do for arc, but a later patch will move all the string hash memory to the notes obstack. * config/tc-i386.c (md_begin): Use notes_alloc for core_optab. (386_md_end): New function. * config/tc-i386.h (386_md_end): Declare. (md_end): Define. * hash.h (str_htab_create): Pass free as del_f.
2022-07-09ppc gas: don't leak ppc_hash memoryAlan Modra2-2/+37
* config/tc-ppc.c (insn_obstack): New. (insn_calloc): New function. (ppc_setup_opcodes): Use insn_obstack for ppc_hash. (ppc_md_end): New function. * config/tc-ppc.h (ppc_md_end): Declare (md_end): Define.
2022-07-09gas hash.h tidyAlan Modra2-30/+38
Only inline functions should be defined in hash.h, there's no benefit in having multiple copies of hash_string_tuple and eq_string_tuple. Also, use the table alloc_f when allocating tuples to be stored, so that these functions are usable with different memory allocation strategies. * hash.h (struct string_tuple, string_tuple_t): Move earlier. (string_tuple_alloc): Add table param, allocate using table alloc_f. (str_hash_insert): Adjust to suit. Call table->free_f when entry is not used. (hash_string_tuple, eq_string_tuple): Move to.. * hash.c: ..here.
2022-07-09gas: rename md_end to md_finishAlan Modra42-80/+84
Currently md_end is typically used for some final actions rather than freeing memory like other *_end functions. Rename it to md_finish, and rename target implementation. The renaming of target functions makes it possible to find them all with "grep md_finish", eg. md_mips_end is renamed to mips_md_finish, not md_mips_finish. This patch leaves a number of md_end functions unchanged, those that either do nothing or deallocate memory, and calls them late. The idea here is that target maintainers implement md_end functions to tidy memory, if anyone cares. Freeing persistent memory in gas is not at all important, except that it can hide more important memory leaks, those that happen once per some frequent gas operation, amongst these unimportant memory leaks. * as.c (main): Rename md_end to md_finish. * config/tc-alpha.c, * config/tc-alpha.h, * config/tc-arc.c, * config/tc-arc.h, * config/tc-arm.c, * config/tc-arm.h, * config/tc-csky.c, * config/tc-csky.h, * config/tc-ia64.c, * config/tc-ia64.h, * config/tc-mcore.c, * config/tc-mcore.h, * config/tc-mips.c, * config/tc-mips.h, * config/tc-mmix.c, * config/tc-mmix.h, * config/tc-msp430.c, * config/tc-msp430.h, * config/tc-nds32.c, * config/tc-nds32.h, * config/tc-ppc.c, * config/tc-ppc.h, * config/tc-pru.c, * config/tc-pru.h, * config/tc-riscv.c, * config/tc-riscv.h, * config/tc-s390.c, * config/tc-s390.h, * config/tc-sparc.c, * config/tc-sparc.h, * config/tc-tic4x.c, * config/tc-tic4x.h, * config/tc-tic6x.c, * config/tc-tic6x.h, * config/tc-v850.c, * config/tc-v850.h, * config/tc-xtensa.c, * config/tc-xtensa.h, * config/tc-z80.c, * config/tc-z80.h: Similarly. * output-file.c (output_file_close): Call md_end.
2022-07-09gas: set up notes obstack earlierAlan Modra3-11/+15
So that the notes obstack can be used for persistent storage in parse_args. * as.c (parse_args): Use notes_alloc and notes_strdup. (free_notes): New function. (main): Init notes obstack, and arrange to be freed on exit. * read.c (read_begin): Don't init notes obstack. (read_end): Free cond_obstack. * subsegs.c (subsegs_end): Don't free cond_obstack or notes.
2022-07-09gas: itbl_filesAlan Modra1-20/+2
itbl_files seems to be debug code. Get rid of it. * as.c (struct itbl_file_list): Delete. (itbl_files): Delete. (parse_args): Don't keep itbl_files list.
2022-07-09gas: free sy_hash, macro_hash and po_hashAlan Modra7-0/+33
* macro.c (macro_end): New function. * macro.h (macro_end): Declare. * read.c (read_end, poend): New functions. * read.h (read_end): Declare. * symbols.c (symbol_end): New function. * symbols.h (symbol_end): Declare. * output-file.c (output_file_close): Call new *_end functions.
2022-07-09dw2gencfi.c: use notes obstackAlan Modra1-12/+10
Use notes obstack for dwcfi_hash entries, and free table. Freeing the table makes memory checkers complain more about "definitely lost" memory as we've moved some from the "still reachable" category. That will be fixed with a later patch. * dw2gencfi.c (get_debugseg_name): Allocate on notes obstack. (alloc_debugseg_item): Likewise. (dwcfi_hash_find_or_make): Adjust failure path free. (cfi_finish): Delete dwfci_hash.
2022-07-09expr.c make_expr_symbol: use notes obstackAlan Modra1-1/+1
* expr.c (make_expr_symbol): Use notes_alloc.
2022-07-09read.c assign_symbol: use notes obstack for dummy listing fragAlan Modra1-1/+1
* read.c (assign_symbol): Use notes_calloc for dummy_frag.
2022-07-09read.c s_include: use notes obstack for pathAlan Modra1-4/+2
* read.c (s_include): Use notes obstack for path mem.
2022-07-09macro.c: use string hash from hash.h for macro_hashAlan Modra3-144/+29
Another case of duplicated hash.h code, the only minor difference being that macro->format_hash was created with 7 entries vs. str_hash with 16 entries. * macro.c (macro_init, define_macro): Use str_htab_create. (do_formals, define_macro, macro_expand_body): Use str_hash_insert (macro_expand_body): Use str_hash_find and str_hash_delete. (delete_macro): Likewise. (sub_actual, macro_expand, check_macro): Use str_hash_find. (expand_irp): Use str_htab_create and str_hash_insert. * macro.h (struct macro_struct): Tidy. (struct macro_hash_entry, macro_hash_entry_t, hash_macro_entry), (eq_macro_entry, macro_entry_alloc, macro_entry_find), (struct formal_hash_entry, formal_hash_entry_t), (hash_formal_entry, eq_formal_entry, formal_entry_alloc), (formal_entry_find): Delete. * config/tc-iq2000.c (iq2000_add_macro): Use str_htab_create and str_hash_insert.
2022-07-09read.c: use string hash from hash.h for po_hashAlan Modra1-56/+7
po_hash code duplicates the str_hash code in hash.h for no good reason. * read.c (struct po_entry, po_entry_t): Delete. (hash_po_entry, eq_po_entry, po_entry_alloc, po_entry_find): Delete. (pop_insert): Use str_hash_insert. (pobegin): Use str_htab_create. (read_a_source_file, s_macro): Use str_hash_find.
2022-07-09free read_symbol_name stringAlan Modra2-0/+5
read_symbol_name mallocs the string it returns. Free it when done. * read.c (read_symbol_name): Free name on error path. * config/tc-ppc.c (ppc_GNU_visibility): Free name returned from read_symbol_name. (ppc_extern, ppc_globl, ppc_weak): Likewise.
2022-07-09gas: output_file_closeAlan Modra4-15/+13
This is mostly a tidy with the aim of being able to free out_file_name, but it does fix a possible attempt to unlink the output file twice (not that that matters). * as.h (keep_it): New global. * as.c (keep_it): Delete. (close_output_file): Delete, merged into.. * output-file.c (output_file_close): ..here. Delete parameter. * output-file.h (output_file_close): Update prototype.
2022-07-09gas: utility notes memory alloc functionsAlan Modra3-10/+90
Makes it a little easier to use the notes obstack for persistent storage. * as.h (gas_mul_overflow): Define. * symbols.h (notes_alloc, notes_calloc, notes_memdup), (notes_strdup, notes_concat, notes_free): Declare. * symbols.c (notes_alloc, notes_calloc, notes_memdup), (notes_strdup, notes_concat, notes_free): New functions. (save_symbol_name): Use notes_strdup. (symbol_create, local_symbol_make, local_symbol_convert), (symbol_clone, decode_local_label_name): Use notes_alloc.
2022-07-09gas: arm -mwarn-syms duplicatesAlan Modra2-5/+3
arm gas is only supposed to warn once per symbol for -mwarn-syms, but doesn't because the str_hash_find added with commit 629310abec88 always returns NULL. That's so because the str_hash_insert inserts a NULL value for the key,value pair. Let str_hash_insert do the job instead. * config/tc-arm.c (arm_tc_equal_in_insn): Correct already_warned logic. * testsuite/gas/arm/pr18347.s: Modify to generate duplicate warning without this patch.
2022-07-09Regenerate with automake-1.15.1Alan Modra3-733/+379
Until we update the recommended versions of autoconf/automake, files should be regenerated with automake-1.15.1 and autoconf-2.69. That's not because we think those versions are golden, and newer versions are bad. It's simply because maintainers want to be able to update configury files without trouble, and if someone regenerates files with automake-1.16.5 then --enable-maintainer-mode builds will hit errors: checking that generated files are newer than configure... configure.ac:26: error: version mismatch. This is Automake 1.15.1, configure.ac:26: but the definition used by this AM_INIT_AUTOMAKE configure.ac:26: comes from Automake 1.16.5. You should recreate configure.ac:26: aclocal.m4 with aclocal and run automake again. WARNING: 'automake-1.15' is probably too old. Correcting this requires regenerating the files by hand.
2022-07-08Update version to 2.39.50 and regenerate filesNick Clifton4-2371/+2751
2022-07-08Add markers for 2.39 branchNick Clifton2-0/+6
2022-07-07RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI13-32/+64
This commit adds Zfhmin and Zhinxmin extensions (subsets of Zfh and Zhinx extensions, respectively). In the process supporting Zfhmin and Zhinxmin extension, this commit also changes how instructions are categorized considering Zfhmin, Zhinx and Zhinxmin extensions. Detailed changes, * From INSN_CLASS_ZFH to INSN_CLASS_ZFHMIN: flh, fsh, fmv.x.h and fmv.h.x. * From INSN_CLASS_ZFH to INSN_CLASS_ZFH_OR_ZHINX: fmv.h. * From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFH_OR_ZHINX: fneg.h, fabs.h, fsgnj.h, fsgnjn.h, fsgnjx.h, fadd.h, fsub.h, fmul.h, fdiv.h, fsqrt.h, fmin.h, fmax.h, fmadd.h, fnmadd.h, fmsub.h, fnmsub.h, fcvt.w.h, fcvt.wu.h, fcvt.h.w, fcvt.h.wu, fcvt.l.h, fcvt.lu.h, fcvt.h.l, fcvt.h.lu, feq.h, flt.h, fle.h, fgt.h, fge.h, fclass.h. * From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFHMIN_OR_ZHINXMIN: fcvt.s.h and fcvt.h.s. * From INSN_CLASS_D_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_D: fcvt.d.h and fcvt.h.d. * From INSN_CLASS_Q_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_Q: fcvt.q.h and fcvt.h.q. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Change implicit subsets. Zfh->Zicsr is not needed and Zfh->F is replaced with Zfh->Zfhmin and Zfhmin->F. Zhinx->Zicsr is not needed and Zhinx->Zfinx is replaced with Zhinx->Zhinxmin and Zhinxmin->Zfinx. (riscv_supported_std_z_ext): Added zfhmin and zhinxmin. (riscv_multi_subset_supports): Rewrite handling for new instruction classes. (riscv_multi_subset_supports_ext): Updated. (riscv_parse_check_conflicts): Change error message to include zfh and zfhmin extensions. gas/ChangeLog: * testsuite/gas/riscv/zfhmin-d-insn-class-fail.s: New complex error handling test. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l: Likewise. * testsuite/gas/riscv/zhinx.d: Renamed from fp-zhinx-insns.d and refactored. * testsuite/gas/riscv/zhinx.s: Likewise. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Removed INSN_CLASS_ZFH, INSN_CLASS_D_AND_ZFH_INX and INSN_CLASS_Q_AND_ZFH_INX. Added INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, INSN_CLASS_ZFHMIN_AND_D and INSN_CLASS_ZFHMIN_AND_Q. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Change instruction classes for Zfh and Zfhmin instructions. Fix `fcvt.h.lu' instruction (two operand variant) mask.
2022-07-07RISC-V: Fix disassembling Zfinx with -M numericTsukasa OI2-0/+12
This commit fixes floating point operand register names from ABI ones to dynamically set ones. gas/ChangeLog: * testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of Zfinx extension and -M numeric disassembler option. * testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR names to disassemble Zfinx instructions.
2022-07-07RISC-V: Fix requirement handling on Zhinx+{D,Q}Tsukasa OI1-1/+1
This commit fixes how instructions are masked on Zhinx+Z{d,q}inx. fcvt.h.d and fcvt.d.h require ((D&&Zfh)||(Zdinx&&Zhinx)) and fcvt.h.q and fcvt.q.h require ((Q&&Zfh)||(Zqinx&&Zhinx)). bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Fix feature gate on INSN_CLASS_{D,Q}_AND_ZFH_INX. (riscv_multi_subset_supports_ext): Fix feature gate diagnostics on INSN_CLASS_{D,Q}_AND_ZFH_INX. gas/ChangeLog: * testsuite/gas/riscv/fp-zhinx-insns.d: Add Zqinx to -march for proper testing.
2022-07-07PR29320, 'struct obstack' declared inside parameter listAlan Modra2-2/+2
PR 29320 * frags.h: Move declaration of struct obstack.. * as.h: ..to here.
2022-07-06x86: make D attribute usable for XOP and FMA4 insnsJan Beulich1-7/+35
This once again allows to reduce redundancy in (and size of) the opcode table. Don't go as far as also making D work on the two 5-operand XOP insns: This would significantly complicate the code, as there the first (immediate) operand would need special treatment in several places. Note that the .s suffix isn't being enabled to have any effect, for being deprecated. Whereas neither {load} nor {store} pseudo prefixes make sense here, as the respective operands are inputs (loads) only anyway, regardless of order. Hence there is (as before) no way for the programmer to request the alternative encoding to be used for register- only insns. Note further that it is always the first original template which is retained (and altered), to make sure the same encoding as before is used for register-only insns. This has the slightly odd (but pre- existing) effect of XOP register-only insns having XOP.W clear, but FMA4 ones having VEX.W set.
2022-07-06x86: fold two switch() statements in match_template()Jan Beulich1-16/+3
I don't see why two of them were introduced (very long ago) using similar fall-through logic.
2022-07-06x86: fix 3-operand insn reverse-matchingJan Beulich3-18/+19
The middle operand would have gone entirely unchecked, allowing e.g. vmovss %xmm0, %esp, %xmm2 to assemble successfully, or e.g. vmovss %xmm0, $4, %xmm2 causing an internal error. Alongside dealing with this also drop a related comment, which hasn't been applicable anymore since the introduction of 3-operand patterns with D set (and which perhaps never had been logical to be there, as reverse-matched insns don't make it there in the first place).
2022-07-06x86: introduce a state stack for .archJan Beulich5-2/+159
When using just slightly non-trivial combinations of .arch, it can be quite useful to be able to go back to prior state without needing to re-invoke perhaps many earlier directives and without needing to invoke perhaps many "negative" ones. Like some other architectures allow saving (pushing) and restoring (popping) present/prior state. For now require the same .code<N> to be in effect for ".arch pop" that was in effect for the corresponding ".arch push". Also change the global "no_cond_jump_promotion" to be bool, to match the new struct field.
2022-07-06x86: generalize disabling of sub-architecturesJan Beulich1-235/+179
I never really understood upon what basis ".arch .no*" options were made available. Let's not have any "criteria" at all, and simply allow disabling of all of them. Then we also have all data for a sub-arch in a single place, as we now only need a single table.
2022-07-06x86: permit "default" with .archJan Beulich5-8/+85
So far there was no way to reset the architecture to that assembly would start with in the absence of any overrides (command line or directives). Note that for Intel MCU "default" is merely an alias of "iamcu". While there also zap a stray @item from the doc section, as noticed when inspecting the generated output (which still has some quirks, but those aren't easy to address without re-flowing almost the entire section).
2022-07-06x86: don't leak sub-architecture accumulated stringsJan Beulich1-0/+3
While it may not be necessary in i386_target_format() (but then setting the variable to NULL also wouldn't be necessary), at least in the other cases strings may already have accumulated.
2022-07-05x86: introduce fake processor type to mark sub-arch entries in cpu_arch[]Jan Beulich2-4/+10
This is in preparation of dropping the leading . from the strings. While there also move PROCESSOR_GENERIC{32,64} from the middle of AMD entries to near the top.
2022-07-05x86: macro-ize cpu_arch[] entriesJan Beulich1-308/+164
Putting individual elements behind macros, besides (imo) improving readability, will make subsequent (and likely also future) changes less intrusive. Utilize this right away to pack the table a little more tightly, by converting "skip" to bool and putting it earlier in a group of bitfields together with "len".
2022-07-05x86: de-duplicate sub-architecture strings accumulationJan Beulich1-38/+14
Introduce a helper function to replace 4 instances of similar code. Use reconcat() to cover the previously explicit free().
2022-07-04alloc gas seginfo on notes obstackAlan Modra3-18/+62
Lots of memory used in gas should go on this obstack. The patch also frees all the gas obstacks on exit, which isn't a completely trivial task. * subsegs.c (alloc_seginfo): New function. (subseg_change, subseg_get): Use it. (subsegs_end): New function. * as.h (subsegs_end): Declare. * output-file.c: Include subsegs.h (stash_frchain_obs): New function. (output_file_close): Save obstacks attached to output bfd before closing. Call subsegs_end with the array of obstacks.
2022-07-04gas/testsuite: properly exclude aout in all/weakref1uJan Beulich1-1/+1
Use the (wider) predicate rather than a triplet. This eliminates the sole i386-msdos failure in the testsuite.
2022-07-04x86: fold Disp32S and Disp32Jan Beulich2-75/+42
The only case where 64-bit code uses non-sign-extended (can also be considered zero-extended) displacements is when an address size override is in place for a memory operand (i.e. particularly excluding displacements of direct branches, which - if at all - are controlled by operand size, and then are still sign-extended, just from 16 bits). Hence the distinction in templates is unnecessary, allowing code to be simplified in a number of places. The only place where logic becomes more complicated is when signed-ness of relocations is determined in output_disp(). The other caveat is that Disp64 cannot be specified anymore in an insn template at the same time as Disp32. Unlike for non-64-bit mode, templates don't specify displacements for both possible addressing modes; the necessary adjustment to the expected ones has already been done in match_template() anyway (but of course the logic there needs tweaking now). Hence the single template so far doing so is split.
2022-07-04x86: restore masking of displacement kindsJan Beulich1-16/+15
Commit 7d5e4556a375 rendered the check near the end of what is now i386_finalize_displacement() entirely dead for AT&T mode, since for operands involving a displacement .unspecified will always be set. But the logic there is bogus anyway - Intel syntax operand size specifiers are of no interest there either. The only thing which matters in the "displacement only" determination is .baseindex. Of course when masking displacement kinds we should not at the same time also mask off other attributes. Furthermore the type mask returned by lex_got() also needs to be adjusted: The only case where we want Disp32 (rather than Disp32S) is when dealing with 32-bit addressing mode in 64-bit code.
2022-07-04x86-64: improve handling of branches to absolute addressesJan Beulich5-2/+53
There are two related problems here: The use of "addr32" on a direct branch would, besides causing a warning, result in operands to be permitted which mistakenly are refused without "addr32". Plus at some point not too long ago I'm afraid it may have been me who regressed the relocation addends emitted for such branches. Correct both problems, adding a testcase to guard against regressing this again.
2022-06-29opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess7-57/+67
The function aarch64_print_operand (aarch64-opc.c) is responsible for converting an instruction operand into the textual representation of that operand. In some cases, a comment is included in the operand representation, though this (currently) only happens for the last operand of the instruction. In a future commit I would like to enable the new libopcodes styling for AArch64, this will allow objdump and GDB[1] to syntax highlight the disassembler output, however, having operands and comments combined in a single string like this makes such styling harder. In this commit, I propose to extend aarch64_print_operand to take a second buffer. Any comments for the instruction are written into this extra buffer. The two callers of aarch64_print_operand are then updated to pass an extra buffer, and print any resulting comment. In this commit no styling is added, that will come later. However, I have adjusted the output slightly. Before this commit some comments would be separated from the instruction operands with a tab character, while in other cases the comment was separated with two single spaces. After this commit I use a single tab character in all cases. This means a few test cases needed updated. If people would prefer me to move everyone to use the two spaces, then just let me know. Or maybe there was a good reason why we used a mix of styles, I could probably figure out a way to maintain the old output exactly if that is critical. Other than that, there should be no user visible changes after this commit. [1] GDB patches have not been merged yet, but have been posted to the GDB mailing list: https://sourceware.org/pipermail/gdb-patches/2022-June/190142.html
2022-06-28RISC-V: Add 'Sstc' extension and its CSRsTsukasa OI12-0/+125
This commit adds "stimecmp / vstimecmp" Extension (Sstc) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Sstc' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Sstc' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_STIMECMP, CSR_STIMECMPH, CSR_VSTIMECMP, CSR_VSTIMECMPH): New CSR macros.
2022-06-28RISC-V: Add 'Sscofpmf' extension with its CSRsTsukasa OI12-0/+817
This commit adds Count Overflow and Mode-Based Filtering Extension (Sscofpmf) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Sscofpmf' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Sscofpmf' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_SCOUNTOVF, CSR_MHPMEVENT3H, CSR_MHPMEVENT4H, CSR_MHPMEVENT5H, CSR_MHPMEVENT6H, CSR_MHPMEVENT7H, CSR_MHPMEVENT8H, CSR_MHPMEVENT9H, CSR_MHPMEVENT10H, CSR_MHPMEVENT11H, CSR_MHPMEVENT12H, CSR_MHPMEVENT13H, CSR_MHPMEVENT14H, CSR_MHPMEVENT15H, CSR_MHPMEVENT16H, CSR_MHPMEVENT17H, CSR_MHPMEVENT18H, CSR_MHPMEVENT19H, CSR_MHPMEVENT20H, CSR_MHPMEVENT21H, CSR_MHPMEVENT22H, CSR_MHPMEVENT23H, CSR_MHPMEVENT24H, CSR_MHPMEVENT25H, CSR_MHPMEVENT26H, CSR_MHPMEVENT27H, CSR_MHPMEVENT28H, CSR_MHPMEVENT29H, CSR_MHPMEVENT30H, CSR_MHPMEVENT31H): New CSR macros.
2022-06-28RISC-V: Add 'Smstateen' extension and its CSRsTsukasa OI12-0/+525
This commit adds State Enable Extension (Smstateen) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Smstateen' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Smstateen' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_MSTATEEN0, CSR_MSTATEEN1, CSR_MSTATEEN2, CSR_MSTATEEN3, CSR_SSTATEEN0, CSR_SSTATEEN1, CSR_SSTATEEN2, CSR_SSTATEEN3, CSR_HSTATEEN0, CSR_HSTATEEN1, CSR_HSTATEEN2, CSR_HSTATEEN3, CSR_MSTATEEN0H, CSR_MSTATEEN1H, CSR_MSTATEEN2H, CSR_MSTATEEN3H, CSR_HSTATEEN0H, CSR_HSTATEEN1H, CSR_HSTATEEN2H, CSR_HSTATEEN3H): New CSR macros.
2022-06-28RISC-V: Add new CSR feature gate handling (RV32,H)Tsukasa OI1-4/+7
To support feature gate like Smstateen && H, this commit adds certain CSR feature gate handling. It also changes how RV32-only CSRs are handled for cleanliness. gas/ChangeLog: * config/tc-riscv.c (riscv_csr_address): Add CSR feature gate handling for H. Change handling on RV32.
2022-06-27drop XC16x bitsJan Beulich55-2676/+0
Commit 04f096fb9e25 ("Move the xc16x target to the obsolete list") moved the architecture from the "obsolete but still available" to the "obsolete / support removed" list in config.bfd, making the architecture impossible to enable (except maybe via "enable everything" options"). Note that I didn't touch */po/*.po{,t} on the assumption that these would be updated by some (half)automatic means.
2022-06-22RISC-V: Reorder the prefixed extensions which are out of order.Nelson Chu6-15/+0
This patch has been pending for almost a year... However, I noticed that llvm can already re-order the extensions, even if they are out of orders. Not really sure if they can also re-order the single letter extensions, but at least we can do this for the multi-letter extensions in binutils. bfd/ * elfxx-riscv.c (riscv_parse_prefixed_ext): Removed the code which are used to check the prefixed extension orders. gas/ * testsuite/gas/riscv/march-fail-order-x-z.d: Removed since we will help tp reorder the prefixed extensions for now. * testsuite/gas/riscv/march-fail-order-x-z.l: Likewise. * testsuite/gas/riscv/march-fail-order-x.d: Likewise. * testsuite/gas/riscv/march-fail-order-x.l: Likewise. * testsuite/gas/riscv/march-fail-order-z.d: Likewise. * testsuite/gas/riscv/march-fail-order-z.l: Likewise.
2022-06-22RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu12-309/+361
According to the picture 28.1 in the current ISA spec, h is no larger the multi-letter extension, it is a single extension after v. Therefore, this patch fix the implementation, and use the single h to control hypervisor CSRs and instructions, which we promised to do before. bfd/ * elfxx-riscv.c (riscv_supported_std_ext): Added h with version 1.0 after v. (riscv_supported_std_h_ext): Removed. (riscv_all_supported_ext): Updated since riscv_supported_std_h_ext is removed. (riscv_prefix_ext_class): Removed RV_ISA_CLASS_H. (parse_config): Updated since riscv_prefix_ext_class is removed. (riscv_recognized_prefixed_ext): Likewise. (riscv_get_default_ext_version): Likewise. (riscv_multi_subset_supports): Handle INSN_CLASS_H for hypervisor instructions. (riscv_multi_subset_supports_ext): Likewise. gas/ * config/tc-riscv.c (riscv_csr_class): Added CSR_CLASS_H and CSR_CLASS_H_32 for hypervisor CSRs. (riscv_csr_address): Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Updated since hypervisor CSRs are controlled by single h extension for now. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/h-ext-32.d: Added h to architecture string. * testsuite/gas/riscv/h-ext-64.d: Likewise. * testsuite/gas/riscv/march-fail-single-prefix-h: Removed since h is no longer multi-letter extension. * testsuite/gas/riscv/march-fail-unknown-h.d: Likewise. include/ * opcode/riscv-opc.h: Control hypervisor CSRs by h extension, rather than the privileged spec verisons. * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_H. opcodes/ * riscv-opc.c (riscv_opcodes): Control hypervisor instructions by h extension.
2022-06-22RISC-V: Fix inconsistent error message (range)Tsukasa OI1-1/+1
This commit fixes inconsistent error message format involving compressed funct<n> fields. In specific, funct6 had an error message with range 0..2^<n> ("0..64") unlike other funct<n> fields with 0..2^<n>-1 (e.g. funct4 with "0..15"). gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Fix inconsistent error message.
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