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2020-03-03x86: Improve -malign-branchHongtao Liu7-32/+378
According to intel SDM manual, not all compare flag-modifying instructions are marcro-fusible with subsequent jcc instructions. For those non-fusible instructions, -malign-branch doesn't need to align them, only jcc itself needs to be aligned. Here are 2 restrictions which separate macro-fusible instruction from not Restriction 1: If TEST/AND/CMP/ADD/SUB/INC/DEC is one of the following format: cmp m, imm add m, imm sub m, imm test m, imm and m, imm inc m dec m it is unfusible with any jcc instruction. Restriction 2: /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture Note it also works for Skylake and Cascadelake. --------------------------------------------------------------------- | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | | ------ | ----------- | ------- | -------- | | Jo | N | N | Y | | Jno | N | N | Y | | Jc/Jb | Y | N | Y | | Jae/Jnb | Y | N | Y | | Je/Jz | Y | Y | Y | | Jne/Jnz | Y | Y | Y | | Jna/Jbe | Y | N | Y | | Ja/Jnbe | Y | N | Y | | Js | N | N | Y | | Jns | N | N | Y | | Jp/Jpe | N | N | Y | | Jnp/Jpo | N | N | Y | | Jl/Jnge | Y | Y | Y | | Jge/Jnl | Y | Y | Y | | Jle/Jng | Y | Y | Y | | Jg/Jnle | Y | Y | Y | Update maybe_fused_with_jcc_p to check if operands of CMP like instructions can be fused with condition jump. * gas/config/tc-i386.h (i386_tc_frag_data): Add member mf_type. (TC_FRAG_INIT): Init mf_type. * gas/config/tc-i386.c (enum mf_jcc_kind): New enum. (enum mf_cmp_kind): Ditto. (maybe_fused_with_jcc_p): Add argument mf_cmp_p to get mf_type of corresponding instructons, exclude unfusible instructions. (add_fused_jcc_padding_frag_p): Likewise. (add_branch_padding_frag_p): Likewise. (output_insn): Record mf_type for corresponding instructions. (i386_macro_fusible_p): New function. (i386_next_fusible_jcc_frag): Rename from i386_next_jcc_frag, add argument cmp_fragP to return next fusible jcc frag only. (i386_classify_machine_dependant_frag): Seperate macro-fusible instructions from condition jump. * gas/testsuite/gas/i386/align-branch-9.s: New file. * gas/testsuite/gas/i386/align-branch-9.d: Ditto. * gas/testsuite/gas/i386/x86-64-align-branch-9.s: Ditto. * gas/testsuite/gas/i386/x86-64-align-branch-9.d: Ditto. * gas/testsuite/gas/i386/i386.exp: Run new tests.
2020-03-03Fix a potential illegal memory access in the Z80 assembler.Sergey Belyashov2-8/+30
PR 25604 * config/tc-z80.c (contains_register): Prevent an illegal memory access when checking an expression for a register name.
2020-03-03Tidy obj-coff.hAlan Modra2-14/+5
* config/obj-coff.h: Remove vestiges of coff-m68k and pe-mips support.
2020-03-02miscellaneous SEC_SMALL_DATAAlan Modra6-56/+34
This patch arranges for symbols defined in .sdata and .sbss to be reported by nm with 'g' and 's' flags, for coff targets that support .sdata and .sbss. The assembler changes regarding SEC_SMALL_DATA are really just documentation. As far as I'm aware, this won't change any assembler output. bfd/ * coff-alpha.c (alpha_ecoff_le_vec): Add SEC_SMALL_DATA to applicable section flags. * coff-mips.c (mips_ecoff_le_vec, mips_ecoff_be_vec): Likewise. (mips_ecoff_bele_vec): Likewise. * coffcode.h (sec_to_styp_flags): Set SEC_SMALL_DATA for .sdata and .sbss sections. * ecoff.c (_bfd_ecoff_new_section_hook): Likewise. (_bfd_ecoff_styp_to_sec_flags): Likewise. gas/ * config/tc-m32r.c (md_begin): Set SEC_SMALL_DATA on .scommon section. * config/tc-mips.c (s_change_sec): Set SEC_SMALL_DATA for .sdata and .sbss sections. * config/tc-score.c: Delete !BFD_ASSEMBLER code throughout. (s3_s_change_sec): Set SEC_SMALL_DATA for .sbss section. (s3_s_score_lcomm): Likewise. * config/tc-score7.c: Similarly. * read.c (bss_alloc): Set SEC_SMALL_DATA for .sbss section.
2020-02-28MIPS/fix_loongson3_llsc: fix when target has multi labelsYunQiang Su2-5/+51
When there is multi-labels on the same insn, the current code will take care about the last one. it may cause that no sync is added at the target. Here we scan all labels with same value of S_GET_VALUE(label_list->label) by label_list->next. 2020-02-28 YunQiang Su <syq@debian.org> PR gas/25539 * config/tc-mips.c (fix_loongson3_llsc): Compare label value to handle multi-labels. (has_label_name): New.
2020-02-26[binutils][arm] Arm CDE CX*A instructions allow condition codeMatthew Malcomson5-46/+50
The implementation of the Arm CDE CX*A instructions doesn't allow a condition code on the instructions but does allow the instruction in an ITBlock. The specification has been recently updated, though this is yet to be published. The instructions now should allow a suffix, and should behave in the standard way around ITBlocks. This patch removes the custom pred_instruction_type and handling for these instructions, and uses the standard INSIDE_IT_INSN predication type to describe the new instructions. gas/ChangeLog: 2020-02-26 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (enum pred_instruction_type): Remove NEUTRAL_IT_NO_VPT_INSN predication type. (cxn_handle_predication): Modify to require condition suffixes. (handle_pred_state): Remove NEUTRAL_IT_NO_VPT_INSN cases. * testsuite/gas/arm/cde-scalar.s: Update test. * testsuite/gas/arm/cde-warnings.l: Update test. * testsuite/gas/arm/cde-warnings.s: Update test.
2020-02-26gas gettext warningAlan Modra2-1/+6
gettext("") returns the header entry with meta information, not the empty string. * config/tc-arm.c (reg_expected_msgs[REG_TYPE_RNB]): Don't use N_() on empty string.
2020-02-26gas strncpy warningAlan Modra2-1/+7
Avoid a warning that the buffer may not be zero terminated. * read.c (read_a_source_file): Call strncpy with length one less than size of original_case_string.
2020-02-26Indent labelsAlan Modra22-63/+87
Labels don't go in the first column according to standard emacs C indent rules, and I got annoyed enough at seeing diff -p show a label rather than the function name to fix this. bfd/ * aoutx.h: Indent labels correctly. Format error strings. * archive.c: Likewise. * archive64.c: Likewise. * coff-arm.c: Likewise. * coff-rs6000.c: Likewise. * coff-stgo32.c: Likewise. * cpu-arm.c: Likewise. * dwarf2.c: Likewise. * elf-ifunc.c: Likewise. * elf-properties.c: Likewise. * elf-s390-common.c: Likewise. * elf-strtab.c: Likewise. * elf.c: Likewise. * elf32-arm.c: Likewise. * elf32-bfin.c: Likewise. * elf32-cr16.c: Likewise. * elf32-csky.c: Likewise. * elf32-i386.c: Likewise. * elf32-m68k.c: Likewise. * elf32-msp430.c: Likewise. * elf32-nds32.c: Likewise. * elf32-nios2.c: Likewise. * elf32-pru.c: Likewise. * elf32-xtensa.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-x86-64.c: Likewise. * elfcode.h: Likewise. * elfcore.h: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * elfnn-riscv.c: Likewise. * elfxx-mips.c: Likewise. * elfxx-sparc.c: Likewise. * elfxx-x86.c: Likewise. * i386lynx.c: Likewise. * merge.c: Likewise. * pdp11.c: Likewise. * plugin.c: Likewise. * reloc.c: Likewise. binutils/ * elfedit.c: Indent labels correctly. * readelf.c: Likewise. * resres.c: Likewise. gas/ * config/obj-elf.c: Indent labels correctly. * config/obj-macho.c: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-frv.c: Likewise. * config/tc-i386-intel.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-nds32.c: Likewise. * config/tc-riscv.c: Likewise. * config/tc-s12z.c: Likewise. * config/tc-xtensa.c: Likewise. * config/tc-z80.c: Likewise. * read.c: Likewise. * symbols.c: Likewise. * write.c: Likewise. ld/ * emultempl/cskyelf.em: Indent labels correctly. * ldfile.c: Likewise. * ldlang.c: Likewise. * plugin.c: Likewise. opcodes/ * aarch64-asm.c: Indent labels correctly. * aarch64-dis.c: Likewise. * aarch64-gen.c: Likewise. * aarch64-opc.c: Likewise. * alpha-dis.c: Likewise. * i386-dis.c: Likewise. * nds32-asm.c: Likewise. * nfp-dis.c: Likewise. * visium-dis.c: Likewise.
2020-02-20RISC-V: Support the read-only CSR checking.Nelson Chu8-0/+543
CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of CSR address is 0x3. The read-only CSR can not be written by the CSR instructions. gas/ * config/tc-riscv.c (riscv_ip): New boolean insn_with_csr to indicate we are assembling instruction with CSR. Call riscv_csr_read_only_check after parsing all arguments. (enum csr_insn_type): New enum is used to classify the CSR instruction. (riscv_csr_insn_type, riscv_csr_read_only_check): New functions. These are used to check if we write a read-only CSR by the CSR instruction. * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: New testcase. Test all CSR for the read-only CSR checking. * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-02.s: New testcase. Test all CSR instructions for the read-only CSR checking. * testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise.
2020-02-20RISC-V: Disable the CSR checking by default.Nelson Chu5-3/+50
Add new .option `csr-check/no-csr-check` and GAS option `-mcsr-check /-mno-csr-check` to enbale/disable the CSR checking. Disable the CSR checking by default. gas/ * config/tc-riscv.c: Add new .option and GAS options to enbale/disable the CSR checking. We disable the CSR checking by default. (reg_lookup_internal): Check the `riscv_opts.csr_check` before we doing the CSR checking. * doc/c-riscv.texi: Add description for the new .option and assembler options. * testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsr-check` to enable the CSR checking. * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
2020-02-20RISC-V: Support the ISA-dependent CSR checking.Nelson Chu8-9/+198
According to the riscv privilege spec, some CSR are only valid when rv32 or the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS to record more informaton we need, and then check whether the CSR is valid according to these information. We report warning message when the CSR is invalid, so we have a choice between error and warning by --fatal-warnings option. Also, a --no-warn/-W option is used to turn the warnings off, if people don't want the warnings. gas/ * config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide whether or not this CSR is legal in the current ISA string. (struct riscv_csr_extra): New structure to hold all extra information of CSR. (riscv_init_csr_hash): New function. According to the DECLARE_CSR and DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash. Call hash_reg_name to insert CSR address into reg_names_hash. (md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR. (reg_csr_lookup_internal, riscv_csr_class_check): New functions. Decide whether the CSR is valid according to the csr_extra_hash. (init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is not a boolean. This is same as riscv_init_csr_hash, so keep the consistent usage. * testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option. * testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option. * testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the f-ext CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv64if, so the rv32-only CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. include/ * opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to record riscv_csr_class. opcodes/ * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed. gdb/ * riscv-tdep.c: Updated since the DECLARE_CSR is changed. * riscv-tdep.h: Likewise. * features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without rv32-only CSR. * features/riscv/64bit-csr.xml: Regernated. binutils/ * dwarf.c: Updated since the DECLARE_CSR is changed.
2020-02-21pdp11 reloc processingAlan Modra2-13/+22
This allows pdp11 to handle 32-bit fixups that can be applied by gas, and improves the error message emitted when the required reloc isn't available. * config/tc-pdp11.c (md_apply_fix): Handle BFD_RELOC_32. (tc_gen_reloc): Only give a BAD_CASE assertion on pcrel relocs.
2020-02-21PR25569, PDP11 ld -s clobbers last data byteAlan Modra2-20/+35
This patch fixes an ancient wart in aout support, in that text and data section sizes are rounded up for alignment rather that just the corresponding header sizes. Changing section sizes could conceivably result in buffer overflows if section contents were held in memory. Also, keeping the original section sizes allows this PR to be fixed nicely. bfd/ PR 25569 * aoutx.h (adjust_o_magic, adjust_z_magic, adjust_n_magic): Use "text", "data" and "bss" section pointer vars. Don't update section size, just exec header sizes. (adjust_sizes_and_vmas): Don't update text section size. Set initial exec header a_text. Print exec headers sizes. * pdp11.c (adjust_o_magic, adjust_z_magic, adjust_n_magic), (adjust_sizes_and_vmas): Similarly. Formatting. (final_link): Correct final file extension. gas/ PR 25569 * config/obj-aout.c (obj_aout_frob_file_before_fix): Don't loop on section size adjustment, instead perform another write if exec header size is larger than section size.
2020-02-19RISC-V: Add description for -march-attr/-mno-arch-attr options in gas doc.Nelson Chu2-0/+19
gas/ * doc/c-riscv.texi: Add the doc entries for -march-attr/ -mno-arch-attr command line options.
2020-02-19RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.Jim Wilson3-0/+19
2020-02-19 Nelson Chu <nelson.chu@sifive.com> gas/ * testsuite/gas/riscv/c-add-addi.d: New testcase. * testsuite/gas/riscv/c-add-addi.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed c.mv/c.li if rs1 is zero. Change-Id: Id939b5e6db80d267a832545f3ffef7b9ba881f7d
2020-02-19Various fixes for the Z80 support.Sergey Belyashov25-229/+209
PR 25537 ld * emultempl/z80.em: Remove machine compatability checking. PR 25517 * testsuite/ld-z80/arch_ez80_adl.d: Update command line. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80n.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z80_ez80.d: Likewise. * testsuite/ld-z80/comb_arch_z80_z180.d: Likewise. * testsuite/ld-z80/comb_arch_z80_z80n.d: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_ez80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80n.d: Likewise. bfd * cpu-z80.c: Add machine type compatibility checking. gas * config/tc-z80.c (md_parse_option): Do not use an underscore prefix for local labels in SDCC compatability mode. (z80_start_line_hook): Remove SDCC dollar label support. * testsuite/gas/z80/sdcc.d: Update expected disassembly. * testsuite/gas/z80/sdcc.s: Likewise. * config/tc-z80.c: Add -march option. * doc/as.texi: Update Z80 documentation. * doc/c-z80.texi: Likewise. * testsuite/gas/z80/ez80_adl_all.d: Update command line. * testsuite/gas/z80/ez80_adl_suf.d: Likewise. * testsuite/gas/z80/ez80_pref_dis.d: Likewise. * testsuite/gas/z80/ez80_z80_all.d: Likewise. * testsuite/gas/z80/ez80_z80_suf.d: Likewise. * testsuite/gas/z80/gbz80_all.d: Likewise. * testsuite/gas/z80/r800_extra.d: Likewise. * testsuite/gas/z80/r800_ii8.d: Likewise. * testsuite/gas/z80/r800_z80_doc.d: Likewise. * testsuite/gas/z80/sdcc.d: Likewise. * testsuite/gas/z80/z180.d: Likewise. * testsuite/gas/z80/z180_z80_doc.d: Likewise. * testsuite/gas/z80/z80_doc.d: Likewise. * testsuite/gas/z80/z80_ii8.d: Likewise. * testsuite/gas/z80/z80_in_f_c.d: Likewise. * testsuite/gas/z80/z80_op_ii_ld.d: Likewise. * testsuite/gas/z80/z80_out_c_0.d: Likewise. * testsuite/gas/z80/z80_sli.d: Likewise. * testsuite/gas/z80/z80n_all.d: Likewise. * testsuite/gas/z80/z80n_reloc.d: Likewise.
2020-02-19x86: Mark cvtpi2ps and cvtpi2pd as MMXH.J. Lu6-1/+36
* config/tc-i386.c (output_insn): Mark cvtpi2ps and cvtpi2pd with GNU_PROPERTY_X86_FEATURE_2_MMX. * testsuite/gas/i386/i386.exp: Run property-3 and x86-64-property-3. * testsuite/gas/i386/property-3.d: New file. * testsuite/gas/i386/property-3.s: Likewise. * testsuite/gas/i386/x86-64-property-3.d: Likewise.
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu3-5/+14
AMD ABM has 2 instructions: popcnt and lzcnt. ABM CPUID feature bit has been reused for lzcnt and a POPCNT CPUID feature bit is added for popcnt which used to be the part of SSE4.2. This patch removes CpuABM and adds CpuPOPCNT. It changes ABM to enable both lzcnt and popcnt, changes SSE4.2 to also enable popcnt. gas/ * config/tc-i386.c (cpu_arch): Add .popcnt. * doc/c-i386.texi: Remove abm and .abm. Add popcnt and .popcnt. Add a tab before @samp{.sse4a}. opcodes/ * i386-gen.c (cpu_flag_init): Replace CpuABM with CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add CPU_POPCNT_FLAGS. (cpu_flags): Remove CpuABM. Add CpuPOPCNT. * i386-opc.h (CpuABM): Removed. (CpuPOPCNT): New. (i386_cpu_flags): Remove cpuabm. Add cpupopcnt. * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on popcnt. Remove CpuABM from lzcnt. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2020-02-17x86: fold AddrPrefixOpReg templatesJan Beulich2-48/+72
There's no need to have separate Cpu64 and CpuNo64 templates: There already is special logic handling the attribute, and all that's needed is rejecting 16-bit address registers in 64-bit mode. Suppress suffix guessing and group all involved logic together, outside of suffix processing (arguably it doesn't even belong in process_suffix()). Also, since no AddrPrefixOpReg template permits any suffixes, move the No_*Suf specifiers for them to a central place. Along with this drop the no longer relevant NoRex64 from there.
2020-02-17x86/Intel: don't swap operands of MONITOR{,X} and MWAIT{,X}Jan Beulich9-4/+124
Generally, the documentation doesn't allow for any explicit operands to be specified with MONITOR/MWAIT. To permit the more legible overriding of the address size via specifying operands, the option is being retained even in Intel mode, but operand swapping is being suppressed by this patch. This is both because it makes no sense here (all of the operands are inputs) and because, as a result, old gcc (prior to 4.8) actually expects it this way with -mintel-syntax (and hence gets fixed by this change rather than, as claimed by a reply in the bug report, broken).
2020-02-17x86/Intel: improve diagnostics for ambiguous VCVT* operandsJan Beulich10-45/+115
Conversions which shrink element size and which have a memory source can't be disambiguated between their 128- and 256-bit variants by looking at the register operand. "operand size mismatch", however, is a pretty misleading diagnostic. Generalize the logic introduced for VFPCLASSP{S,D} such that, with suitable similar adjustments to the respective templates, it'll cover these cases too. For VCVTNEPS2BF16 also fold the two previously separate AVX512VL templates to achieve the intended effect. This is then also accompanied by a respective addition to the inval-avx512f testcase.
2020-02-16x86: Don't disable SSE4a when disabling SSE4H.J. Lu3-2/+13
commit 7deea9aad8 changed nosse4 to include CpuSSE4a. But AMD SSE4a is a superset of SSE3 and Intel SSE4 is a superset of SSSE3. Disable Intel SSE4 shouldn't disable AMD SSE4a. This patch restores nosse4. It also adds .sse4a and nosse4a. gas/ * config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a. Restore nosse4. * doc/c-i386.texi: Document sse4a and nosse4a. opcodes/ * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove CPU_ANY_SSE4_FLAGS.
2020-02-14Remove the old movsx and movzx documentation for AT&T syntaxH.J. Lu2-16/+5
* doc/c-i386.texi: Remove the old movsx and movzx documentation for AT&T syntax.
2020-02-14x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZXJan Beulich29-87/+1673
For these to get treatment consistent with other operand size checking the special logic shouldn't live in md_assemble(), but process_suffix(). And there's more logic involved than simply zapping the suffix. Note however that MOVS[BW]* and MOVZ[BW]* still won't be fully consistent, due to the objection to fold MOVS* templates just like was done for MOVZ* in c07315e0c6 ("x86: allow suffix-less movzw and 64-bit movzb"). Note further that it is against my own intentions to have MOVSX/MOVZX silently default to a byte source in AT&T mode. This should happen only when the destination register is a 16-bit one. In all other cases there is an ambiguity, and the user should be warned. But it was explicitly requested for this to be done in a way inconsistent with everything else. Note finally that the assembler change points out (and this patch fixes) a wrong Intel syntax test introduced by bc31405ebb2c ("x86-64: Properly encode and decode movsxd"): When source code specifies a 16-bit destination register, disassembly expectations shouldn't have been to find a 32-bit one.
2020-02-14x86: adjust segment override prefix emissionJan Beulich4-6/+29
Since we already suppress the prefix altogether when it's the default one for the chosen addressing mode, let's do so also when instruction prefix and override specified with the memory operand match. (Note that insn prefix specified segment overrides never get discarded.)
2020-02-14x86: optimize away pointless segment overridesJan Beulich4-3/+31
When optimizing there's no point keeping the segment overrides when we warn about their presence in the first place.
2020-02-14x86: extend LEA's segment override warningJan Beulich6-3/+33
For one both possible forms should be warned about. And then, to guard against future surprises, qualify the original opcode check by excluding VEX/EVEX-like templates.
2020-02-14x86: Document movsx/movsxd/movzx for AT&T syntaxH.J. Lu2-0/+59
Document different mnemonics of movsx, movsxd and movzx in AT&T syntax. PR gas/25438 * doc/c-i386.texi: Document movsx, movsxd and movzx for AT&T syntax.
2020-02-13x86: Resolve PLT32 reloc aganst local symbol to sectionH.J. Lu7-2/+62
Since PLT entry isn't needed for branch to local symbol, we can resolve R_386_PLT32/R_X86_64_PLT32 relocation aganst local symbol to section, similar to R_386_PC32/R_X86_64_PC32. 2020-02-13 Fangrui Song <maskray@google.com> H.J. Lu <hongjiu.lu@intel.com> PR gas/25551 * config/tc-i386.c (tc_i386_fix_adjustable): Don't check BFD_RELOC_386_PLT32 nor BFD_RELOC_X86_64_PLT32. * testsuite/gas/i386/i386.exp: Run relax-5 and x86-64-relax-4. * testsuite/gas/i386/relax-5.d: New file. * testsuite/gas/i386/relax-5.s: Likewise. * testsuite/gas/i386/x86-64-relax-4.d: Likewise. * testsuite/gas/i386/x86-64-relax-4.s: Likewise.
2020-02-13x86: fix SSE4a dependencies of ".arch .nosse*"Jan Beulich2-1/+6
Since ".arch .sse4a" enables SSE3 and earlier, disabling SSE3 should also disable SSE4a. And as per its name, ".arch .nosse4" should also do so.
2020-02-12x86: correct VFPCLASSP{S,D} operand size handlingJan Beulich6-5/+93
With AVX512VL disabled (e.g. when writing code for the Knights family of processors) these insns aren't ambiguous when used with a memory source, and hence should be accepted without suffix or operand size specifier. When AVX512VL is enabled, to be consistent with this as well as other ambiguous operand size handling it would seem better to just warn about the ambiguity in AT&T mode, and still default to 512-bit operands (on the assumption that the code may have been written without AVX512VL in mind yet), but it was requested to leave AT&T syntax mode alone here.
2020-02-12x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich11-3/+88
AMD and Intel differ in their handling of far indirect branches as well as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note how the latter three were hybrids so far, while far branches were fully AMD-like.)
2020-02-12x86: also disallow non-byte/-word registers with byte/word suffixJan Beulich7-71/+62
Along the lines of be4c5e58bd ("x86: Always disallow double word suffix with word general register") also adjust check_{byte,word}_reg(), to make overall behavior consistent again in this regard.
2020-02-12x86/Intel: improve diagnosticsJan Beulich2-4/+11
The diagnostics issued by check_*_reg() are pretty AT&T-centric. Re-use logic already used for SIMD memory operand size checking also for ones where GPRs would alternatively also be allowed. (There's certainly room for further improvement here.)
2020-02-11x86: drop ShortForm attributeJan Beulich2-3/+16
It is very simple to derive from other template properties, and hence there's little point wasting storage for it.
2020-02-11[binutils][gas] Fix build failure with -std=c89Matthew Malcomson2-2/+7
My previous patch introduced the use of a C99 feature. C99 standard is not required for gas, so this feature should be removed. Committed as obvious. gas/ChangeLog: 2020-02-11 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (vcx_handle_register_arguments): Remove `for` loop initial declaration.
2020-02-10[binutils][arm] Implement Custom Datapath Extensions for MVEMatthew Malcomson13-4/+1393
Here we implement the custom datapath extensions for MVE. This required the following changes: - Adding a new register argument type (that takes either an MVE vector or a Neon S or D register). - Adding two new immediate operands types (0-127 and 0-4095). - Using the Neon type machinery to distinguish between instruction types. This required the introduction of new neon shapes to account for the coprocessor operands to these instructions. - Adding a new disassembly character to `print_insn_cde` to handle the new register types. Specification can be found at https://developer.arm.com/docs/ddi0607/latest Successfully regression tested on arm-none-eabi, and arm-wince-pe. gas/ChangeLog: 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (NEON_MAX_TYPE_ELS): Increment to account for instructions that can have 5 arguments. (enum operand_parse_code): Add new operands. (parse_operands): Account for new operands. (S5): New macro. (enum neon_shape_el): Introduce P suffixes for coprocessor. (neon_select_shape): Account for P suffix. (LOW1): Move macro to global position. (HI4): Move macro to global position. (vcx_assign_vec_d): New. (vcx_assign_vec_m): New. (vcx_assign_vec_n): New. (enum vcx_reg_type): New. (vcx_get_reg_type): New. (vcx_size_pos): New. (vcx_vec_pos): New. (vcx_handle_shape): New. (vcx_ensure_register_in_range): New. (vcx_handle_register_arguments): New. (vcx_handle_insn_block): New. (vcx_handle_common_checks): New. (do_vcx1): New. (do_vcx2): New. (do_vcx3): New. * testsuite/gas/arm/cde-missing-fp.d: New test. * testsuite/gas/arm/cde-missing-fp.l: New test. * testsuite/gas/arm/cde-missing-mve.d: New test. * testsuite/gas/arm/cde-missing-mve.l: New test. * testsuite/gas/arm/cde-mve-or-neon.d: New test. * testsuite/gas/arm/cde-mve-or-neon.s: New test. * testsuite/gas/arm/cde-mve.s: New test. * testsuite/gas/arm/cde-warnings.l: * testsuite/gas/arm/cde-warnings.s: * testsuite/gas/arm/cde.d: * testsuite/gas/arm/cde.s: opcodes/ChangeLog: 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (print_insn_cde): Define 'V' parse character. (cde_opcodes): Add VCX* instructions.
2020-02-10[binutils][arm] arm support for ARMv8.m Custom Datapath ExtensionMatthew Malcomson10-3/+1330
This patch is part of a series that adds support for the Armv8.m ARMv8.m Custom Datapath Extension to binutils. This patch introduces the Custom Instructions Class 1/2/3 (Single/ Dual, Accumulator/Non-accumulator varianats) to the arm backend. The following Custom Instructions are added: cx1, cx1a, cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da. Specification can be found at https://developer.arm.com/docs/ddi0607/latest This patch distinguishes between enabling CDE for different coprocessor numbers by defining multiple architecture flags. This means that the parsing of the architecture extension flags is kept entirely in the existing code path. We introduce a new IT block state to indicate the behaviour of these instructions. This new state allows being used in an IT block or outside an IT block, but does not allow the instruction to be used inside a VPT block. We need this since the CX*A instruction versions can be used in IT blocks, but they aren't to have the conditional suffixes on them. Hence we need to mark an instruction as allowed in either position. We also need a new flag to objdump, in order to determine whether to disassemble an instruction as CDE related or not. Successfully regression tested on arm-none-eabi, and arm-wince-pe. gas/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (arm_ext_cde*): New feature sets for each CDE coprocessor that can be enabled. (enum pred_instruction_type): New pred type. (BAD_NO_VPT): New error message. (BAD_CDE): New error message. (BAD_CDE_COPROC): New error message. (enum operand_parse_code): Add new immediate operands. (parse_operands): Account for new immediate operands. (check_cde_operand): New. (cde_coproc_enabled): New. (cde_coproc_pos): New. (cde_handle_coproc): New. (cxn_handle_predication): New. (do_custom_instruction_1): New. (do_custom_instruction_2): New. (do_custom_instruction_3): New. (do_cx1): New. (do_cx1a): New. (do_cx1d): New. (do_cx1da): New. (do_cx2): New. (do_cx2a): New. (do_cx2d): New. (do_cx2da): New. (do_cx3): New. (do_cx3a): New. (do_cx3d): New. (do_cx3da): New. (handle_pred_state): Define new IT block behaviour. (insns): Add newn CX*{,d}{,a} instructions. (CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table): Define new cdecp extension strings. * doc/c-arm.texi: Document new cdecp extension arguments. * testsuite/gas/arm/cde-scalar.d: New test. * testsuite/gas/arm/cde-scalar.s: New test. * testsuite/gas/arm/cde-warnings.d: New test. * testsuite/gas/arm/cde-warnings.l: New test. * testsuite/gas/arm/cde-warnings.s: New test. * testsuite/gas/arm/cde.d: New test. * testsuite/gas/arm/cde.s: New test. include/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * opcode/arm.h (ARM_EXT2_CDE): New extension macro. (ARM_EXT2_CDE0): New extension macro. (ARM_EXT2_CDE1): New extension macro. (ARM_EXT2_CDE2): New extension macro. (ARM_EXT2_CDE3): New extension macro. (ARM_EXT2_CDE4): New extension macro. (ARM_EXT2_CDE5): New extension macro. (ARM_EXT2_CDE6): New extension macro. (ARM_EXT2_CDE7): New extension macro. opcodes/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (struct cdeopcode32): New. (CDE_OPCODE): New macro. (cde_opcodes): New disassembly table. (regnames): New option to table. (cde_coprocs): New global variable. (print_insn_cde): New (print_insn_thumb32): Use print_insn_cde. (parse_arm_disassembler_options): Parse coprocN args.
2020-02-10x86: Accept Intel64 only instruction by defaultH.J. Lu5-12/+52
Commit d835a58baae720 disabled sysenter/sysenter in 64-bit mode by default. By default, assembler should accept common, Intel64 only and AMD64 ISAs since there are no conflicts. gas/ PR gas/25516 * config/tc-i386.c (intel64): Renamed to ... (isa64): This. (match_template): Accept Intel64 only instruction by default. (i386_displacement): Updated. (md_parse_option): Updated. * c-i386.texi: Update -mamd64/-mintel64 documentation. * testsuite/gas/i386/i386.exp: Run x86-64-sysenter. Pass -mamd64 to x86-64-sysenter-amd. * testsuite/gas/i386/x86-64-sysenter.d: New file. opcodes/ PR gas/25516 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64 with ISA64. * i386-opc.h (AMD64): Removed. (Intel64): Likewose. (AMD64): New. (INTEL64): Likewise. (INTEL64ONLY): Likewise. (i386_opcode_modifier): Replace amd64 and intel64 with isa64. * i386-opc.tbl (Amd64): New. (Intel64): Likewise. (Intel64Only): Likewise. Replace AMD64 with Amd64. Update sysenter/sysenter with Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter. * i386-tbl.h: Regenerated.
2020-02-10gas: error for section type, attr, or entsize changeAlan Modra4-8/+31
* config/obj-elf.c (obj_elf_change_section): Error for section type, attr or entsize changes in assembly. * testsuite/gas/elf/elf.exp: Pass -Z to gas for section5 test. * testsuite/gas/elf/section5.l: Update.
2020-02-10gas -Z flagAlan Modra3-2/+9
-Z is supposed to "generate object file even after errors". It doesn't do so at the moment, unless you count a zero length object file as useful output. Fixed for most targets as follows. I suspect avr and pru need target patches. * output-file.c (output_file_close): Do a normal close when flag_always_generate_output. * write.c (write_object_file): Don't stop output when flag_always_generate_output.
2020-02-07Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add ↵Sergey Belyashov10-128/+4039
DWARF debug info support to the Z80 assembler. PR 25469 bfd * archures.c: Add GBZ80 and Z80N machine values. * reloc.c: Add BFD_RELOC_Z80_16_BE. * coff-z80.c: Add support for new reloc. * coffcode.h: Add support for new machine values. * cpu-z80.c: Add support for new machine names. * elf32-z80.c: Add support for new reloc. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. binutils* readelf.c (get_machine_flags): Add support for Z80N machine number. gas * config/tc-z80.c: Add -gbz80 command line option to generate code for the GameBoy Z80. Add support for generating DWARF. * config/tc-z80.h: Add support for DWARF debug information generation. * doc/c-z80.texi: Document new command line option. * testsuite/gas/z80/gbz80_all.d: New file. * testsuite/gas/z80/gbz80_all.s: New file. * testsuite/gas/z80/z80.exp: Run the new tests. * testsuite/gas/z80/z80n_all.d: New file. * testsuite/gas/z80/z80n_all.s: New file. * testsuite/gas/z80/z80n_reloc.d: New file. include * coff/internal.h (R_IMM16BE): Define. * elf/z80.h (EF_Z80_MACH_Z80N): Define. (R_Z80_16_BE): New reloc. ld * emulparams/elf32z80.sh: Use z80 emulation. * emultempl/z80.em: Make generic to both COFF and ELF Z80 emulations. * emultempl/z80elf.em: Delete. * testsuite/ld-elf/pr22450.d: Expect to fail for the Z80. * testsuite/ld-elf/sec64k.exp: Fix Z80 assembly. * testsuite/ld-unique/pr21529.s: Avoid register name conflict. * testsuite/ld-unique/unique.s: Likewise. * testsuite/ld-unique/unique_empty.s: Likewise. * testsuite/ld-unique/unique_shared.s: Likewise. * testsuite/ld-unique/unique.d: Updated expected output. * testsuite/ld-z80/arch_z80n.d: New file. * testsuite/ld-z80/comb_arch_z80_z80n.d: New file. * testsuite/ld-z80/labels.s: Add more labels. * testsuite/ld-z80/relocs.s: Add more reloc tests. * testsuite/ld-z80/relocs_f_z80n.d: New file opcodes * z80-dis.c: Add support for GBZ80 opcodes.
2020-02-06ELF: Support the section flag 'o' in .section directiveH.J. Lu14-5/+197
As shown in https://sourceware.org/bugzilla/show_bug.cgi?id=25490 --gc-sections will silently remove __patchable_function_entries section and generate corrupt result. This patch adds the section flag 'o' to .section directive: .section __patchable_function_entries,"awo",@progbits,foo .section __patchable_function_entries,"awoG",@progbits,foo,foo,comdat .section __patchable_function_entries,"awo",@progbits,bar,unique,4 .section __patchable_function_entries,"awoG",@progbits,foo,foo,comdat,unique,1 which specifies the symbol name which the section references. Assmebler will set its elf_linked_to_section to a local section where the symbol is defined. Linker is updated to call mark_hook if gc_mark of any of its linked-to sections is set after all sections, except for backend specific ones, have been garbage collected. bfd/ PR gas/25381 * bfd-in2.h: Regenerated. * elflink.c (_bfd_elf_gc_mark_extra_sections): Call mark_hook on section if gc_mark of any of its linked-to sections is set and don't set gc_mark again. * section.c (asection): Add linked_to_symbol_name to map_head union. gas/ PR gas/25381 * config/obj-elf.c (get_section): Also check linked_to_symbol_name. (obj_elf_change_section): Also set map_head.linked_to_symbol_name. (obj_elf_parse_section_letters): Handle the 'o' flag. (build_group_lists): Renamed to ... (build_additional_section_info): This. Set elf_linked_to_section from map_head.linked_to_symbol_name. (elf_adjust_symtab): Updated. * config/obj-elf.h (elf_section_match): Add linked_to_symbol_name. * doc/as.texi: Document the 'o' flag. * testsuite/gas/elf/elf.exp: Run PR gas/25381 tests. * testsuite/gas/elf/section18.d: New file. * testsuite/gas/elf/section18.s: Likewise. * testsuite/gas/elf/section19.d: Likewise. * testsuite/gas/elf/section19.s: Likewise. * testsuite/gas/elf/section20.d: Likewise. * testsuite/gas/elf/section20.s: Likewise. * testsuite/gas/elf/section21.d: Likewise. * testsuite/gas/elf/section21.l: Likewise. * testsuite/gas/elf/section21.s: Likewise. ld/ PR ld/24526 PR ld/25021 PR ld/25490 * testsuite/ld-elf/elf.exp: Run PR ld/25490 tests. * testsuite/ld-elf/pr24526.d: New file. * testsuite/ld-elf/pr24526.s: Likewise. * testsuite/ld-elf/pr25021.d: Likewise. * testsuite/ld-elf/pr25021.s: Likewise. * testsuite/ld-elf/pr25490-2-16.rd: Likewise. * testsuite/ld-elf/pr25490-2-32.rd: Likewise. * testsuite/ld-elf/pr25490-2-64.rd: Likewise. * testsuite/ld-elf/pr25490-2.s: Likewise. * testsuite/ld-elf/pr25490-3-16.rd: Likewise. * testsuite/ld-elf/pr25490-3-32.rd: Likewise. * testsuite/ld-elf/pr25490-3-64.rd: Likewise. * testsuite/ld-elf/pr25490-3.s: Likewise. * testsuite/ld-elf/pr25490-4-16.rd: Likewise. * testsuite/ld-elf/pr25490-4-32.rd: Likewise. * testsuite/ld-elf/pr25490-4-64.rd: Likewise. * testsuite/ld-elf/pr25490-4.s: Likewise. * testsuite/ld-elf/pr25490-5-16.rd: Likewise. * testsuite/ld-elf/pr25490-5-32.rd: Likewise. * testsuite/ld-elf/pr25490-5-64.rd: Likewise. * testsuite/ld-elf/pr25490-5.s: Likewise. * testsuite/ld-elf/pr25490-6-16.rd: Likewise. * testsuite/ld-elf/pr25490-6-32.rd: Likewise. * testsuite/ld-elf/pr25490-6-64.rd: Likewise. * testsuite/ld-elf/pr25490-6.s: Likewise.
2020-02-06[2.34] Mention x86 assembler options to align branchesH.J. Lu2-0/+10
* NEWS: Mention x86 assembler options to align branches for binutils 2.34.
2020-02-06x86: Run unique tests only for ELF targetsH.J. Lu4-4/+9
* testsuite/gas/i386/i386.exp: Run unique and x86-64-unique only for ELF targets. * testsuite/gas/i386/unique.d: Don't xfail. * testsuite/gas/i386/x86-64-unique.d: Likewise.
2020-02-06xfail x86 gas unique testAlan Modra3-0/+7
* testsuite/gas/i386/unique.d: xfail for non-elf targets. * testsuite/gas/i386/x86-64-unique.d: Likewise.
2020-02-06mbind gas tests and supports_gnu_osabi testsuite infrastructureAlan Modra5-12/+16
With the addition of section16 tests we have multiple tests advertising themselves as "mbind sections" and "mbind section contents". This patch fixes that, and fails on quite a few targets that force an OSABI value. It's a pain specifying all the relevant arm targets on an xfail line, so I wrote supports_gnu_osabi. binutils/ * testsuite/lib/binutils-common.exp (match_target): Accept '!' before TCL procedure. (supports_gnu_osabi): New procedure. (is_generic): New, from ld-lib.exp. (supports_gnu_unique): Use the above. gas/ * testsuite/gas/elf/section12a.d: Use supports_gnu_osabi in xfail, and rename test. * testsuite/gas/elf/section12b.d: Likewise. * testsuite/gas/elf/section16a.d: Likewise. * testsuite/gas/elf/section16b.d: Likewise. ld/ * testsuite/lib/ld-lib.exp (is_generic): Delete. * testsuite/ld-unique/unique.exp: Exclude tic6x.
2020-02-02ELF: Add support for unique section ID to assemblerH.J. Lu24-51/+491
Clang's integrated assembler supports multiple section with the same name: .section .text,"ax",@progbits,unique,1 nop .section .text,"ax",@progbits,unique,2 nop "unique,N" assigns the number, N, as the section ID, to a section. The valid values of the section ID are between 0 and 4294967295. It can be used to distinguish different sections with the same section name. This is useful with -fno-unique-section-names -ffunction-sections. -ffunction-sections by default generates .text.foo, .text.bar, etc. Using the same string can save lots of space in .strtab. This patch adds section_id to bfd_section and reuses the linker internal bit in BFD section flags, SEC_LINKER_CREATED, for assmebler internal use to mark valid section_id. It also updates objdump to compare section pointers if 2 sections comes from the same file since 2 different sections can have the same section name. bfd/ PR gas/25380 * bfd-in2.h: Regenerated. * ecoff.c (bfd_debug_section): Add section_id. * section.c (bfd_section): Add section_id. (SEC_ASSEMBLER_SECTION_ID): New. (BFD_FAKE_SECTION): Add section_id. binutils/ PR gas/25380 * objdump.c (sym_ok): Return FALSE if 2 sections are in the same file with different section pointers. gas/ PR gas/25380 * config/obj-elf.c (section_match): Removed. (get_section): Also match SEC_ASSEMBLER_SECTION_ID and section_id. (obj_elf_change_section): Replace info and group_name arguments with match_p. Also update the section ID and flags from match_p. (obj_elf_section): Handle "unique,N". Update call to obj_elf_change_section. * config/obj-elf.h (elf_section_match): New. (obj_elf_change_section): Updated. * config/tc-arm.c (start_unwind_section): Update call to obj_elf_change_section. * config/tc-ia64.c (obj_elf_vms_common): Likewise. * config/tc-microblaze.c (microblaze_s_data): Likewise. (microblaze_s_sdata): Likewise. (microblaze_s_rdata): Likewise. (microblaze_s_bss): Likewise. * config/tc-mips.c (s_change_section): Likewise. * config/tc-msp430.c (msp430_profiler): Likewise. * config/tc-rx.c (parse_rx_section): Likewise. * config/tc-tic6x.c (tic6x_start_unwind_section): Likewise. * doc/as.texi: Document "unique,N" in .section directive. * testsuite/gas/elf/elf.exp: Run "unique,N" tests. * testsuite/gas/elf/section15.d: New file. * testsuite/gas/elf/section15.s: Likewise. * testsuite/gas/elf/section16.s: Likewise. * testsuite/gas/elf/section16a.d: Likewise. * testsuite/gas/elf/section16b.d: Likewise. * testsuite/gas/elf/section17.d: Likewise. * testsuite/gas/elf/section17.l: Likewise. * testsuite/gas/elf/section17.s: Likewise. * testsuite/gas/i386/unique.d: Likewise. * testsuite/gas/i386/unique.s: Likewise. * testsuite/gas/i386/x86-64-unique.d: Likewise. * testsuite/gas/i386/i386.exp: Run unique and x86-64-unique. ld/ PR gas/25380 * testsuite/ld-i386/pr22001-1c.S: Use "unique,N" in .section directives. * testsuite/ld-i386/tls-gd1.S: Likewise. * testsuite/ld-x86-64/pr21481b.S: Likewise.
2020-02-02elf/section13.s: Replace @nobits with %nobitsH.J. Lu2-1/+5
* testsuite/gas/elf/section13.s: Replace @nobits with %nobits.
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