aboutsummaryrefslogtreecommitdiff
path: root/gas
AgeCommit message (Collapse)AuthorFilesLines
2019-03-28PR24390, Don't decode mtfsb field as a cr fieldAlan Modra3-8/+14
"mtfsb0 4*cr7+lt" doesn't make all that much sense, but unfortunately glibc uses just that instead of "mtfsb0 28" to clear the fpscr xe bit. So for backwards compatibility accept cr field expressions when assembling mtfsb operands, but disassemble to a plain number. PR 24390 include/ * opcode/ppc.h (PPC_OPERAND_CR_REG): Comment. opcodes/ * ppc-opc.c (BTF): Define. (powerpc_opcodes): Use for mtfsb*. * ppc-dis.c (print_insn_powerpc): Print fields with both PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. gas/ * testsuite/gas/ppc/476.d: Update mtfsb*. * testsuite/gas/ppc/a2.d: Likewise.
2019-03-21Remove strip_underscore from struct emulationAlan Modra3-6/+7
This field is unused. I would have liked to also remove leading_underscore and fake_label_name but in an i386-elf/coff/aout multi-obj setup those fields are used to select a different fake_label_name for aout. * emul.h (struct emulation): Delete strip_underscore. * emul-target.h (emul_strip_underscore): Don't define. (emul_struct_name): Update initialization.
2019-03-21Teach a few targets to resolve BFD_RELOC_8Alan Modra6-46/+38
and tidy "forward" test. I've removed some checks in d30v md_apply_fix that have no business being there. Any symbol problems will be caught later in tc_gen_reloc, and overflow checking is done in gas/write.c. * config/tc-d10v.c (md_apply_fix): Apply BFD_RELOC_8. * config/tc-pdp11.c (md_apply_fix): Likewise. * config/tc-d30v.c (md_apply_fix): Don't emit errors for BFD_RELOC_8, BFD_RELOC_16, and BFD_RELOC_64. * testsuite/gas/all/gas.exp: Move target exclusions for forward test, but not cr16, to.. * testsuite/gas/all/forward.d: ..here, with explanation. Remove d10v, d30v, and pdp11 xfails.
2019-03-19x86: Correct EVEX vector load/store optimizationH.J. Lu15-145/+196
Update EVEX vector load/store optimization: 1. There is no need to check AVX since AVX2 is required for AVX512F. 2. We need to check both operands for ZMM register since AT&T syntax may not set zmmword on the first operand. 3. Update Opcode_SIMD_IntD check and set. 4. Since the VEX prefix has 2 or 3 bytes, the EVEX prefix has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 bytes, we choose EVEX Disp8 over VEX Disp32. * config/tc-i386.c (optimize_encoding): Don't check AVX for EVEX vector load/store optimization. Check both operands for ZMM register. Update EVEX vector load/store opcode check. Choose EVEX Disp8 over VEX Disp32. * testsuite/gas/i386/optimize-1.d: Updated. * testsuite/gas/i386/optimize-1a.d: Likewise. * testsuite/gas/i386/optimize-2.d: Likewise. * testsuite/gas/i386/optimize-4.d: Likewise. * testsuite/gas/i386/optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2a.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2b.d: Likewise. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise. * testsuite/gas/i386/x86-64-optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-6.d: Likewise. * testsuite/gas/i386/optimize-1.s: Add ZMM register load test. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
2019-03-19x86: Correct EVEX to 128-bit EVEX optimizationH.J. Lu6-33/+200
Since not all AVX512F processors support AVX512VL, we can optimize 512-bit EVEX to 128-bit EVEX encoding for upper 16 vector registers only when AVX512VL is enabled explicitly at command-line or via ".arch .avx512vl" directive. PR gas/24352 * config/tc-i386.c (optimize_encoding): Check only cpu_arch_flags.bitfield.cpuavx512vl. * testsuite/gas/i386/i386.exp: Run x86-64-optimize-2b. * testsuite/gas/i386/x86-64-optimize-2.d: Revert the last change. * testsuite/gas/i386/x86-64-optimize-2b.d: New file. * testsuite/gas/i386/x86-64-optimize-2b.s: Likewise.
2019-03-19ix86: Disable AVX512F when disabling AVX2H.J. Lu20-258/+276
Since AVX2 is required for AVX512F, we should disable AVX512F when AVX2 is disabled. gas/ PR gas/24359 * testsuite/gas/i386/i386.exp: Change optimize-6a, optimize-7, x86-64-optimize-7a and x86-64-optimize-8 tests to run_list_test. Remove optimize-6c and x86-64-optimize-7c tests. * testsuite/gas/i386/noavx-3.l: Updated. * testsuite/gas/i386/noavx-4.d: Likewise. * testsuite/gas/i386/noavx-5.d: Likewise. * testsuite/gas/i386/noavx-3.s: Add AVX512F tests. * testsuite/gas/i386/noavx-4.s: Remove AVX512F tests. * testsuite/gas/i386/nosse-5.s: Likewise. * testsuite/gas/i386/optimize-6a.d: Removed. * testsuite/gas/i386/optimize-6c.d: Likewise. * testsuite/gas/i386/optimize-7.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7c.d: Likewise. * testsuite/gas/i386/x86-64-optimize-8.d: Likewise. * testsuite/gas/i386/optimize-6a.l: New file. * testsuite/gas/i386/optimize-6a.s: Likewise. * testsuite/gas/i386/optimize-7.l: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.l: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.s: Likewise. * testsuite/gas/i386/x86-64-optimize-8.l: Likewise. opcodes/ PR gas/24359 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to CPU_ANY_AVX2_FLAGS. * i386-init.h: Regenerated.
2019-03-18Use temp_ilp and restore_ilp in more placesAlan Modra4-11/+8
* as.c (macro_expr): Use temp_ilp and restore_ilp. * macro.c (buffer_and_nest): Likewise. * read.c (temp_ilp): Remove FIXME.
2019-03-18Fix MRI mode testsuite failuresAlan Modra2-7/+8
These fails were introduced by git commit 2469b3c584 with the inroduction of "input_from_string": m68k-linux FAIL: MRI structured for m68k-linux FAIL: MRI structured if m68k-linux FAIL: MRI structured repeat m68k-linux FAIL: MRI structured while Since the m68k parser called expression() without setting input_from_string, get_symbol_name rejected FAKE_LABEL_CHAR in names. * config/m68k-parse.y (yylex): Use temp_ilp and restore_ilp.
2019-03-18x86: Pass -O0 to assembler for some testsH.J. Lu11-6/+23
* testsuite/gas/i386/att-regs.d: Pass -O0 to assembler. * testsuite/gas/i386/avx512bw-intel.d: Likewise. * testsuite/gas/i386/avx512bw.d: Likewise. * testsuite/gas/i386/avx512f-intel.d: Likewise. * testsuite/gas/i386/avx512f.d: Likewise. * testsuite/gas/i386/disp32.d: Likewise. * testsuite/gas/i386/intel-regs.d: Likewise. * testsuite/gas/i386/pseudos.d: Likewise. * testsuite/gas/i386/x86-64-disp32.d: Likewise. * testsuite/gas/i386/x86-64-pseudos.d: Likewise.
2019-03-18x86: Optimize EVEX vector load/store instructionsH.J. Lu29-1/+974
When there is no write mask, we can encode lower 16 128-bit/256-bit EVEX vector register load and store instructions as VEX vector register load and store instructions with -O1. gas/ PR gas/24348 * config/tc-i386.c (optimize_encoding): Encode 128-bit and 256-bit EVEX vector register load/store instructions as VEX vector register load/store instructions for -O1. * doc/c-i386.texi: Update -O1 documentation. * testsuite/gas/i386/i386.exp: Run PR gas/24348 tests. * testsuite/gas/i386/optimize-1.s: Add tests for EVEX vector load/store instructions. * testsuite/gas/i386/optimize-2.s: Likewise. * testsuite/gas/i386/optimize-3.s: Likewise. * testsuite/gas/i386/optimize-5.s: Likewise. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise. * testsuite/gas/i386/x86-64-optimize-3.s: Likewise. * testsuite/gas/i386/x86-64-optimize-4.s: Likewise. * testsuite/gas/i386/x86-64-optimize-5.s: Likewise. * testsuite/gas/i386/x86-64-optimize-6.s: Likewise. * testsuite/gas/i386/optimize-1.d: Updated. * testsuite/gas/i386/optimize-2.d: Likewise. * testsuite/gas/i386/optimize-3.d: Likewise. * testsuite/gas/i386/optimize-4.d: Likewise. * testsuite/gas/i386/optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise. * testsuite/gas/i386/x86-64-optimize-4.d: Likewise. * testsuite/gas/i386/x86-64-optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-6.d: Likewise. * testsuite/gas/i386/optimize-7.d: New file. * testsuite/gas/i386/optimize-7.s: Likewise. * testsuite/gas/i386/x86-64-optimize-8.d: Likewise. * testsuite/gas/i386/x86-64-optimize-8.s: Likewise. opcodes/ PR gas/24348 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32 and vmovdqu64. * i386-tbl.h: Regenerated.
2019-03-18x86: Encode 256-bit/512-bit VEX/EVEX insns with 128-bit VEXH.J. Lu6-15/+206
Since all AVX512 processors support AVX, we can encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions at -O1. * config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions at -O1. * doc/c-i386.texi: Update -O1 and -O2 documentation. * testsuite/gas/i386/i386.exp: Run optimize-1a and x86-64-optimize-2a. * testsuite/gas/i386/optimize-1a.d: New file. * testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
2019-03-17x86: Set optimize to INT_MAX for -OsH.J. Lu6-1/+30
Set optimize to INT_MAX, instead of -1, for -Os so that -Os will include -O2 optimization. PR gas/24353 * config/tc-i386.c (md_parse_option): Set optimize to INT_MAX for -Os. * testsuite/gas/i386/optimize-2.s: Add a test. * testsuite/gas/i386/x86-64-optimize-3.s: Likewise. * testsuite/gas/i386/optimize-2.d: Updated. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
2019-03-17x86: Correctly optimize EVEX to 128-bit VEX/EVEXH.J. Lu12-29/+470
We can optimize 512-bit EVEX to 128-bit EVEX encoding for upper 16 vector registers only when AVX512VL is enabled. We can't optimize EVEX to 128-bit VEX encoding when AVX isn't enabled. PR gas/24352 * config/tc-i386.c (optimize_encoding): Encode 512-bit EVEX with 128-bit VEX encoding only when AVX is enabled and with 128-bit EVEX encoding only when AVX512VL is enabled. * testsuite/gas/i386/i386.exp: Run PR gas/24352 tests. * testsuite/gas/i386/optimize-6.s: New file. * testsuite/gas/i386/optimize-6a.d: Likewise. * testsuite/gas/i386/optimize-6b.d: Likewise. * testsuite/gas/i386/optimize-6c.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7.s: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7b.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7c.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Updated.
2019-03-15Fix a potential illegal memory access whilt parsing an x86 insn.Li Hao2-32/+42
PR 24308 * config/tc-i386.c (parse_insn): Check mnemp before using it to determine if a suffix can be trimmed.
2019-03-13dwarf2: Align relocation within .debug_line sectionChristian Eggers2-3/+19
All relocations specify a byte address. As dwarf debug information is organized in octets, some relocations may not be aligned. While it might be possible to define special relocations that operate at an octet offset from their address, it's easier to ensure the relocations are aligned by padding with "nop" statements. In most dwarf sections this requirement is already fulfilled, only relocations for symbol address within the .debug_line section can be misaligned. * dwarf2dbg.c (out_set_addr): Align relocation within .debug_line.
2019-03-13dwarf2: Pad size of .debug_line section.Christian Eggers2-0/+15
As all dwarf debug information is organized in octets, the size of all dwarf sections must be aligned to OCTETS_PER_BYTE. Most DWARF sections meet this requirement, only the .debug_line section can reach an arbitrary octet size. In order to align the size to a multiple of OCTETS_PER_BYTE, the section is padded with "nop" statements at the end. * dwarf2dbg.c (out_debug_line): Pad size of .debug_line section.
2019-03-13dwarf2: Use octets for .debug_string offsetsChristian Eggers2-3/+7
Like other dwarf2 offsets, also the string offsets in the .debug_info section which points into the .debug_str section must be expressed in octets instead of bytes. * dwarf2dbg.c (out_debug_str): Use octets for .debug_string pointers.
2019-03-13dwarf2: Use octets for .debug_line prologueChristian Eggers2-2/+6
Like the u32 size field at the beginning of the section, also the prologue size must be expressed in octets. * dwarf2dbg.c (out_debug_line): Use octets for .debug_line prologue.
2019-03-13dwarf2: Use octets for dwarf2 headersChristian Eggers2-4/+9
The content of the dwarf2 sections .debug_line, .debug_aranges and .debug_info starts with an u32 containing the the size of the remaining data. According to the dwarf2 specification this value must be expressed in octets instead of bytes. * dwarf2dbg.c (out_debug_line): Use octets for dwarf2 headers. (out_debug_aranges, out_debug_info): Likewise.
2019-03-13Symbols with octets valueChristian Eggers3-1/+49
Up to now, all symbol values are in units of bytes, where a "byte" can consist of one or more octets (e.g. 8 bit or 16 bit). Allow to specfiy that the "unit" of a newly created symbol is octets (exactly 8 bit), instead of bytes. * symbols.h (symbol_temp_new_now_octets): Declare. (symbol_set_value_now_octets, symbol_octets_p): Declare. * symbols.c (struct symbol_flags): New member sy_octets. (symbol_temp_new_now_octets): New function. (resolve_symbol_value): Return octets instead of bytes if sy_octets is set. (symbol_set_value_now_octets): New function. (symbol_octets_p): New function.
2019-03-13dwarf2: Fix calculation of line info offsetChristian Eggers2-1/+5
The units of the value returned by "frag_now_fix()" and "size" do not match. "frag_now_fix()" returns bytes (can be 8, 16 or 32 bit), while "size" is octets (exactly 8 bit). * dwarf2dbg.c (dwarf2_emit_insn): Fix calculation of line info offset.
2019-03-12Add missing changelogs for previous commits.Andreas Krebbel1-0/+5
2019-03-12S/390: arch13: Adjust to recent changesAndreas Krebbel2-48/+43
opcodes/ChangeLog: 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com> * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand from vstrszb, vstrszh, and vstrszf. gas/ChangeLog: 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com> * testsuite/gas/s390/zarch-arch13.s: Adjust testcase to optable changes. * testsuite/gas/s390/zarch-arch13.d: Likewise.
2019-02-27Testsuite: Allow multiple lines of "as" in testsuite.Matthew Malcomson7-33/+14
Committed on behalf of Matthew Malcomson. This allows checking the command line parsing more easily than before by allowing many command line invokations from the same .d file. Each line is used as a set of flags, and the tests are ran against the output of the assembler with each set. Each line of assembler is treated as another set of tests (as if the test file were copied to another with a different #as: line). This patch includes some example uses where multiple testcases can be merged into one file using this new functionality. binutils/ChangeLog: * testsuite/lib/binutils-common.exp: Allow multiple "as" lines. gas/ChangeLog: * testsuite/gas/aarch64/dotproduct.d: Use multiple "as" lines. * testsuite/gas/aarch64/dotproduct_armv8_4.d: Remove. * testsuite/gas/aarch64/dotproduct_armv8_4.s: Remove. * testsuite/gas/aarch64/illegal-dotproduct.d: Use multiple "as" lines. * testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: Remove. * testsuite/gas/aarch64/ldst-rcpc.d: Use multiple "as" lines.
2019-02-24Re: PowerPC __tls_get_addr arg parsingAlan Modra2-0/+6
Fixes non-ELF powerpc build failure: tc-ppc.c:3009:1: error: ‘parse_tls_arg’ defined but not used * config/tc-ppc.c (parse_tls_arg): Wrap in #ifdef OBJ_ELF.
2019-02-24PR24144, pdp11-ld overwriting section data with zerosAlan Modra2-11/+27
bfd/ PR 24144 * pdp11.c (set_section_contents): Revert 2015-02-24 change. gas/ PR 24144 * config/obj-aout.c (obj_aout_frob_file_before_fix): Write to end of section to ensure file contents cover aligned section size.
2019-02-22[arm][gas] Add support for Neoverse N1Kyrylo Tkachov3-1/+9
This adds support for the Neoverse N1 CPU [1] to gas. This was previously enabled under the Ares codename, which remains as a valid option for -mcpu for compatibility reasons. make check-gas passes on arm-none-eabi. [1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-n1-platform-accelerating-the-transformation-to-a-scalable-cloud-to-edge-infrastructure 2019-02-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-arm.c (arm_cpus): Add neoverse-n1. * doc/c-arm.texi (-mcpu): Document neoverse-n1 value.
2019-02-22[AArch64][gas] Add support for Neoverse E1Kyrylo Tkachov3-0/+11
This adds support for the Neoverse E1 CPU [1] to gas. make check-gas passes on aarch64-none-elf. [1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-e1-platform-empowering-the-infrastructure-to-meet-next-generation-throughput-demands 2019-02-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-aarch64.c (aarch64_cpus): Add neoverse-e1. * doc/c-aarch64.texi (-mcpu): Document neoverse-e1 value.
2019-02-22[AArch64][gas] Add support for Neoverse N1Kyrylo Tkachov3-0/+11
This adds support for the Neoverse N1 [1] CPU to gas. This was previously enabled under the Ares codename, which remains as a valid option for -mcpu for compatibility reasons. make check-gas passes on aarch64-none-elf. [1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-n1-platform-accelerating-the-transformation-to-a-scalable-cloud-to-edge-infrastructure 2019-02-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-aarch64.c (aarch64_cpus): Add neoverse-n1. * doc/c-aarch64.texi (-mcpu): Document neoverse-n1 value.
2019-02-21PowerPC __tls_get_addr arg parsingAlan Modra1-40/+52
The syntax we ended up with for -m32 -fPIC calls to __tls_get_addr is rather weird. bl __tls_get_addr+0x8000(gd0@tlsgd)@plt This came about by accident, probably due to requiring the arg reloc before the call reloc. Of course the @plt really belongs with __tls_get_addr since it affects the call rather than the call arg, and it isn't a great deal of trouble to ensure the relocs are emitted in the correct order. This patch supports a newer syntax, like so: bl __tls_get_addr+0x8000@plt(gd0@tlsgd) gas/ * config/tc-ppc.c (parse_tls_arg): New function, extracted.. (md_assembler): ..from here. Call it after parsing other suffix modifiers too. ld/ * testsuite/ld-powerpc/tls32.s: Test new @plt syntax.
2019-02-19Fix a potential deadlock in some older Loongson 3A1000 MIPS processors.Paul Hua7-57/+285
* NEWS: Mention -m[no-]fix-loongson3-llsc. * configure.ac: Add --enable-mips-fix-loongson3-llsc. Define DEFAULT_MIPS_FIX_LOONGSON3_LLSC. * config.in: Regenerated. * configure: Likewise. * config/tc-mips.c (sync_insn, mips_fix_loongson3_llsc): New variables. (options): New OPTION_FIX_LOONGSON3_LLSC, OPTION_NO_FIX_LOONGSON3_LLSC. (md_longopts): Add -m[no-]fix-loongson3-llsc. (md_begin): Initialize sync insn. (fix_loongson3_llsc): New. (append_insn): Call fix_loongson3_llsc. (md_parse_option): Handle OPTION_FIX_LOONGSON3_LLSC, OPTION_NO_FIX_LOONGSON3_LLSC. (md_show_usage): Display -m[no-]fix-loongson3-llsc. * doc/c-mips.texi: Document -m[no-]fix-loongson3-llsc, --enable-mips-fix-loongson3-llsc=[yes|no].
2019-02-10gas: Pass max_bytes to TC_FRAG_INITH.J. Lu17-22/+52
ommit 3ae729d5a4f63740ed9a778960b17c2912b0bbdd Author: H.J. Lu <hjl.tools@gmail.com> Date: Wed Mar 7 04:18:45 2018 -0800 x86: Rewrite NOP generation for fill and alignment increased MAX_MEM_FOR_RS_ALIGN_CODE to 4095 which resulted in increase of assembler time and memory usage by 5 times for inputs with many .p2align directives, which is typical for LTO output. This patch passes max_bytes to TC_FRAG_INIT so that MAX_MEM_FOR_RS_ALIGN_CODE can be set as needed and tracked by backend it so that HANDLE_ALIGN can check the maximum alignment for each rs_align_code frag. Wall time to assemble the same cc1plus.s: before: 423.78user 0.89system 7:05.71elapsed 99%CPU after: 102.35user 0.27system 1:42.89elapsed 99%CPU PR gas/24165 * frags.c (frag_var_init): Pass max_chars to TC_FRAG_INIT as max_bytes. * config/tc-aarch64.h (TC_FRAG_INIT): Add and pass max_bytes to aarch64_init_frag. * /config/tc-arm.h (TC_FRAG_INIT): And and pass max_bytes to arm_init_frag. * config/tc-avr.h (TC_FRAG_INIT): And and ignore max_bytes. * config/tc-ia64.h (TC_FRAG_INIT): Likewise. * config/tc-mmix.h (TC_FRAG_INIT): Likewise. * config/tc-nds32.h (TC_FRAG_INIT): Likewise. * config/tc-ns32k.h (TC_FRAG_INIT): Likewise. * config/tc-rl78.h (TC_FRAG_INIT): Likewise. * config/tc-rx.h (TC_FRAG_INIT): Likewise. * config/tc-score.h (TC_FRAG_INIT): Likewise. * config/tc-tic54x.h (TC_FRAG_INIT): Likewise. * config/tc-tic6x.h (TC_FRAG_INIT): Likewise. * config/tc-xtensa.h (TC_FRAG_INIT): Likewise. * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Set to (alignment ? ((1 << alignment) - 1) : 1) (i386_tc_frag_data): Add max_bytes. (TC_FRAG_INIT): Add and track max_bytes. (HANDLE_ALIGN): Replace MAX_MEM_FOR_RS_ALIGN_CODE with fragP->tc_frag_data.max_bytes. * doc/internals.texi: Update TC_FRAG_TYPE with max_bytes.
2019-02-08Add missing ChangeLog files for previous patch.Jim Wilson1-0/+5
2019-02-08RISC-V: Compress 3-operand beq/bne against x0.Jim Wilson1-0/+6
This lets us accept an instruction like beq a2,x0,.Label and generate a compressed beqz. This will allow some future simplications to the gcc support, e.g. eliminating some duplicate patterns, and avoiding adding new duplicate patterns, since currently we have to handle signed and equality compares against zero specially. Tested with rv{32,64}-{elf,linux} cross builds and make checks for binutils and gcc. There were no regressions. gas/ * config/tc-riscv.c (validate_riscv_insn) <'C'>: Add 'z' support. (riscv_ip) <'C'>: Add 'z' support. opcodes/ * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form. <bne>: Likewise.
2019-02-07Arm: Backport hlt to all architectures.Tamar Christina5-1/+79
The software trap instruction HLT that was introduced in Armv8-a is used as the semihosting trap instruction in AArch64. In order to allow systems configured to run AArch64 code to also run AArch32 with semihosting it was decided that AArch32 should also use HLT in the case of the "mixed mode" environment. This requires that HLT also be backported to all earlier architectures. The instruction is in the undefined encoding space earlier architectures but must trigger a semihosting trap [3]. The Arm Architectural Reference Manual [1] doesn't explicitly mention this however this is an explicit requirement in the Semihosting-v2 protocol [2]. [1] https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile [2] https://developer.arm.com/docs/100863/latest/the-semihosting-interface [3] https://github.com/qemu/qemu/commit/19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e gas/ChangeLog: * config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for hlt to armv1. * testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs * testsuite/gas/arm/hlt.d: New test. * testsuite/gas/arm/hlt.s: New test. opcodes/ChangeLog: * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2019-02-07AArch64: Add negative tests for Armv8.3-a complex number instructions ↵Tamar Christina3-0/+131
instructions. This patch just adds a few negative tests for the Armv8.3-a complex instructions. These already do the right disassembly without needing a verifier, but adding some tests to make sure that stays that way. gas/ChangeLog: * testsuite/gas/aarch64/undefined_advsimd_armv8_3.d: New test. * testsuite/gas/aarch64/undefined_advsimd_armv8_3.s: New test.
2019-02-07AArch64: Add verifier for By elem Single and Double sized instructions.Tamar Christina3-0/+101
The AArch64 instruction set has cut-outs inside instructions encodings for when a given encoding that would normally fall within the encoding space of an instruction is instead undefined. This updates the first few instructions FMLA, FMLA, FMUL and FMULX in the case where sz:L == 11. gas/ChangeLog: PR binutils/23212 * testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test. * testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test. opcodes/ChangeLog: PR binutils/23212 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. * aarch64-opc.c (verify_elem_sd): New. (fields): Add FLD_sz entr. * aarch64-tbl.h (_SIMD_INSN): New. (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and fmulx scalar and vector by element isns.
2019-02-07Visium: align branch absolute instruction for the GR6Eric Botcazou7-10/+41
This is done in order to avoid a pipeline hazard on the GR6. gas/ * config/tc-visium.c (md_assemble) <mode_cad>: Align instruction on 64-bit boundaries for the GR6. * testsuite/gas/visium/allinsn_gr6.s: Tweak. * testsuite/gas/visium/allinsn_gr6.d: Likewise. * testsuite/gas/visium/bra-1.d: New test. * testsuite/gas/visium/bra-1.s: Likewise. * testsuite/gas/visium/visium.exp: Run bra-1 test.
2019-02-01S12Z: GAS: Allow #_symbol operands as mov sourceJohn Darrington5-35/+115
mov.l, mov.p and mov.w (but not mov.b) when called with an immediate source operand should be accepted a relocatable expression. This change makes that possible. gas/ * config/tc-s12z.c (lex_imm): Add new argument exp_o. (emit_reloc): New function. (md_apply_fix): [BFD_RELOC_S12Z_OPR] Recognise that it can be either 2 bytes or 3 bytes long. * testsuite/gas/s12z/mov-imm-reloc.d: New file. * testsuite/gas/s12z/mov-imm-reloc.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-02-01S12Z: GAS: Fix incorrect range test for 16-bit PC relative offsets.John Darrington8-1/+63
The limits for PC relative offsets were incorrect. This change fixes them and adds some tests. gas/ * config/tc-s12z.c (md_apply_fix): Fix incorrect limits. * testsuite/gas/s12z/pc-rel-bad.d: New file. * testsuite/gas/s12z/pc-rel-bad.l: New file. * testsuite/gas/s12z/pc-rel-bad.s: New file. * testsuite/gas/s12z/pc-rel-good.d: New file. * testsuite/gas/s12z/pc-rel-good.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-02-01S12Z: GAS: Issue warning if TFR/EXG have identical source and destination.John Darrington4-0/+11
It is permissible for the source and destination operands of TFR and EXG to be the same register. However it is a pointless instruction and anyone writing it has probably made a mistake. This change emits a warning if such an instruction is encountered. gas/ * config/tc-s12z.c (tfr): Emit warning if operands are the same. * testsuite/gas/s12z/exg.d: New test case. * testsuite/gas/s12z/exg.l: New file.
2019-02-01S12Z: GAS: Disallow immediate destination operandsJohn Darrington6-36/+107
The assembler permitted instructions which attempted to assign to an immediate operand. Bizarrely there is a valid machine code for such operations (although the documentation says it's "inappropriate"). This change causes such attempts to fail with an error message. gas/ * config/tc-s12z.c (lex_opr): Add a parameter to indicate whether immediate mode operands should be permitted. * testsuite/s12z/imm-dest.d: New file. * testsuite/s12z/imm-dest.l: New file. * testsuite/s12z/imm-dest.s: New file. * testsuite/s12z/s12z.exp: Add them.
2019-01-31S/390: Implement instruction set extensionsAndreas Krebbel7-7/+328
opcodes/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * s390-mkopc.c (main): Accept arch13 as cpu string. * s390-opc.c: Add new instruction formats and instruction opcode masks. * s390-opc.txt: Add new arch13 instructions. include/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH13. gas/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (s390_parse_cpu): New entry for arch13. * doc/c-s390.texi: Document arch13 march option. * testsuite/gas/s390/s390.exp: Run the arch13 related tests. * testsuite/gas/s390/zarch-arch13.d: New test. * testsuite/gas/s390/zarch-arch13.s: New test. * testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics also for z13.
2019-01-31Assorted warning fixesAlan Modra4-8/+15
gcc-9 flagged warnings at the places I'm patching here, all real bugs. * config/tc-alpha.c (md_apply_fix): Correct range checks for BFD_RELOC_ALPHA_NOP, BFD_RELOC_ALPHA_LDA, BFD_RELOC_ALPHA_BSR. * config/tc-arm.c (md_apply_fix): Use llabs rather than abs. * config/tc-csky.c (get_macro_reg_vals): Pass s to csky_show_error.
2019-01-28xtensa: gas: don't keep relocations for constantsMax Filippov3-1/+13
xtensa gas chokes on 8/16 bit data entries representing constant symbols because it leaves BFD_RELOC_8/BFD_RELOC_16 fixups for which xtensa BFD cannot emit relocations. Resolve fixups for constant symbols in md_apply_fix. gas/ 2019-01-28 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (md_apply_fix): Mark fixups for constant symbols as done in md_apply_fix. * testsuite/gas/all/forward.d: Don't XFAIL for xtensa.
2019-01-28Updated Russian and French translations for the gas sub-directoryNick Clifton3-5489/+6351
2019-01-28Control gas enable-checking default by bfd/development.shAlan Modra3-8/+12
* configure.ac (ac_checking): Set from bfd/development.sh development variable. * configure: Regenerate.
2019-01-25AArch64: Add missing changelog for Update encodings for stg, st2g, stzg and ↵Tamar Christina1-0/+10
st2zg
2019-01-25AArch64: Update encodings for stg, st2g, stzg and st2zg.Sudi Das5-69/+102
This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch updates the st*g instructions to use a previously reserved field for a new register operand. Thus the new versions of the instructions are as follows: - STG Xt, [<Xn|SP>, #<simm>] - STG Xt, [<Xn|SP>, #<simm>]! - STG Xt, [<Xn|SP>], #<simm> - STZG Xt, [<Xn|SP>, #<simm>] - STZG Xt, [<Xn|SP>, #<simm>]! - STZG Xt, [<Xn|SP>], #<simm> - ST2G Xt, [<Xn|SP>, #<simm>] - ST2G Xt, [<Xn|SP>, #<simm>]! - ST2G Xt, [<Xn|SP>], #<simm> - STZ2G Xt, [<Xn|SP>, #<simm>] - STZ2G Xt, [<Xn|SP>, #<simm>]! - STZ2G Xt, [<Xn|SP>], #<simm> Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * config/tc-aarch64.c (warn_unpredictable_ldst): Exempt stg, st2g, stzg and stz2g from Xt == Xn with writeback warning. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Change tests for stg, stzg, st2g and stz2g. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** opcodes/ChangeLog *** * aarch64-tbl.h (QL_LDST_AT): Update macro. (aarch64_opcode): Change encoding for stg, stzg st2g and st2zg. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2019-01-25AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension.Sudi Das5-0/+34
This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch adds the new STZGM instruction. STGZM Xt, [<Xn|SP>] Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** opcodes/ChangeLog *** * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
generated by cgit v1.1 at 2025-01-21 07:52:21 +0000