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2008-04-112008-04-11 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu5-4/+11
* gas/lns/lns-big-delta.d: Updated. * gas/lns/lns-common-1.d: Likewise. * gas/lns/lns-common-1-alt.d: Likewise. * gas/lns/lns-duplicate.d: Likewise.
2008-04-11 * listing.c (print_timestamp): Use localtime rather thanNick Clifton2-3/+8
localtime_r since not all build environments provide the latter.
2008-04-10gas/H.J. Lu16-0/+266
2008-04-10 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention -msse-check=[none|error|warning]. * config/tc-i386.c (sse_check): New. (OPTION_MSSE_CHECK): Likewise. (md_assemble): Check SSE instructions if needed. (md_longopts): Add -msse-check. (md_parse_option): Handle OPTION_MSSE_CHECK. (md_show_usage): Show -msse-check=[none|error|warning]. * doc/c-i386.texi: Document -msse-check=[none|error|warning]. gas/testsuite/ 2008-04-10 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run sse-check, sse-check-warn, sse-check-error, x86-64-sse-check, x86-64-sse-check-warn and x86-64-sse-check-error. * gas/i386/sse-check.d: New. * gas/i386/sse-check.s: Likewise. * gas/i386/sse-check-error.l: Likewise. * gas/i386/sse-check-error.s: Likewise. * gas/i386/sse-check-warn.d: Likewise. * gas/i386/sse-check-warn.e: Likewise. * gas/i386/x86-64-sse-check.d: Likewise. * gas/i386/x86-64-sse-check-error.l: Likewise. * gas/i386/x86-64-sse-check-error.s: Likewise. * gas/i386/x86-64-sse-check-warn.d: Likewise.
2008-04-10 * listing.c: Add -ag listing flag to show general information inNick Clifton8-13/+171
listings such as gas version, passed options, and time stamp. (listing_general_info): New function. (print_options): New function. (print_single_option): New function. (print_timestamp): New function. (MAX_DATELEN): Define. (listing_print): Add call to listing_general_info. * listing.h (LISTING_GENERAL): Define. (listing_print): Add new parameter. * as.c (show_usage): Print new switch. (parse_args): Parse new switch. (main): Pass command line on to listing_print. * NEWS: Mention this new feature. * doc/as.texinfo: Document the new sub-option. * gas/all/gas.exp: Check the performance of the -ag command line switch.
2008-04-102008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>Andreas Krebbel2-212/+217
* s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic extensions for conditional jumps (o, p, m, nz, z, nm, np, no). (s390_crb_extensions): New extensions table. (insertExpandedMnemonic): Handle '$' tag. * s390-opc.txt: Remove conditional jump variants which can now be expanded automatically. Replace '*' tag with '$' in the compare and branch instructions. 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/zarch-z10.d: Map the compare and branch variants with odd condition code mask to version with an even mask.
2008-04-07 * dwarf2dbg.c (dwarf2_emit_insn): Simplify test before dwarf2_whereAlan Modra2-32/+31
call. Delete out of date comment. (dwarf2_consume_line_info): Always clear dwarf2_loc_directive_seen. (dwarf2_emit_label): Don't emit unless there has been a previous .file or we are outputting assembler generated debug. dwarf2_consume_line_info after emitting line info, not before. (out_debug_info): Simplify files_in_use test.
2008-04-07Add the missing ymm test in the last checkin.H.J. Lu4-0/+4
2008-04-07gas/H.J. Lu7-0/+24
2008-04-07 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (parse_real_register): Return AVX register only if AVX is enabled. gas/testsuite/ 2008-04-07 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/att-regs.s: Add AVX register test. * gas/i386/intel-regs.s: Likewise. * gas/i386/att-regs.d: Updated. * gas/i386/intel-regs.d: Likewise.
2008-04-07 PR gas/6043Kaz Kojima5-2/+34
* config/tc-sh64.c (shmedia_md_pcrel_from_section): Use md_pcrel_from_section for BFD_RELOC_64 and BFD_RELOC_64_PCREL. * gas/sh/sh64/eh-1.d: New. * gas/sh/sh64/eh-1.d: Likewise.
2008-04-042008-04-04 Adrian Bunk <bunk@stusta.de>Bob Wilson2-2/+8
Bob Wilson <bob.wilson@acm.org> * config/tc-xtensa.c (xg_apply_fix_value): Check return code from call to decode_reloc.
2008-04-04gas/H.J. Lu19-19/+47
2008-04-04 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention XSAVE. Change CLMUL to PCLMUL. * config/tc-i386.c (cpu_arch): Add .pclmul. (md_show_usage): Replace clmul with pclmul. * doc/c-i386.texi: Likewise. gas/testsuite/ 2008-04-04 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/arch-10.s: Likewise. * gas/i386/clmul-intel.d: Likewise. * gas/i386/clmul.d: Likewise. * gas/i386/clmul.s: Likewise. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/x86-64-clmul-intel.d: Likewise. * gas/i386/x86-64-clmul.d: Likewise. * gas/i386/x86-64-clmul.s: Likewise. * gas/i386/arch-10.d: Replace clmul with pclmul. * gas/i386/x86-64-arch-2.d: Likewise. opcodes/ 2008-04-04 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL with CPU_PCLMUL_FLAGS/CpuPCLMUL. (cpu_flags): Replace CpuCLMUL with CpuPCLMUL. * i386-opc.tbl: Likewise. * i386-opc.h (CpuCLMUL): Renamed to ... (CpuPCLMUL): This. (CpuFMA): Updated. (i386_cpu_flags): Replace cpuclmul with cpupclmul. * i386-init.h: Regenerated.
2008-04-03binutils/H.J. Lu49-187/+22245
2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * dwarf.c (dwarf_regnames_i386): Add AVX registers. (dwarf_regnames_x86_64): Likewise. gas/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx. * doc/c-i386.texi: Add avx, aes, clmul and fma to -march=. Document -msse2avx, .avx, .aes, .clmul and .fma. * config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New. (vex_prefix): Likewise. (sse2avx): Likewise. (CPU_FLAGS_ARCH_MATCH): Likewise. (CPU_FLAGS_64BIT_MATCH): Likewise. (CPU_FLAGS_32BIT_MATCH): Likewise. (CPU_FLAGS_PERFECT_MATCH): Likewise. (regymm): Likewise. (vex_imm4): Likewise. (fits_in_imm4): Likewise. (build_vex_prefix): Likewise. (VEX_check_operands): Likewise. (bad_implicit_operand): Likewise. (OPTION_MSSE2AVX): Likewise. (T_YMMWORD): Likewise. (_i386_insn): Add vex. (cpu_arch): Add .avx, .aes, .clmul and .fma. (cpu_flags_match): Changed to take a pointer to const template. Enable encoding SSE instructions with VEX prefix for -msse2avx. (match_mem_size): Also check ymmword. (operand_type_match): Clear ymmword. (md_begin): Allow '_' in mnemonic. (type_names): Add OPERAND_TYPE_VEX_IMM4. (process_immext): Update assert. (md_assemble): Don't call process_immext if sse2avx and immext are true. Call build_vex_prefix if vex is true. (parse_insn): Updated for cpu_flags_match. (swap_operands): Handle 5 operands. (match_template): Handle 5 operands. Updated for cpu_flags_match. Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX. (process_suffix): Handle YMMWORD_MNEM_SUFFIX. (check_byte_reg): Check regymm. (process_operands): Duplicate the destination register for -msse2avx if needed. (build_modrm_byte): Updated for instructions with VEX encoding. (output_insn): Output VEX prefix if needed. (md_longopts): Add msse2avx. (md_parse_option): Handle OPTION_MSSE2AVX. (md_show_usage): Add avx, aes, clmul, fma and -msse2avx. (intel_e09): Support YMMWORD. (intel_e11): Likewise. (intel_get_token): Likewise. gas/testsuite/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes, x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx, x86-64-avx-intel and x86-64-inval-avx. * gas/cfi/cfi-i386.s: Add tests for AVX register maps. * gas/cfi/cfi-x86_64.s: Likewise. * gas/i386/aes.d: New. * gas/i386/aes.s: Likewise. * gas/i386/aes-intel.d: Likewise. * gas/i386/avx.d: Likewise. * gas/i386/avx.s: Likewise. * gas/i386/avx-intel.d: Likewise. * gas/i386/clmul.d: Likewise. * gas/i386/clmul-intel.d: Likewise. * gas/i386/clmul.s: Likewise. * gas/i386/i386.exp: Likewise. * gas/i386/inval-avx.l: Likewise. * gas/i386/inval-avx.s: Likewise. * gas/i386/sse2avx.d: Likewise. * gas/i386/sse2avx.s: Likewise. * gas/i386/x86-64-aes.d: Likewise. * gas/i386/x86-64-aes.s: Likewise. * gas/i386/x86-64-aes-intel.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. * gas/i386/x86-64-clmul.d: Likewise. * gas/i386/x86-64-clmul-intel.d: Likewise. * gas/i386/x86-64-clmul.s: Likewise. * gas/i386/x86-64-inval-avx.l: Likewise. * gas/i386/x86-64-inval-avx.s: Likewise. * gas/i386/x86-64-sse2avx.d: Likewise. * gas/i386/x86-64-sse2avx.s: Likewise. * gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/rexw.s: Add AVX tests. * gas/i386/x86-64-opcode-inval.s: Remove lds/les test. * gas/cfi/cfi-i386.d: Updated. * gas/cfi/cfi-x86_64.d: Likewise. * gas/i386/arch-10.d: Likewise. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/rexw.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-opcode-inval.d: Likewise. * gas/i386/x86-64-opcode-inval-intel.d: Likewise. include/opcode/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * i386.h (MAX_OPERANDS): Set to 5. (MAX_MNEM_SIZE): Changed to 20. opcodes/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_E_register): New. (OP_E_memory): Likewise. (OP_VEX): Likewise. (OP_EX_Vex): Likewise. (OP_EX_VexW): Likewise. (OP_XMM_Vex): Likewise. (OP_XMM_VexW): Likewise. (OP_REG_VexI4): Likewise. (PCLMUL_Fixup): Likewise. (VEXI4_Fixup): Likewise. (VZERO_Fixup): Likewise. (VCMP_Fixup): Likewise. (VPERMIL2_Fixup): Likewise. (rex_original): Likewise. (rex_ignored): Likewise. (Mxmm): Likewise. (XMM): Likewise. (EXxmm): Likewise. (EXxmmq): Likewise. (EXymmq): Likewise. (Vex): Likewise. (Vex128): Likewise. (Vex256): Likewise. (VexI4): Likewise. (EXdVex): Likewise. (EXqVex): Likewise. (EXVexW): Likewise. (EXdVexW): Likewise. (EXqVexW): Likewise. (XMVex): Likewise. (XMVexW): Likewise. (XMVexI4): Likewise. (PCLMUL): Likewise. (VZERO): Likewise. (VCMP): Likewise. (VPERMIL2): Likewise. (xmm_mode): Likewise. (xmmq_mode): Likewise. (ymmq_mode): Likewise. (vex_mode): Likewise. (vex128_mode): Likewise. (vex256_mode): Likewise. (USE_VEX_C4_TABLE): Likewise. (USE_VEX_C5_TABLE): Likewise. (USE_VEX_LEN_TABLE): Likewise. (VEX_C4_TABLE): Likewise. (VEX_C5_TABLE): Likewise. (VEX_LEN_TABLE): Likewise. (REG_VEX_XX): Likewise. (MOD_VEX_XXX): Likewise. (PREFIX_0F38DB..PREFIX_0F38DF): Likewise. (PREFIX_0F3A44): Likewise. (PREFIX_0F3ADF): Likewise. (PREFIX_VEX_XXX): Likewise. (VEX_OF): Likewise. (VEX_OF38): Likewise. (VEX_OF3A): Likewise. (VEX_LEN_XXX): Likewise. (vex): Likewise. (need_vex): Likewise. (need_vex_reg): Likewise. (vex_i4_done): Likewise. (vex_table): Likewise. (vex_len_table): Likewise. (OP_REG_VexI4): Likewise. (vex_cmp_op): Likewise. (pclmul_op): Likewise. (vpermil2_op): Likewise. (m_mode): Updated. (es_reg): Likewise. (PREFIX_0F38F0): Likewise. (PREFIX_0F3A60): Likewise. (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE. (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF and PREFIX_VEX_XXX entries. (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE. (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and PREFIX_0F3ADF. (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE. Add MOD_VEX_XXX entries. (ckprefix): Initialize rex_original and rex_ignored. Store the REX byte in rex_original. (get_valid_dis386): Handle the implicit prefix in VEX prefix bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE. (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before calling get_valid_dis386. Use rex_original and rex_ignored when printing out REX. (putop): Handle "XY". (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and ymmq_mode. (OP_E_extended): Updated to use OP_E_register and OP_E_memory. (OP_XMM): Handle VEX. (OP_EX): Likewise. (XMM_Fixup): Likewise. (CMP_Fixup): Use ARRAY_SIZE. * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS, CPU_FMA_FLAGS and CPU_AVX_FLAGS. (operand_type_init): Add OPERAND_TYPE_REGYMM and OPERAND_TYPE_VEX_IMM4. (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA. (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD, VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources, VexImmExt and SSE2AVX. (operand_types): Add RegYMM, Ymmword and Vex_Imm4. * i386-opc.h (CpuAVX): New. (CpuAES): Likewise. (CpuCLMUL): Likewise. (CpuFMA): Likewise. (Vex): Likewise. (Vex256): Likewise. (VexNDS): Likewise. (VexNDD): Likewise. (VexW0): Likewise. (VexW1): Likewise. (Vex0F): Likewise. (Vex0F38): Likewise. (Vex0F3A): Likewise. (Vex3Sources): Likewise. (VexImmExt): Likewise. (SSE2AVX): Likewise. (RegYMM): Likewise. (Ymmword): Likewise. (Vex_Imm4): Likewise. (Implicit1stXmm0): Likewise. (CpuXsave): Updated. (CpuLM): Likewise. (ByteOkIntel): Likewise. (OldGcc): Likewise. (Control): Likewise. (Unspecified): Likewise. (OTMax): Likewise. (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma. (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256, vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a, vex3sources, veximmext and sse2avx. (i386_operand_type): Add regymm, ymmword and vex_imm4. * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions. * i386-reg.tbl: Add AVX registers, ymm0..ymm15. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2008-03-28/gas:Eric B. Weddington3-1/+7
2008-03-28 Eric B. Weddington <eric.weddington@atmel.com> * config/tc-avr.c (mcu_types): Add attiny167. * doc/c-avr.texi: Likewise. /include: 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com> * opcode/avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
2008-03-28/gas:Eric B. Weddington3-2/+8
2008-03-28 Eric B. Weddington <eric.weddington@atmel.com> * config/tc-avr.c (mcu_types): Add atmega32u4. * doc/c-avr.texi: Likewise.
2008-03-28/gas:Eric B. Weddington3-1/+7
2008-03-28 Eric B. Weddington <eric.weddington@atmel.com> * config/tc-avr.c (mcu_types): Add atmega32c1. * doc/c-avr.texi: Likewise.
2008-03-282008-03-28 Paul Brook <paul@codesourcery.com>Paul Brook2-13/+18
gas/ * config/tc-arm.c (parse_neon_mov): Parse register before immediate to avoid spurious symbols.
2008-03-28 * config/tc-m68k.c (md_convert_frag_1): Replace as_fatal withNathan Sidwell2-1/+7
as_bad_where.
2008-03-27 * config/tc-avr.c (mcu_types): Add atmega32m1.Nick Clifton3-9/+15
* doc/c-avr.texi: Likewise.
2008-03-27 * config/tc-arm.c (do_neon_cvt): Move variable declarations toNick Clifton2-4/+14
start of block. (do_neon_ext): Fix sign of comparison.
2008-03-26gas/testsuite/:Bernd Schmidt29-2281/+2313
From Robin Getz <rgetz@blackfin.uclinux.org> * gas/bfin/arithmetic.d: Update to reflect spaces/capitalization in recent changes in opcodes/bfin-dis.c. gas/bfin/arithmetic.s: Likewise. gas/bfin/bit.d: Likewise. gas/bfin/bit2.d: Likewise. gas/bfin/control_code.d: Likewise. gas/bfin/control_code2.d: Likewise. gas/bfin/event.d: Likewise. gas/bfin/event2.d: Likewise. gas/bfin/flow.d: Likewise. gas/bfin/flow2.d: Likewise. gas/bfin/load.d: Likewise. gas/bfin/logical.d: Likewise. gas/bfin/logical2.d: Likewise. gas/bfin/move.d: Likewise. gas/bfin/move2.d: Likewise. gas/bfin/parallel.d: Likewise. gas/bfin/parallel2.d: Likewise. gas/bfin/parallel3.d: Likewise. gas/bfin/parallel4.d: Likewise. gas/bfin/shift.d: Likewise. gas/bfin/shift2.d: Likewise. gas/bfin/stack.d: Likewise. gas/bfin/stack2.d: Likewise. gas/bfin/store.d: Likewise. gas/bfin/vector.d: Likewise. gas/bfin/vector2.d: Likewise. gas/bfin/video.d: Likewise. gas/bfin/video2.d: Likewise. opcodes/: * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d, c_imm32, c_huimm32e): Define. (constant_formats): Add flags for printing decimal, leading spaces, and exact symbols. (comment, parallel): Add global flags in all disassembly. (fmtconst): Take advantage of new flags, and print default in hex. (fmtconst_val): Likewise. (decode_macfunc): Be consistant with spaces, tabs, comments, capitalization in disassembly, fix minor coding style issues. (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise. (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0, decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0, decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0, decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0, decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0, decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0, decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0, decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0, decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0, _print_insn_bfin, print_insn_bfin): Likewise.
2008-03-26gas/:Bernd Schmidt5-33/+30
* config/tc-bfin.c (bfin_start_line_hook): Localize the labels generated for LOOP_BEGIN and LOOP_END instructions. (bfin_gen_loop): Likewise. gas/testsuite/: * gas/bfin/flow.d: Adjust since the generated labels for LOOP_BEGIN and LOOP_END instruction are local now. * gas/bfin/flow2.d: Likewise.
2008-03-26gas/Bernd Schmidt7-56/+82
* config/bfin-parse.y (check_macfunc_option): Allow (IU) option for multiply and multiply-accumulate to data register instruction. (check_macfuncs): Don't check if accumulator matches the data register here. (assign_macfunc): Check if accumulator matches the data register in each rule that moves to the data register. gas/testsuite/ * gas/bfin/arithmetic.s, gas/bfin/arithmetic.d: Add check for IU option. * gas/bfin/expected_errors.l, gas/bfin/expected_errors.s: Add check for mismatch of accumulator and data register. opcodes/ * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for multiply and multiply-accumulate to data register instruction.
2008-03-26gas/:Bernd Schmidt7-681/+771
* config/bfin-parse.y (check_macfunc_option): New. (check_macfuncs): Check option by calling check_macfunc_option. Fix comparison always true warnings. Both scalar instructions of vector instruction must share the same mode option. Only allow option mode at the end of the second instruction of the vector. (asm_1): Check option by calling check_macfunc_option. gas/testsuite/: * gas/bfin/expected_errors.l, gas/bfin/expected_errors.s: Add tests for bad options of "multiply and multipy-accumulate to accumulator" instructions. Add new vector instruction option mode tests. * gas/bfin/vector2.s: Add new vector instruction option mode test. * gas/bfin/vector2.d: Adjust accordingly. * gas/bfin/expected_errors.s, gas/bfin/expected_errors.l: Add test for mismatched half registers in vector multipy-accumulate instructions.
2008-03-26gas/Bernd Schmidt6-7/+51
From Jie Zhang <jie.zhang@analog.com> * config/bfin-parse.y (asm_1): Check AREGS in comparison instructions. And call yyerror () when comparing PREG with DREG. gas/testsuite/: * gas/bfin/expected_comparison_errors.l: New test. * gas/bfin/expected_comparison_errors.s: New test. * gas/bfin/bfin.exp: Add expected_comparison_errors.
2008-03-26opcodes:Bernd Schmidt2-10/+15
From Robin Getz <robin.getz@analog.com> * bfin-dis.c (bu32): Typedef. (enum const_forms_t): Add c_uimm32 and c_huimm32. (constant_formats[]): Add uimm32 and huimm16. (fmtconst_val): New. (uimm32): Define. (huimm32): Define. (imm16_val): Define. (luimm16_val): Define. (struct saved_state): Define. (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG, A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG, LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define. (get_allreg): New. (decode_LDIMMhalf_0): Print out the whole register value. gas/testsuite: From Jie Zhang <jie.zhang@analog.com> * gas/bfin/load.d: Update.
2008-03-192008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>Andreas Krebbel6-0/+760
* opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z10 added. (s390_cond_extensions): Reduced extensions to the compare related. (main): z10 cpu type option added. (expandConditionalJump): Renamed to ... (insertExpandedMnemonic): ... this. * opcodes/s390-opc.c: Re-group the operand format makros. (INSTR_RIE_RRPU, INSTR_RIE_RRP0, INSTR_RIE_RUPI, INSTR_RIE_R0PI, INSTR_RIE_RUPU, INSTR_RIE_R0PU, INSTR_RIE_R0IU, INSTR_RIE_R0I0, INSTR_RIE_R0UU, INSTR_RIE_R0U0, INSTR_RIE_RRUUU, INSTR_RIS_RURDI, INSTR_RIS_R0RDI, INSTR_RIS_RURDU, INSTR_RIS_R0RDU, INSTR_RRF_U0RR, INSTR_RRF_00RR, INSTR_RRS_RRRDU, INSTR_RRS_RRRD0, INSTR_RXY_URRD, INSTR_SIY_IRD, INSTR_SIL_RDI, INSTR_SIL_RDU): New instruction formats added. (MASK_RIE_RRPU, MASK_RIE_RRP0, MASK_RIE_RUPI, MASK_RIE_R0PI, MASK_RIE_RUPU, MASK_RIE_R0PU, MASK_RIE_R0IU, MASK_RIE_R0I0, MASK_RIE_R0UU, MASK_RIE_R0U0, MASK_RIE_RRUUU, MASK_RIS_RURDI, MASK_RIS_R0RDI, MASK_RIS_RURDU, MASK_RIS_R0RDU, MASK_RRF_U0RR, MASK_RRF_00RR, MASK_RRS_RRRDU, MASK_RRS_RRRD0, MASK_RXY_URRD, MASK_SIY_IRD, MASK_SIL_RDI, MASK_SIL_RDU): New instruction format masks added. (s390_opformats): New formats added "ris", "rrs", "sil". * opcodes/s390-opc.txt: Add the conditional jumps with the extensions removed from automatic expansion in s390-mkopc.c manually. (asi - trtre): Add new System z10 EC instructions. * include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z10 added. 2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com> * config/tc-s390.c (md_parse_option): z10 option added. 2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/zarch-z10.d: New file. * gas/s390/zarch-z10.s: New file. * gas/s390/s390.exp: Run the z10 testcases.
2008-03-18 * gas/macros/test1.s: Rename symbols to avoid conflicts withNick Clifton2-4/+4
possible register names. * gas/macros/test1.d: Update expected disassembly.
2008-03-17 * configure.ac: m4_include config/proginstall.m4.Ralf Wildenhues5-19/+41
* configure: Regenerate. config/ * proginstall.m4: New file, with fixed AC_PROG_INSTALL. bfd/ * aclocal.m4: Regenerate. * configure: Likewise. * Makefile.in: Likewise. bfd/doc/ * Makefile.in: Regenerate. intl/ * aclocal.m4: Regenerate. * configure: Likewise. gas/ * aclocal.m4: Regenerate. * configure: Likewise. * Makefile.in: Likewise. * doc/Makefile.in: Likewise. ld/ * aclocal.m4: Regenerate. * configure: Likewise. * Makefile.in: Likewise. opcodes/ * aclocal.m4: Regenerate. * configure: Likewise. * Makefile.in: Likewise. binutils/ * aclocal.m4: Regenerate. * configure: Likewise. * Makefile.in: Likewise. * doc/Makefile.in: Likewise. gprof/ * aclocal.m4: Regenerate. * configure: Likewise. * Makefile.in: Likewise.
2008-03-17gas/testsuite/Richard Sandiford3-2/+7
* gas/mips/elf-rel26.d: Add -32. * gas/mips/mips16-intermix.d: Likewise. ld/testsuite/ * ld-mips-elf/mips-elf.exp (o32_as_flags, o32_ld_flags): New variables. (mips16_call_global_test, mips16_intermix_test): Use them.
2008-03-16 PR 5946Alan Modra2-18/+5
* config/tc-hppa.c (is_same_frag): Delete.
2008-03-142008-03-14 Sterling Augustine <sterling@tensilica.com>Bob Wilson2-1/+8
* config/tc-xtensa.h (xtensa_relax_statesE): Update comment for RELAX_LOOP_END_ADD_NOP.
2008-03-13PR gas/5895Nick Clifton5-2/+33
* read.c (s_mexit): Warn if attempting to exit a macro when not inside a macro definition. * gas/macros/exit.s: New test case. * gas/macros/macros.exp: Run the new test, expect it to produce an error result.
2008-03-13bfd/Alan Modra4-216/+222
* Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * po/SRC-POTFILES.in: Regenerate. bfd/doc/ * Makefile.in: Regenerate. binutils/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * configure: Regenerate. gas/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * configure: Regenerate. opcodes/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * configure: Regenerate.
2008-03-092008-03-09 Paul Brook <paul@codesourcery.com>Paul Brook3-0/+9
gas/ * config/tc-arm.c (arm_cpu_option_table): Add cortex-a9. * doc/c-arm.texi: Add cortex-a9.
2008-03-092008-03-09 Paul Brook <paul@codesourcery.com>Paul Brook6-11/+93
bfd/ * elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle new Tag_VFP_arch values. binutils/ * readelf.c (arm_attr_tag_VFP_arch): Add "VFPv3-D16". gas/ * config/tc-arm.c (fpu_vfp_ext_d32): New vairable. (parse_vfp_reg_list, encode_arm_vfp_reg): Use it. (arm_option_cpu_value): Add vfpv3-d16, vfpv2 and vfpv3. (aeabi_set_public_attributes): Handle Tag_VFP_arch=VFPV3-D16. * doc/c-arm.texi: Document new ARM FPU variants. gas/testsuite/ * gas/arm/vfpv3-d16-bad.d: New test. * gas/arm/vfpv3-d16-bad.l: New test. include/opcode/ * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
2008-03-082008-03-07 Paul Brook <paul@codesourcery.com>Paul Brook2-1/+5
bfd/ * elf32-arm.c (elf32_arm_howto_table_1): Fix bitmasks for MOVW and MOVT relocations. (elf32_arm_final_link_relocate): Fix off by one MOVW/MOVT sign extension. (elf32_arm_relocate_section): Handle MOVW and MOVT relocations. Improve safety check for other weird relocations. (elf32_arm_check_relocs): Only set h->needs_plt for branch/call relocations. gas/ * config/tc-arm.c (md_apply_fix): Use correct offset range. ld/testsuite/ * ld-arm/arm-elf.exp (armelftests): Add movw-merge and arm-app-movw. * ld-arm/arm-app-movw.s: New test. * ld-arm/arm-app.r: Update expected output. * ld-arm/movw-merge.d: New test. * ld-arm/movw-merge.s: New test.
2008-03-06 * config/tc-ppc.c (ppc_setup_opcodes): Tidy. Add code to testAlan Modra2-9/+52
for strict ordering of powerpc_opcodes, but disable for now.
2008-03-062008-03-06 Florian Krohm <fkrohm@us.ibm.com>Andreas Krebbel7-48/+60
* s390-opc.c (INSTR_RSL_R0RD): Fix operands. * s390-opc.txt (cmpsc): Duplicate entry removed. (dxr, sqdr, sqer, cxfbr, cdfbr, cefbr, lzer, lzdr, lzxr, cegbr, cdgbr, cxgbr, cegr, cdgr, cxgr, cxfr, cdfr, cefr, fixr, fidr, fier, cu42, cu41): Fix operand format. 2008-03-06 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/esa-g5.d (cdfbr, cdfr, cefbr, cefr, cxfbr, cxfr, dxr, fidr, fier, fixr, lzdr, lzer, lzxr, sqdr, sqer, tp): Fix operand format. * gas/s390/esa-g5.s: Likewise. * gas/s390/zarch-z900.d (cdgbr, cdgr, cegbr, cegr, cxgbr, cxgr): Likewise. * gas/s390/zarch-z900.s: Likewise. * gas/s390/zarch-z9-109.d (cu41, cu42): Remove mask operand. * gas/s390/zarch-z9-109.s: Likewise.
2008-03-052008-03-04 Paul Brook <paul@codesourcery.com>Paul Brook7-24/+98
gas/ * config/tc-arm.c (arm_ext_barrier, arm_ext_msr): New. (arm_ext_v7m): Rename... (arm_ext_m): ... to this. Include v6-M. (do_t_add_sub): Allow narrow low-reg non flag setting adds. (do_t_mrs, do_t_msr, aeabi_set_public_attributes): Use arm_ext_m. (md_assemble): Allow wide msr instructions. (insns): Add classifications for v6-m instructions. (arm_cpu_option_table): Add cortex-m1. (arm_arch_option_table): Add armv6-m. (cpu_arch): Add ARM_ARCH_V6M. Fix numbering of other v6 variants. gas/testsuite/ * gas/arm/archv6m.d: New test. * gas/arm/archv6m.s: New test. * gas/arm/t16-bad.s: Test low register non flag setting add. * gas/arm/t16-bad.l: Update expected output. include/opcode/ * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define. (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags. (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
2008-03-03bfd/Bob Wilson2-1/+11
* xtensa-isa.c (xtensa_isa_num_pipe_stages): Make max_stage static and only compute its value once. gas/ * config/tc-xtensa.c (xtensa_num_pipe_stages): New. (md_begin): Initialize it. (resources_conflict): Use it.
2008-03-032008-03-03 Sterling Augustine <sterling@tensilica.com>Bob Wilson2-1/+7
* config/tc-xtensa.h (RELAX_XTENSA_NONE): New.
2008-03-03gas/H.J. Lu10-0/+97
2008-03-03 Denys Vlasenko <vda.linux@googlemail.com> H.J. Lu <hongjiu.lu@intel.com> PR gas/5543 * read.c (pseudo_set): Don't allow global register symbol. * symbols.c (S_SET_EXTERNAL): Don't allow register symbol global. 2008-03-03 H.J. Lu <hongjiu.lu@intel.com> PR gas/5543 * write.c (write_object_file): Don't allow symbols which were equated to register. Stop if there is an error. gas/testsuite/ 2008-03-03 H.J. Lu <hongjiu.lu@intel.com> PR gas/5543 * gas/i386/i386.exp: Run inval-equ-1 and inval-equ-2. * gas/i386/inval-equ-1.l: New. * gas/i386/inval-equ-1.s: Likewise. * gas/i386/inval-equ-2.l: Likewise. * gas/i386/inval-equ-2.s: Likewise.
2008-03-01gas/testsuite/H.J. Lu5-157/+140
2008-03-01 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/x86-64-branch.s: Add tests for 16-bit near indirect branches. * gas/i386/x86-64-inval.s: Remove tests for 16-bit near indirect branches. * gas/i386/x86-64-branch.d: Updated. * gas/i386/x86-64-inval.l: Likewise. opcodes/ 2008-03-01 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64. * i386-tbl.h: Regenerated.
2008-03-01 * config/tc-ppc.h (struct _ppc_fix_extra): New.Alan Modra3-9/+34
(ppc_cpu): Declare. (TC_FIX_TYPE, TC_INIT_FIX_DATA): Define. * config/tc-ppc.c (ppu_cpu): Make global. (ppc_insert_operand): Add ppu_cpu parameter. (md_assemble): Adjust for above change. (md_apply_fix): Pass tc_fix_data.ppc_cpu to ppc_insert_operand.
2008-02-27 PR 3134Nick Clifton5-1/+31
* h8300.h (h8_opcodes): Add an encoding for a mov.l instruction with a 32-bit displacement but without the top bit of the 4th byte set. * gas/h8300/pr3134.s: New test. * gas/h8300/pr3134.d: Expected disassembly * gas/h8300/h8300.exp: Run the new test. * gas/h8300/h8300-coff.exp: Fix test for COFF based ports to accept h8300-rtemscoff not just h8300-rtems.
2008-02-262008-02-26 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-16/+20
* gas/i386/jump.d: Updated for COFF.
2008-02-23gas/testsuite/H.J. Lu7-133/+290
2008-02-23 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/jump.s: Add tests for far branches. * gas/i386/jump16.s: Likewise. * gas/i386/jump.d: Updated. * gas/i386/jump16.d: Likewise. * gas/i386/x86-64-inval.l: Likewise. * gas/i386/x86-64-inval.s: Add tests for 16-bit near indirect branches. opcodes/ 2008-02-23 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Disallow 16-bit near indirect branches for x86-64. * i386-tbl.h: Regenerated.
2008-02-22 * config/tc-arm.c (do_bx): Only test EF_ARM_EABI_VERSION on ELFNick Clifton2-2/+2
targeted ARM ports, otherwise just skip generating the reloc.
2008-02-22* gas/m68hc11/bug-1825.d: Update to match changes in theNick Clifton6-5/+13
information generated with source-in-disassembly listings. * gas/m68hc11/indexed12.d: Likewise. * gas/m68hc11/insns-dwarf2.d: Likewise. * gas/m68hc11/lbranch-dwarf2.d: Likewise.
2008-02-22 * config/tc-arm.c (do_bx): Only test EF_ARM_EABI_VERSION on ELFNick Clifton2-0/+7
targeted ARM ports.
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