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2024-07-30gas/NEWS, ld/NEWS: Announce LoongArch changes in 2.43Lulu Cai1-0/+3
2024-07-29Updated translations for the bfd, binutils, gas, ld and opcodes directoriesNick Clifton3-6623/+7615
2024-07-26microMIPS: Add MT ASE instruction set supportYunQiang Su7-21/+656
Add the MT ASE instruction operand types and encodings to the microMIPS opcode table and enable the assembly of these instructions in GAS from MIPSr2 onwards. Update the binutils and GAS testsuites accordingly. References: "MIPS Architecture for Programmers, Volume IV-f: The MIPS MT Module for the microMIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00768, Revision 1.12, July 16, 2013 Co-Authored-By: Maciej W. Rozycki <macro@redhat.com>
2024-07-26gas: correct sb_add_char() 2nd parameter typeJan Beulich2-2/+2
It's entirely unclear why size_t was used there; my only guess is copy- and-paste from another of the functions.
2024-07-26gas: drop scrubber state -2Jan Beulich4-48/+50
Instead re-use code handling LEX_IS_TWOCHAR_COMMENT_1ST, thus ensuring that we wouldn't get bogus state transitions: For example, when we're in states 0 or 1, a comment should be no different from whitespace encountered in those states. Plus for e.g. x86 this results in such comments now truly being converted to a blank, as mandated by documentation. Both aspects apparently were a result of blindly (and wrongly) moving to state 3 _before_ consuming the "ungot" blank. Also amend a related comment elsewhere. In the new testcase the .irp is to make visible in the listing all the whitespace that the scrubber inserts / leaves in place.
2024-07-26x86: accept whitespace around prefix separatorJan Beulich4-19/+99
... and prediction suffix comma. Other than documented /**/ comments currently aren't really converted to a single space, at least not for x86 in its most common configurations. That'll be fixed subsequently, at which point blanks may appear where so far none were expected. Furthermore not permitting blanks around these separators wasn't quite logical anyway - such constructs are composite ones, and hence components ought to have been permitted to be separated by whitespace from the very beginning. Furthermore note how, due to the scrubber being overly aggressive in removing whitespace, some similar construct with a prefix were already accepted. Note how certain other checks in parse_insn() can be simplified as a result. While there for the prediction suffix also make checks case-insensitive and check for a proper trailing separator.
2024-07-26x86/APX: optimize certain {nf}-form insns to BMI2 onesJan Beulich8-10/+1503
..., as those leave EFLAGS untouched anyway. That's a shorter encoding, available as long as no eGPR is in use anywhere.
2024-07-20Change version to 2.43.50Nick Clifton2-2132/+2413
2024-07-20Add markers for 2.43 branch/releaseNick Clifton2-0/+6
2024-07-19MIPS/GAS/testsuite: Run the MT ASE test across architecturesMaciej W. Rozycki2-2/+3
Verify that MT ASE instructions assemble and disassemble correctly across the compatible architectures.
2024-07-19MIPS/opcodes: Output thread context registers numerically with MFTR/MTTRMaciej W. Rozycki1-32/+32
We print MFTR and MTTR instructions' thread context register operand in disassembly using the ABI name the register number would correspond to should the targeted register be a general-purpose register. However in most cases it is wrong, because general-purpose registers are only referred when the 'u' and 'sel' operands are 1 and 0 respectively. And even in these cases the MFGPR and MTGPR aliases take precedence over the corresponding generic instruction encodings, so you won't see the valid case to normally trigger. Conversely decoding the thread context register operand numerically is always valid, so switch to using it. Adjust test coverage accordingly.
2024-07-19Sparc: relax gas testsuite whitespace expectationsJan Beulich1-1/+1
In a subsequent change the scrubber is going to be changed to retain further whitespace. Test case expectations generally would better not depend on the specific whitespace treatment by the scrubber, unless of course a test is specifically about it. Adjust relevant test cases to permit blanks where those will subsequently appear.
2024-07-19TilePro: correct macro use in gas testsuiteJan Beulich1-1/+1
Whitespace in macro arguments either needs quoting / parenthesizing to reliably not be mistaken for an argument separator, or respective macro parameters need to be marked as covering all remaining arguments. The latter appears more appropriate (and far less intrusive) here.
2024-07-19MIPS: correct macro use in gas and ld testsuitesJan Beulich16-32/+32
Whitespace in macro arguments either needs quoting / parenthesizing to reliably not be mistaken for an argument separator, or respective macro parameters need to be marked as covering all remaining arguments. The former appears more appropriate here, as the macro parameters already have ":req".
2024-07-19ia64: correct macro use in gas testsuiteJan Beulich1-6/+6
Whitespace in macro arguments either needs quoting / parenthesizing to reliably not be mistaken for an argument separator, or respective macro parameters need to be marked as covering all remaining arguments. The latter appears more appropriate here.
2024-07-19bfin: drop _ASSIGN_BANGJan Beulich2-6/+5
A few testcases demonstrate that "=!" isn't supposed to be an individual token, since "= !" is used in a number of places. So far lexing that to a single token worked because of the scrubber being overly aggressive in removing whitespace. As that's going to change, replace uses by separate ASSIGN and BANG.
2024-07-19bfin: correct macro use in gas testsuiteJan Beulich1-4/+4
Whitespace in macro arguments either needs quoting / parenthesizing to reliably not be mistaken for an argument separator, or respective macro parameters need to be marked as covering all remaining arguments. The latter really isn't an option here.
2024-07-19Arm: correct macro use in gas testsuiteJan Beulich2-2/+2
The way the inner macro invocations are written doesn't quite work as expected (and would actually break subsequently): Due to overly aggressive removal of whitespace by the scrubber, the incoming \sym and \offset arguments actually get concatenated; an empty 3rd argument is being passed to ldrtest2. That just so happened to work as intended; any use of \offset alone would have exposed the problem. Quote the 3rd argument, thus retaining enough whitespace to be independent of scrubber internals.
2024-07-19gas: adjust impossible/bogus M68K/MRI special case when scrubbingJan Beulich1-6/+2
State 1 is uniformly handled further up. And it is highly questionable that in state 10 (i.e. after having seen not only a possible label, but also an opcode), which is about to go away anyway, a line comment char could still be meant to take effect. With the state checking dropped, the immediately preceding logic can then also be simplified.
2024-07-19gas: consistently drop trailing whitespace when scrubbingJan Beulich8-15/+34
From especially the checks for the two separator forms it appears to follow that the construct being touched is about trailing whitespace. In such a case, considering that for many targets ordinary and line comment chars overlap, take into account that line comment chars override ordinary ones in lex[] (logic elsewhere in do_scrub_chars() actually depends on that ordering, and also accounts for this overriding). Plus of course IS_NEWLINE() would better also be consulted. Note also that the DOUBLESLASH_LINE_COMMENTS change should generally have no effect just yet; it's a prereq for a later change but better fits here. Leave respective comments as well, and update documentation to correct which comment form is actually replaced by a single blank (i.e. neither the ones starting with what {,tc_}comment_chars[] has nor the ones starting with what line_comment_chars[] has).
2024-07-19gas: drop tic6x scrubber special caseJan Beulich1-10/+0
Two successive PUT() without a state change in between can't be right: The first PUT() may take the "goto tofull" path, leading to the subsequent character being processed later in the previously set state (1 in this case), rather than the state we were in upon entry to the switch() (13 in this case). However, the original purpose of that logic appears to be to not mistake "|| ^" for "||^". This effect, sadly, looks to not have been achieved. Therefore drop the special case altogether; something that actually achieves the (presumably) intended effect may then be introduced down the road.
2024-07-19gas: pre-init the scrubber's lex[]Jan Beulich1-21/+62
While we can't - unlike an old comment suggests - do this fully, we can certainly do part of this at compile time. Since it's adjacent, also drop the unnecessary forward declaration of process_escape().
2024-07-19x86: accept whitespace inside curly bracesJan Beulich4-5/+73
Other than documented /**/ comments currently aren't really converted to a single space, at least not for x86 in its most common configurations. That'll be fixed subsequently, at which point blanks may appear where so far none were expected. Furthermore not permitting blanks immediately inside curly braces wasn't quite logical anyway - such constructs are composite ones, and hence components ought to have been permitted to be separated by whitespace from the very beginning. With this we also don't care anymore whether the scrubber would remove whitespace around curly braces, so move them from extra_symbol_chars[] to operand_special_chars[]. Note: The new testcase doesn't actually exercise much (if any) of the added code. It is being put in place to ensure that subsequently, when that code actually comes into play, behavior remains the same.
2024-07-19x86: undo '{' being a symbol-start characterJan Beulich2-14/+108
Having it that way has undue side effects, in permitting not only pseudo-prefixes to be parsed correctly, but also permitting odd symbol names which ought to be possible only when quoted. Borrow what other architectures do: Put in place an "unrecognized line" hook to parse off any pseudo prefixes, while using the "start of line" hook to reject ones not actually followed by an insn. For that parsing re-use parse_insn() in yet a slightly different mode (dealing with only pseudo-prefixes). With that, pp may no longer be cleared from init_globals(), but instead needs clearing after a line was fully processed. Since md_assemble() has pretty many return paths, convert that into a local helper, with a trivial wrapper around it. Similarly pp may no longer be updated (by check_register()) when processing anything other than insn operands. To be able to (easily) recognize the case, clear current_templates.start when done with an insn (or with .insn).
2024-07-19x86: split pseudo-prefix state from i386_insnJan Beulich2-198/+199
Subsequently we will want to update that ahead of md_assemble(), with that function needing to take into account such earlier updating. Therefore it'll want resetting separately from i.
2024-07-19x86/APX: add CMPcc/CTESTcc cases to noreg64 testsJan Beulich8-17/+95
This was missed when support for the insns was added. Just like for DATA16, in rex64 neg (%rax) rex64 neg (%r16) rex64 {nf} neg (%rax) it is not logical why the last one shouldn't be permitted. Bypassing that check requires other adjustments, though, to actually properly consume (and then squash) the prefix.
2024-07-19bfin: free the allocated memoryzhangxianting1-0/+2
2024-07-19MIPS/GAS/testsuite: Also verify trap expansions of multiplication macrosMaciej W. Rozycki24-0/+559
Provide 'mul' test variants for trap expansions as requested by the '-trap' command-line option, and run them across all the compatible architectures.
2024-07-19MIPS/GAS/testsuite: Split mul test into 32-bit and 64-bit partsMaciej W. Rozycki26-259/+370
Enable full 32-bit and 64-bit multiplication macro verification, by splitting the 'mul' test into two parts respectively, and run them across all the compatible architectures.
2024-07-19MIPS/GAS/testsuite: Run the mul macro test across architecturesMaciej W. Rozycki11-86/+437
The multiplication macros expand differently based on the ISA chosen, so run the 'mul' macro test across compatible architectures, adopting the 'mul-ilocks' test orphaned by commit 23fce1e31156 ("MIPS16 intermix test failure"), <https://sourceware.org/ml/binutils/2009-01/msg00335.html>, and providing coverage for the expansion variants. Only run from MIPS III up for now and remove the ISA override from the source, so that the 64-bit instructions are covered for individual 64-bit architectures.
2024-07-19MIPS/GAS/testsuite: Also verify trap expansions of division macrosMaciej W. Rozycki20-0/+418
Provide 'div' test variants for trap expansions as requested by the '-trap' command-line option, and run them across all the compatible architectures.
2024-07-19MIPS/GAS/testsuite: Split div test into 32-bit and 64-bit partsMaciej W. Rozycki21-176/+253
Enable full 32-bit and 64-bit division macro verification, by splitting the 'div' test into two parts respectively, and run them across all the compatible architectures.
2024-07-19MIPS/GAS/testsuite: Run the div macro test across architecturesMaciej W. Rozycki10-210/+357
The division macros expand differently depending on the ISA selected, so run the 'div' macro test across compatible architectures, adopting the 'div-ilocks' test orphaned by commit 23fce1e31156 ("MIPS16 intermix test failure"), <https://sourceware.org/ml/binutils/2009-01/msg00335.html>, and providing coverage for the expansion variants. Only run from MIPS III up for now and remove the ISA override from the source, so that the 64-bit instructions are covered for individual 64-bit architectures.
2024-07-19MIPS/GAS: Handle --trap command-line option dynamicallyMaciej W. Rozycki14-15/+663
We have an ISA check for the '--trap' command-line option that reports its incompatibility with the MIPS I architecture. It doesn't prevent trap instructions from being enabled though, so when attempt is made to emit one in an expansion of one of the division or multiplication macros an assertion failure triggers: .../gas/testsuite/gas/mips/brtr-opt.s: Assembler messages: .../gas/testsuite/gas/mips/brtr-opt.s:3: Error: trap exception not supported at ISA 1 .../gas/testsuite/gas/mips/brtr-opt.s:9: Warning: divide by zero .../gas/testsuite/gas/mips/brtr-opt.s:9: Internal error in macro_build at .../gas/config/tc-mips.c:9064. Please report this bug. The same assertion failure triggers without an earlier error message when the initial ISA is compatible with the '--trap', however at the time an attempt is made to emit a trap instruction from a division or multiplication macro the ISA has been changed by a '.set' pseudo-op to an incompatible one. With the way the situations are mishandled it seems unlikely that anyone relies on the current semantics and a sane approach is to decide on the fly according to the currently selected ISA as to whether to emit trap or breakpoint instructions in the case where '--trap' has been used. Change our code to do so then and clarify that in the manual, which is not explicit about how '--trap' is handled with a changing ISA. Mention the change in NEWS too since it's a applies to a user option.
2024-07-19MIPS/GAS/testsuite: Add R10000 CPU architectureMaciej W. Rozycki5-0/+22
Add a fully interlocked MIPS IV CPU so that we can have coverage for MIPS IV instruction sequences with and without instruction separation required for a HI/LO data anti-dependency.
2024-07-19MIPS/GAS/testsuite: Reorder R5900 CPU architecture definitionMaciej W. Rozycki1-3/+3
The R5900 CPU architecture is based on MIPS III, so move it ahead of MIPS IV CPU architecture definitions. No functional change.
2024-07-18gas: aarch64: testsuite: add new tests for SCFIIndu Bhagat59-1/+1501
Similar to the x86_64 testcases, some .s files contain the corresponding CFI directives. This helps in validating the synthesized CFI by running those tests with and without the --scfi=experimental command line option. GAS issues some diagnostics, enabled by default, with --scfi=experimental. The diagnostics have been added with an intent to help user correct inadvertent errors in their hand-written asm. An error is issued when GAS finds that input asm is not amenable to accurate CFI synthesis. The existing scfi-diag-*.s tests in the gas/testsuite/gas/scfi/x86_64 directory test some SCFI diagnostics already: - (#1) "Warning: SCFI: Asymetrical register restore" - (#2) "Error: SCFI: usage of REG_FP as scratch not supported" - (#3) "Error: SCFI: unsupported stack manipulation pattern" - (#4) "Error: untraceable control flow for func 'XXX'" In the newly added aarch64 testsuite, further tests for additional diagnostics have been added: - scfi-diag-1.s in this patch highlights an aarch64-specific diagnostic: (#5) "Warning: SCFI: ignored probable save/restore op with reg offset" Additionally, some testcases are added to showcase the (currently) unsupported patterns, e.g., scfi-unsupported-1.s mov x16, 4384 sub sp, sp, x16 gas/testsuite/: * gas/scfi/README: Update comment to include aarch64. * gas/scfi/aarch64/scfi-aarch64.exp: New file. * gas/scfi/aarch64/ginsn-arith-1.l: New test. * gas/scfi/aarch64/ginsn-arith-1.s: New test. * gas/scfi/aarch64/ginsn-cofi-1.l: New test. * gas/scfi/aarch64/ginsn-cofi-1.s: New test. * gas/scfi/aarch64/ginsn-ldst-1.l: New test. * gas/scfi/aarch64/ginsn-ldst-1.s: New test. * gas/scfi/aarch64/scfi-callee-saved-fp-1.d: New test. * gas/scfi/aarch64/scfi-callee-saved-fp-1.l: New test. * gas/scfi/aarch64/scfi-callee-saved-fp-1.s: New test. * gas/scfi/aarch64/scfi-callee-saved-fp-2.d: New test. * gas/scfi/aarch64/scfi-callee-saved-fp-2.l: New test. * gas/scfi/aarch64/scfi-callee-saved-fp-2.s: New test. * gas/scfi/aarch64/scfi-cb-1.d: New test. * gas/scfi/aarch64/scfi-cb-1.l: New test. * gas/scfi/aarch64/scfi-cb-1.s: New test. * gas/scfi/aarch64/scfi-cfg-1.d: New test. * gas/scfi/aarch64/scfi-cfg-1.l: New test. * gas/scfi/aarch64/scfi-cfg-1.s: New test. * gas/scfi/aarch64/scfi-cfg-2.d: New test. * gas/scfi/aarch64/scfi-cfg-2.l: New test. * gas/scfi/aarch64/scfi-cfg-2.s: New test. * gas/scfi/aarch64/scfi-cfg-3.d: New test. * gas/scfi/aarch64/scfi-cfg-3.l: New test. * gas/scfi/aarch64/scfi-cfg-3.s: New test. * gas/scfi/aarch64/scfi-cfg-4.l: New test. * gas/scfi/aarch64/scfi-cfg-4.s: New test. * gas/scfi/aarch64/scfi-cond-br-1.d: New test. * gas/scfi/aarch64/scfi-cond-br-1.l: New test. * gas/scfi/aarch64/scfi-cond-br-1.s: New test. * gas/scfi/aarch64/scfi-diag-1.l: New test. * gas/scfi/aarch64/scfi-diag-1.s: New test. * gas/scfi/aarch64/scfi-diag-2.l: New test. * gas/scfi/aarch64/scfi-diag-2.s: New test. * gas/scfi/aarch64/scfi-diag-3.l: New test. * gas/scfi/aarch64/scfi-diag-3.s: New test. * gas/scfi/aarch64/scfi-ldrp-1.d: New test. * gas/scfi/aarch64/scfi-ldrp-1.l: New test. * gas/scfi/aarch64/scfi-ldrp-1.s: New test. * gas/scfi/aarch64/scfi-ldrp-2.d: New test. * gas/scfi/aarch64/scfi-ldrp-2.l: New test. * gas/scfi/aarch64/scfi-ldrp-2.s: New test. * gas/scfi/aarch64/scfi-ldstnap-1.d: New test. * gas/scfi/aarch64/scfi-ldstnap-1.l: New test. * gas/scfi/aarch64/scfi-ldstnap-1.s: New test. * gas/scfi/aarch64/scfi-strp-1.d: New test. * gas/scfi/aarch64/scfi-strp-1.l: New test. * gas/scfi/aarch64/scfi-strp-1.s: New test. * gas/scfi/aarch64/scfi-strp-2.d: New test. * gas/scfi/aarch64/scfi-strp-2.l: New test. * gas/scfi/aarch64/scfi-strp-2.s: New test. * gas/scfi/aarch64/scfi-unsupported-1.l: New test. * gas/scfi/aarch64/scfi-unsupported-1.s: New test. * gas/scfi/aarch64/scfi-unsupported-2.l: New test. * gas/scfi/aarch64/scfi-unsupported-2.s: New test.
2024-07-18gas: aarch64: add experimental support for SCFIIndu Bhagat3-0/+999
For synthesizing CFI (SCFI) for hand-written asm, the SCFI machinery in GAS works on the generic GAS insns (ginsns). This patch adds support in the aarch64 backend to create ginsns for a subset of the supported machine instructions. The subset includes the minimal necessary instructions to ensure SCFI correctness: - Any potential register saves and unsaves. Hence, process instructions belonging to a variety of iclasses involving str, ldr, stp, ldp. - Any change of flow instructions. This includes all conditional and unconditional branches, call (bl, blr, etc.) and return. - Most importantly, any instruction that could affect the two registers of interest: REG_SP, REG_FP. This set includes all pre-indexed and post-indexed memory operations, with writeback, on the stack. This set must also include other instructions (e.g., arithmetic insns) where the destination register is one of the afore-mentioned registers. With respect to callee-saved registers in Aarch64, FP/Advanced SIMD registers D8-D15 are included along with the relevant GPRs. Calculating offsets for loads and stores especially for Q registers needs special attention here. As an example, str q8, [sp, #16] On big-endian: STR Qn stores as a 128-bit integer (MSB first), hence, should record D8 as being saved at sp+24 rather than sp+16. On little-endian: should record D8 as being saved at sp+16 D8-D15 are the low 64 bits of Q8-Q15, and of Z8-Z15 if SVE is used; hence, they remain "interesting" for SCFI purposes in such cases. A CFI save slot always represents the low 64 bits, regardless of whether a save occurs on D, Q or Z registers. Currently, the ginsn creation machinery can handle D and Q registers on little-endian and big-endian. Apart from creating ginsn, another key responsibility of the backend is to make sure there are safeguards in place to detect and alert if an instruction of interest may have been skipped. This is done via aarch64_ginsn_unhandled () (similar to the x86 backend). This function , hence, is also intended to alert when future ISA changes may otherwise render SCFI results incorrect, because of missing ginsns for the newly added machine instructions. At this time, becuase of the complexities wrt endianness in handling Z register usage, skip sve_misc opclass altogether for now. The SCFI machinery will error out (using the aarch64_ginsn_unhandled () code path) though if Z register usage affects correctness. The current SCFI machinery does not currently synthesize the PAC-related, aarch64-specific CFI directives: .cfi_b_key_frame. The support for this is planned for near future. SCFI is enabled for ELF targets only. gas/ * config/tc-aarch64-ginsn.c: New file. * config/tc-aarch64.c (md_assemble): Include tc-aarch64-ginsn.c file. Invoke aarch64_ginsn_new. * config/tc-aarch64.h (TARGET_USE_GINSN): Define for SCFI enablement. (TARGET_USE_SCFI): Likewise. (SCFI_MAX_REG_ID): New definition. (REG_FP): Likewise. (REG_LR): Likewise. (REG_SP): Likewise. (SCFI_INIT_CFA_OFFSET): Likewise. (SCFI_CALLEE_SAVED_REG_P): Likewise. (aarch64_scfi_callee_saved_p): New declaration.
2024-07-18gas: scfi: make scfi_state_restore_reg function more preciseIndu Bhagat1-4/+5
When the SCFI machinery detects that a register has been restored from stack, it makes some state changes in the SCFI state object. Prior to the patch, scfi_state_restore_reg () was setting a value of (reg, CFI_IN_REG) for (base, state) respectively. This was causing issues in the cmp_scfi_state () function: - The default state of all (callee-saved) regs at the beginning of function is set to (0, CFI_UNDEFINED). - If a register is saved and restored on some control path, the state of reg is (reg, CFI_IN_REG) on that path. - On another control path where the register was perhaps not used (or saved/restored on stack) remains (0, CFI_UNDEFINED). - The two states should be treated equal, however, at the point in program after the register has been restored. Fix this by resetting the state to (0, CFI_UNDEFINED) in scfi_state_restore_reg (). A testcase (scfi-cfg-4.s) for this is added in a subsequent commit. gas/ * scfi.c (scfi_state_restore_reg): Reset to 0, CFI_UNDEFINED for base, state.
2024-07-18gas: minor reformatting in command line help and docMatthieu Longo3-17/+20
- help message: add a comma between the short and long option - as doc: - brief summary of how to invoke gas: separate [-w] [-x] on a new line as those two options have nothing to do with the warning options. - reordering of the warning options to have the same order as the listing. - no-warn option description: change an "and" to a "or", as it is either the short or long option to use, but not both at the same time. - remove trailing whitespaces.
2024-07-18X86: Update gas/NEWS for Intel APX.Cui, Lili1-1/+1
gas/ChangeLog: * NEWS: Added "APX_F is fully supportted" to gas/NEWS.
2024-07-16gas: scfi: testsuite: refresh the READMEIndu Bhagat1-9/+12
Update some stale text in the README. Add few more notes to guide future maintenance of the testsuite. gas/testsuite/ * gas/scfi/README: Update text.
2024-07-13Revert "MIPS: Use N64 by default for mips*64*-*-linux-gnuabi64"Maciej W. Rozycki2-2/+2
This reverts commit d49f2dd78b08efa4e1ee51f5df5058846c2eb4fa. It was applied unapproved.
2024-07-13Revert "MIPS/GAS: Omit LI 0 for condition trap"Maciej W. Rozycki4-35/+3
This reverts commit bfa257b407270d1c808b31fbd97da779e0fd20d2. It was applied unapproved.
2024-07-12aarch64: Add support for sme2.1 zero instructions.Srinath Parvathaneni6-1/+270
This patch adds support for following sme2.1 zero instructions and the spec is available here [1]. 1. ZERO (single-vector). 2. ZERO (double-vector). 3. ZERO (quad-vector). The VECTOR GROUP symbols VGx2 and VGx4 are optional for the assembler for most of the sme and sve instructions. But for few of the sme2.1 zero instruction variants VECTOR GROUP symbols VGx2 and VGx4 are mandatory. To address this a bit "F_VG_REQ" is introduced in this patch, on setting F_VG_REQ bit in flags of aarch64_opcode forces the assembler to accept instruction operand only having VECTOR GROUP symbols. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en
2024-07-12aarch64: Add support for sme2.1 movaz instructions.Srinath Parvathaneni11-0/+329
This patch adds support for following sme2.1 movaz instructions and the spec is available here [1]. 1. MOVAZ (array to vector, two registers). 2. MOVAZ (array to vector, four registers). 3. MOVAZ (tile to vector, single). [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en
2024-07-12aarch64: Add support for sme2.1 luti2 and luti4 instructions.Srinath Parvathaneni5-0/+288
This patch adds support for following sme2.1 luti2 and luti4 instructions, spec is available here [1] 1. LUTI2 (two registers) strided. 2. LUTI2 (four registers) strided. 3. LUTI4 (two registers) strided. 4. LUTI4 (four registers) strided. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en
2024-07-12x86: drop unnecessary \() from bundle testsJan Beulich3-15/+15
':' isn't permitted in macro parameter names, hence this separator construct isn't necessary at the end of labels. Drop its use in such cases, for being potentially confusing (and hampering readability, even if only a little).
2024-07-12x86/APX: remove two inconsistenciesJan Beulich7-81/+283
As indicated in earlier discussion, permitting GOTTPOFF uniformly for all legacy non-SIMD insns while at the same time restricting to just certain ADD forms when EVEX-encoded is inconsistent. Make promoted insns "equal" to their legacy original ones. Doing that adjustment prevents another inconsistency, too: In data16 neg (%rax) data16 neg (%r16) data16 {nf} neg (%rax) it is not logical why the last one shouldn't be permitted. Bypassing that check requires other adjustments, though, to actually properly consume (and then squash) the data size prefix. While there also add the missing CMP and TEST cases to the test case being modified.
2024-07-12x86/APX: correct TEST/CTESTcc with 1st operand being a memory oneJan Beulich6-8/+33
While they properly inherited D and C, code processing the reversal of operands wasn't updated accordingly (and "reversed" operands also weren't tested anywhere).
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