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2008-03-142008-03-14 Sterling Augustine <sterling@tensilica.com>Bob Wilson2-1/+8
* config/tc-xtensa.h (xtensa_relax_statesE): Update comment for RELAX_LOOP_END_ADD_NOP.
2008-03-13PR gas/5895Nick Clifton5-2/+33
* read.c (s_mexit): Warn if attempting to exit a macro when not inside a macro definition. * gas/macros/exit.s: New test case. * gas/macros/macros.exp: Run the new test, expect it to produce an error result.
2008-03-13bfd/Alan Modra4-216/+222
* Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * po/SRC-POTFILES.in: Regenerate. bfd/doc/ * Makefile.in: Regenerate. binutils/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * configure: Regenerate. gas/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * configure: Regenerate. opcodes/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * configure: Regenerate.
2008-03-092008-03-09 Paul Brook <paul@codesourcery.com>Paul Brook3-0/+9
gas/ * config/tc-arm.c (arm_cpu_option_table): Add cortex-a9. * doc/c-arm.texi: Add cortex-a9.
2008-03-092008-03-09 Paul Brook <paul@codesourcery.com>Paul Brook6-11/+93
bfd/ * elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle new Tag_VFP_arch values. binutils/ * readelf.c (arm_attr_tag_VFP_arch): Add "VFPv3-D16". gas/ * config/tc-arm.c (fpu_vfp_ext_d32): New vairable. (parse_vfp_reg_list, encode_arm_vfp_reg): Use it. (arm_option_cpu_value): Add vfpv3-d16, vfpv2 and vfpv3. (aeabi_set_public_attributes): Handle Tag_VFP_arch=VFPV3-D16. * doc/c-arm.texi: Document new ARM FPU variants. gas/testsuite/ * gas/arm/vfpv3-d16-bad.d: New test. * gas/arm/vfpv3-d16-bad.l: New test. include/opcode/ * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
2008-03-082008-03-07 Paul Brook <paul@codesourcery.com>Paul Brook2-1/+5
bfd/ * elf32-arm.c (elf32_arm_howto_table_1): Fix bitmasks for MOVW and MOVT relocations. (elf32_arm_final_link_relocate): Fix off by one MOVW/MOVT sign extension. (elf32_arm_relocate_section): Handle MOVW and MOVT relocations. Improve safety check for other weird relocations. (elf32_arm_check_relocs): Only set h->needs_plt for branch/call relocations. gas/ * config/tc-arm.c (md_apply_fix): Use correct offset range. ld/testsuite/ * ld-arm/arm-elf.exp (armelftests): Add movw-merge and arm-app-movw. * ld-arm/arm-app-movw.s: New test. * ld-arm/arm-app.r: Update expected output. * ld-arm/movw-merge.d: New test. * ld-arm/movw-merge.s: New test.
2008-03-06 * config/tc-ppc.c (ppc_setup_opcodes): Tidy. Add code to testAlan Modra2-9/+52
for strict ordering of powerpc_opcodes, but disable for now.
2008-03-062008-03-06 Florian Krohm <fkrohm@us.ibm.com>Andreas Krebbel7-48/+60
* s390-opc.c (INSTR_RSL_R0RD): Fix operands. * s390-opc.txt (cmpsc): Duplicate entry removed. (dxr, sqdr, sqer, cxfbr, cdfbr, cefbr, lzer, lzdr, lzxr, cegbr, cdgbr, cxgbr, cegr, cdgr, cxgr, cxfr, cdfr, cefr, fixr, fidr, fier, cu42, cu41): Fix operand format. 2008-03-06 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/esa-g5.d (cdfbr, cdfr, cefbr, cefr, cxfbr, cxfr, dxr, fidr, fier, fixr, lzdr, lzer, lzxr, sqdr, sqer, tp): Fix operand format. * gas/s390/esa-g5.s: Likewise. * gas/s390/zarch-z900.d (cdgbr, cdgr, cegbr, cegr, cxgbr, cxgr): Likewise. * gas/s390/zarch-z900.s: Likewise. * gas/s390/zarch-z9-109.d (cu41, cu42): Remove mask operand. * gas/s390/zarch-z9-109.s: Likewise.
2008-03-052008-03-04 Paul Brook <paul@codesourcery.com>Paul Brook7-24/+98
gas/ * config/tc-arm.c (arm_ext_barrier, arm_ext_msr): New. (arm_ext_v7m): Rename... (arm_ext_m): ... to this. Include v6-M. (do_t_add_sub): Allow narrow low-reg non flag setting adds. (do_t_mrs, do_t_msr, aeabi_set_public_attributes): Use arm_ext_m. (md_assemble): Allow wide msr instructions. (insns): Add classifications for v6-m instructions. (arm_cpu_option_table): Add cortex-m1. (arm_arch_option_table): Add armv6-m. (cpu_arch): Add ARM_ARCH_V6M. Fix numbering of other v6 variants. gas/testsuite/ * gas/arm/archv6m.d: New test. * gas/arm/archv6m.s: New test. * gas/arm/t16-bad.s: Test low register non flag setting add. * gas/arm/t16-bad.l: Update expected output. include/opcode/ * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define. (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags. (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
2008-03-03bfd/Bob Wilson2-1/+11
* xtensa-isa.c (xtensa_isa_num_pipe_stages): Make max_stage static and only compute its value once. gas/ * config/tc-xtensa.c (xtensa_num_pipe_stages): New. (md_begin): Initialize it. (resources_conflict): Use it.
2008-03-032008-03-03 Sterling Augustine <sterling@tensilica.com>Bob Wilson2-1/+7
* config/tc-xtensa.h (RELAX_XTENSA_NONE): New.
2008-03-03gas/H.J. Lu10-0/+97
2008-03-03 Denys Vlasenko <vda.linux@googlemail.com> H.J. Lu <hongjiu.lu@intel.com> PR gas/5543 * read.c (pseudo_set): Don't allow global register symbol. * symbols.c (S_SET_EXTERNAL): Don't allow register symbol global. 2008-03-03 H.J. Lu <hongjiu.lu@intel.com> PR gas/5543 * write.c (write_object_file): Don't allow symbols which were equated to register. Stop if there is an error. gas/testsuite/ 2008-03-03 H.J. Lu <hongjiu.lu@intel.com> PR gas/5543 * gas/i386/i386.exp: Run inval-equ-1 and inval-equ-2. * gas/i386/inval-equ-1.l: New. * gas/i386/inval-equ-1.s: Likewise. * gas/i386/inval-equ-2.l: Likewise. * gas/i386/inval-equ-2.s: Likewise.
2008-03-01gas/testsuite/H.J. Lu5-157/+140
2008-03-01 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/x86-64-branch.s: Add tests for 16-bit near indirect branches. * gas/i386/x86-64-inval.s: Remove tests for 16-bit near indirect branches. * gas/i386/x86-64-branch.d: Updated. * gas/i386/x86-64-inval.l: Likewise. opcodes/ 2008-03-01 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64. * i386-tbl.h: Regenerated.
2008-03-01 * config/tc-ppc.h (struct _ppc_fix_extra): New.Alan Modra3-9/+34
(ppc_cpu): Declare. (TC_FIX_TYPE, TC_INIT_FIX_DATA): Define. * config/tc-ppc.c (ppu_cpu): Make global. (ppc_insert_operand): Add ppu_cpu parameter. (md_assemble): Adjust for above change. (md_apply_fix): Pass tc_fix_data.ppc_cpu to ppc_insert_operand.
2008-02-27 PR 3134Nick Clifton5-1/+31
* h8300.h (h8_opcodes): Add an encoding for a mov.l instruction with a 32-bit displacement but without the top bit of the 4th byte set. * gas/h8300/pr3134.s: New test. * gas/h8300/pr3134.d: Expected disassembly * gas/h8300/h8300.exp: Run the new test. * gas/h8300/h8300-coff.exp: Fix test for COFF based ports to accept h8300-rtemscoff not just h8300-rtems.
2008-02-262008-02-26 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-16/+20
* gas/i386/jump.d: Updated for COFF.
2008-02-23gas/testsuite/H.J. Lu7-133/+290
2008-02-23 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/jump.s: Add tests for far branches. * gas/i386/jump16.s: Likewise. * gas/i386/jump.d: Updated. * gas/i386/jump16.d: Likewise. * gas/i386/x86-64-inval.l: Likewise. * gas/i386/x86-64-inval.s: Add tests for 16-bit near indirect branches. opcodes/ 2008-02-23 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Disallow 16-bit near indirect branches for x86-64. * i386-tbl.h: Regenerated.
2008-02-22 * config/tc-arm.c (do_bx): Only test EF_ARM_EABI_VERSION on ELFNick Clifton2-2/+2
targeted ARM ports, otherwise just skip generating the reloc.
2008-02-22* gas/m68hc11/bug-1825.d: Update to match changes in theNick Clifton6-5/+13
information generated with source-in-disassembly listings. * gas/m68hc11/indexed12.d: Likewise. * gas/m68hc11/insns-dwarf2.d: Likewise. * gas/m68hc11/lbranch-dwarf2.d: Likewise.
2008-02-22 * config/tc-arm.c (do_bx): Only test EF_ARM_EABI_VERSION on ELFNick Clifton2-0/+7
targeted ARM ports.
2008-02-20Correct year.H.J. Lu1-1/+1
2008-02-202008-02-20 Paul Brook <paul@codesourcery.com>Paul Brook8-5/+266
ld/ * emultempl/armelf.em (OPTION_FIX_V4BX_INTERWORKING): Define. (PARSE_AND_LIST_LONGOPTS): Add fix-v4bx-interworking. (PARSE_AND_LIST_OPTIONS): Ditto. (PARSE_AND_LIST_ARGS_CASES): Handle OPTION_FIX_V4BX_INTERWORKING. * emulparams/armelf.sh (OTHER_TEXT_SECTIONS): Add .v4_bx. * emulparams/armelf_linux.sh (OTHER_TEXT_SECTIONS): Ditto. * emulparams/armnto.sh (OTHER_TEXT_SECTIONS): Ditto. * ld.texinfo: Document --fix-v4bx-interworking. ld/testsuite/ * ld-arm/armv4-bx.d: New test. * ld-arm/armv4-bx.s: New test. * ld-arm/arm.ld: Add .v4bx. * ld-arm/arm-elf.exp: Add armv4-bx. gas/testsuite/ * gas/arm/thumb.d: Exclude EABI targets. * gas/arm/arch4t.d: Exclude EABI targts. * gas/arm/v4bx.d: New test. * gas/arm/v4bx.s: New test. * gas/arm/thumb-eabi.d: New test. * gas/arm/arch4t-eabi.d: New test. gas/ * config/tc-arm.c (fix_v4bx): New variable. (do_bx): Generate V4BX relocations. (md_assemble): Allow bx on v4 codes when fix_v4bx. (md_apply_fix): Handle BFD_RELOC_ARM_V4BX. (tc_gen_reloc): Ditto. (OPTION_FIX_V4BX): Define. (md_longopts): Add fix-v4bx. (md_parse_option): Handle OPTION_FIX_V4BX. (md_show_usage): Document --fix-v4bx. * doc/c-arm.texi: Document --fix-v4bx. bfd/ * reloc.c: Add BFD_RELOC_ARM_V4BX. * elf32-arm.c (elf32_arm_reloc_map): Add BFD_RELOC_ARM_V4BX. (ARM_BX_GLUE_SECTION_NAME, ARM_BX_GLUE_SECTION_NAME): Define. (elf32_arm_link_hash_table): Add bx_glue_size and bx_glue_offset. Update comment for fix_v4bx. (elf32_arm_link_hash_table_create): Zero bx_glue_size and bx_glue_offset. (ARM_BX_VENEER_SIZE, armbx1_tst_insn, armbx2_moveq_insn, armbx3_bx_insn): New. (bfd_elf32_arm_allocate_interworking_sections): Allocate BX veneer section. (bfd_elf32_arm_add_glue_sections_to_bfd): Ditto. (bfd_elf32_arm_process_before_allocation): Record BX veneers. (record_arm_bx_glue, elf32_arm_bx_glue): New functions. (elf32_arm_final_link_relocate): Handle BX veneers. (elf32_arm_output_arch_local_syms): Output mapping symbol for .v4_bx. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate.
2008-02-182008-02-18 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-4/+37
* cfi/cfi.exp (gas_x86_64_check): New. (gas_x86_32_check): Likewise. Run 32bit and 64bit tests for x86 targets if they are supportd.
2008-02-182008-02-18 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-4/+11
* doc/c-i386.texi: Update -march= and .arch.
2008-02-18 * config/tc-mn10300.c (has_known_symbol_location): New function.Nick Clifton2-11/+36
Do not regard weak symbols as having a known location. (md_estimate_size_before_relax): Use new function. (md_pcrel_from): Do not compute a pcrel against a weak symbol.
2008-02-18gas/Jan Beulich8-0/+232
2008-02-18 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (match_template): Disallow 'l' suffix when currently selected CPU has no 32-bit support. (parse_real_register): Do not return registers not available on currently selected CPU. gas/testsuite/ 2008-02-18 Jan Beulich <jbeulich@novell.com> * gas/i386/att-regs.s, gas/i386/att-regs.d, gas/i386/intel-regs.s, gas/i386/intel-regs.d: New. * gas/i386/i386.exp: Run new tests.
2008-02-172008-02-16 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-9/+12
* config/tc-i386.c (process_immext): Fix format.
2008-02-16gas/H.J. Lu2-49/+60
2008-02-16 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (inoutportreg): New. (process_immext): New. (md_assemble): Use it. (update_imm): Use imm16 and imm32s. (i386_att_operand): Use inoutportreg. opcodes/ 2008-02-16 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG. * i386-init.h: Regenerated.
2008-02-142008-02-14 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-87/+165
* config/tc-i386.c (operand_type_all_zero): New. (operand_type_set): Likewise. (operand_type_equal): Likewise. (cpu_flags_all_zero): Likewise. (cpu_flags_set): Likewise. (cpu_flags_equal): Likewise. (UINTS_ALL_ZERO): Removed. (UINTS_SET): Likewise. (UINTS_CLEAR): Likewise. (UINTS_EQUAL): Likewise. (cpu_flags_match): Updated. (smallest_imm_type): Likewise. (set_cpu_arch): Likewise. (md_assemble): Likewise. (optimize_imm): Likewise. (match_template): Likewise. (process_suffix): Likewise. (update_imm): Likewise. (process_drex): Likewise. (process_operands): Likewise. (build_modrm_byte): Likewise. (i386_immediate): Likewise. (i386_displacement): Likewise. (i386_att_operand): Likewise. (parse_real_register): Likewise. (md_parse_option): Likewise. (i386_target_format): Likewise.
2008-02-14 PR gas/5712Nick Clifton5-0/+25
* config/tc-arm.c (s_arm_unwind_save): Advance the input line pointer past the comma after parsing a floating point register name. * gas/arm/fp-save.s: New test. * gas/arm/fp-save.d: Expected disassembly.
2008-02-14 PR gas/2626Nick Clifton2-2/+16
* avr.h (AVR_ISA_2xxe): Define. * config/tc-avr.c (mcu_types): Change the ISA tyoe of the attiny26 to AVR_ISA_2xxe. (avr_operand): Disallow post-increment addressing in the lpm instruction for the attiny26.
2008-02-13 * gas/mips/branch-misc-2pic-64.d (#name): Have a unique nameAdam Nemet2-1/+6
different from the branch-misc-2-64.d test.
2008-02-13gas/Jan Beulich5-17/+43
2008-02-13 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (parse_real_register): Don't return 'FLAT' if not in Intel mode. (i386_intel_operand): Ignore segment overrides in immediate and offset operands. (intel_e11): Range-check i.mem_operands before use as array index. Filter out FLAT for uses other than as segment override. (intel_get_token): Remove broken promotion of "FLAT:" to mean "offset FLAT:". gas/testsuite/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * gas/i386/intelok.s: Replace invalid offset expression with valid ones. * gas/i386/x86_64.s: Likewise. opcodes/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * i386-opc.h (RegFlat): New. * i386-reg.tbl (flat): Add. * i386-tbl.h: Re-generate.
2008-02-13gas/Jan Beulich9-38/+59
2008-02-13 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (intel_e09): Also special-case 'bound'. gas/testsuite/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * gas/i386/intelbad.s, gas/i386/intelok.s: Add 'bound' tests. * gas/i386/intelbad.l, gas/i386/intelok.l, gas/i386/intelok.e, gas/i386/opcode-intel.d: Adjust. opcodes/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * i386-dis.c (a_mode): New. (cond_jump_mode): Adjust. (Ma): Change to a_mode. (intel_operand_size): Handle a_mode. * i386-opc.tbl: Allow Dword and Qword for bound. * i386-tbl.h: Re-generate.
2008-02-13gas/Jan Beulich9-92/+484
2008-02-13 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (allow_pseudo_reg): New. (parse_real_register): Check for NULL just once. Allow all register table entries when allow_pseudo_reg is non-zero. Don't allow any registers without type when allow_pseudo_reg is zero. (tc_x86_regname_to_dw2regnum): Replace with ... (tc_x86_parse_to_dw2regnum): ... this. (tc_x86_frame_initial_instructions): Adjust for above change. * config/tc-i386.h (tc_regname_to_dw2regnum): Remove. (tc_parse_to_dw2regnum): New. (tc_x86_regname_to_dw2regnum): Replace with ... (tc_x86_parse_to_dw2regnum): ... this. * dw2gencfi.c (tc_parse_to_dw2regnum): New, broken out of ... (cfi_parse_reg): ... this. Use tc_parse_to_dw2regnum. Adjust error handling. gas/testsuite/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * gas/cfi/cfi-i386.s: Add code testing use of all registers. Fix a few comments. * gas/cfi/cfi-x86_64.s: Likewise. * gas/cfi/cfi-i386.d, gas/cfi/cfi-x86_64.d: Adjust. opcodes/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * i386-gen.c (process_i386_registers): Process new fields. * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to unsigned char. Add dw2_regnum and Dw2Inval. * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo register names. * i386-tbl.h: Re-generate.
2008-02-122002-02-12 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu4-3/+50
* gas/i386/i386.exp: Run x86-64-arch-2 instead of x86-64-arch-10. * gas/i386/x86-64-arch-10.d: Removed. * gas/i386/x86-64-arch-2.d: New. * gas/i386/x86-64-arch-2.s: Likewise.
2008-02-122008-02-12 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-1/+5
* gas/i386/x86-64-xsave.d: Remove prefix.
2008-02-12* config/tc-tic4x.c (tic4x_insn_insert): Add const qualifier toNick Clifton3-13/+19
argument. (tic4x_insn_add): Likewise. (md_begin): Drop cast that was discarding a const qualifier. * config/tc-d30v.c (get_reloc): Add const qualifier to op argument. (build_insn): Drop cast that was discarding a const qualifier.
2008-02-12gas/H.J. Lu11-60/+97
2008-02-11 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add .xsave. (md_show_usage): Add .xsave. * doc/c-i386.texi: Add xsave to -march=. gas/testsuite/ 2008-02-11 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10.s: Add xgetbv. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-10.d: Likewise. opcodes/ 2008-02-11 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS. * i386-init.h: Updated.
2008-02-12gas/testsuite/H.J. Lu8-0/+102
2002-02-11 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run xsave, xsave-intel, x86-64-xsave and x86-64-xsave-intel. * gas/i386/x86-64-xsave-intel.d: New file. * gas/i386/x86-64-xsave.d: Likewise. * gas/i386/x86-64-xsave.s: Likewise. * gas/i386/xsave-intel.d: Likewise. * gas/i386/xsave.d: Likewise. * gas/i386/xsave.s: Likewise. opcodes/ 2008-02-11 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flags): Add CpuXsave. * i386-opc.h (CpuXsave): New. (Cpu64): Updated. (i386_cpu_flags): Add cpuxsave. * i386-dis.c (MOD_0FAE_REG_4): New. (RM_0F01_REG_2): Likewise. (MOD_0FAE_REG_5): Updated. (RM_0F01_REG_3): Likewise. (reg_table): Use MOD_0FAE_REG_4. (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated for xrstor. (rm_table): Add RM_0F01_REG_2. * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2008-02-07 * read.c (s_weakref): Don't pass unadorned NULL to concat.Alan Modra3-4/+10
* config/tc-i386.c (set_cpu_arch, md_parse_option): Likewise.
2008-02-06 * gas/mips/mips.exp: Invoke the tests smartmips, mips32-dsp,Adam Nemet7-10/+21
mips32-dspr2, mips64-dsp and mips32-mt with run_dump_test instead of run_dump_test_arches. * gas/mips/smartmips.d: Pass -mips32. * gas/mips/mips64-dsp.d: Pass -mips64r2. * gas/mips/mips32-dsp.d: Pass -mips32r2. * gas/mips/mips32-dspr2.d: Likewise. * gas/mips/mips32-mt.d: Likewise.
2008-02-052008-02-05 Sterling Augustine <sterling@tensilica.com>Bob Wilson2-21/+38
* config/tc-xtensa.c (relax_frag_immed): Change internal consistency checks into assertions. When relaxation produces an operation that does not fit in the current FLIX instruction, make sure that the operation is relaxed as needed to account for being placed following the current instruction.
2008-02-04bfd/H.J. Lu2-0/+15
2008-02-04 Kai Tietz <kai.tietz@onevision.com> H.J. Lu <hongjiu.lu@intel.com> PR 5715 * warning.m4: Enable -Wno-format by default when using gcc on mingw. * configure: Regenerated. binutils/ 2008-02-04 H.J. Lu <hongjiu.lu@intel.com> PR 5715 * configure: Regenerated. gas/ 2008-02-04 H.J. Lu <hongjiu.lu@intel.com> PR 5715 * configure: Regenerated. ld/ 2008-02-04 H.J. Lu <hongjiu.lu@intel.com> PR 5715 * configure: Regenerated. opcodes/ 2008-02-04 H.J. Lu <hongjiu.lu@intel.com> PR 5715 * configure: Regenerated.
2008-02-04 * config/tc-mips.c (mips_cpu_info_table): Add Octeon.Adam Nemet2-0/+7
2008-02-04 * gas/mips/mips.exp: Call mips_arch_create for Octeon. InvokeAdam Nemet4-0/+28
Octeon tests. * gas/mips/octeon.s, gas/mips/octeon.d: New test.
2008-02-012008-01-31 Marc Gauthier <marc@tensilica.com>Bob Wilson6-4/+14
bfd/ * config.bfd (xtensa*-*-*): Recognize processor variants. gas/ * configure.tgt (xtensa*-*-*): Recognize processor variants. gas/testsuite/ * gas/all/gas.exp: Recognize Xtensa processor variants. * gas/elf/elf.exp: Likewise. * gas/lns/lns.exp: Likewise. ld/ * configure.tgt (xtensa*-*-*): Recognize processor variants. ld/testsuite/ * ld-elf/merge.d: Recognize Xtensa processor variants. * ld-xtensa/coalesce.exp: Likewise. * ld-xtensa/lcall.exp: Likewise.
2008-01-28binutils/H.J. Lu14-39/+60
2008-01-28 H.J. Lu <hongjiu.lu@intel.com> * dwarf.c: Include "elf/common.h". (eh_addr_size): Changed to int. (dwarf_regnames_i386): New. (dwarf_regnames_x86_64): Likewise. (dwarf_regnames): Likewise. (dwarf_regnames_count): Likewise. (init_dwarf_regnames): Likewise. (regname): Likewise. (frame_display_row): Properly support different address size. Call regname to get register name. (display_debug_frames): Call regname to get register name. Display DW_CFA_def_cfa_register as DW_CFA_def_cfa_register instead of DW_CFA_def_cfa_reg. * dwarf.h (init_dwarf_regnames): New. * objdump.c: Include "elf-bfd.h". (dump_dwarf): Call init_dwarf_regnames on ELF input. * readelf.c (guess_is_rela): Change argument to int. (parse_args): Remove the undocumented upper case options for -wX. (process_file_header): Call init_dwarf_regnames if do_dwarf_register is true. gas/testsuite/ 2008-01-28 H.J. Lu <hongjiu.lu@intel.com> * gas/cfi/cfi-alpha-1.d: Replace DW_CFA_def_cfa_reg with DW_CFA_def_cfa_register. * gas/cfi/cfi-alpha-3.d: Likewise. * gas/cfi/cfi-hppa-1.d: Likewise. * gas/cfi/cfi-i386.d: Likewise. * gas/cfi/cfi-m68k.d: Likewise. * gas/cfi/cfi-mips-1.d: Likewise. * gas/cfi/cfi-sh-1.d: Likewise. * gas/cfi/cfi-sparc-1.d: Likewise. * gas/cfi/cfi-sparc64-1.d: Likewise. * gas/cfi/cfi-x86_64.d: Likewise. * gas/cfi/cfi-common-1.d: Updated for i386/x86-64 register names. * gas/cfi/cfi-common-2.d: Likewise. * gas/cfi/cfi-common-5.d: Likewise. * gas/cfi/cfi-i386.d: Likewise. * gas/cfi/cfi-x86_64.d: Likewise. ld/testsuite/ 2008-01-28 H.J. Lu <hongjiu.lu@intel.com> * ld-elf/eh1.d: Replace DW_CFA_def_cfa_reg with DW_CFA_def_cfa_register. Updated for i386/x86-64 register names. * ld-elf/eh2.d: Likewise. * ld-elf/eh3.d: Likewise. * ld-elf/eh4.d: Likewise. * ld-elf/eh5.d: Likewise.
2008-01-25Add mingw I64 support for printing long and long long valuesNick Clifton2-0/+10
2008-01-25 * doc/c-xtensa.texi (Xtensa Syntax): Clarify handling of opcodes thatBob Wilson2-7/+12
can only be encoded in FLIX instructions but are not specified as such. (Xtensa Automatic Alignment): Remove obsolete comment about debugging labels.
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