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AgeCommit message (Expand)AuthorFilesLines
2016-10-06Refine .cfi_sections check to only consider compact eh_frameMatthew Fortune5-1/+42
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra37-18/+193
2016-10-06-Wimplicit-fallthrough noreturn fixesAlan Modra2-1/+5
2016-10-06-Wimplicit-fallthrough error fixesAlan Modra9-10/+28
2016-10-06bison warning fixesAlan Modra3-2/+7
2016-09-30[AArch64] PR target/20553, fix opcode mask for SIMD multiply by elementJiong Wang3-0/+22
2016-09-29Add .cfi_val_offset GAS command.Andreas Krebbel6-0/+76
2016-09-29Disallow 3-operand cmp[l][i] for ppc64Alan Modra4-4/+12
2016-09-26tc-xtensa.c: fixup xg_reverse_shift_count typoTrevor Saunders2-1/+6
2016-09-26When building target binaries, ensure that the warning flags selected for the...Vlad Zakharov4-6/+58
2016-09-26PowerPC .gnu.attributesAlan Modra2-0/+29
2016-09-22Remove legacy basepri_mask MRS/MSR special regThomas Preud'homme2-1/+5
2016-09-21[AArch64] Print spaces after commas in addressesRichard Sandiford16-9612/+9633
2016-09-21[AArch64] Use "must" rather than "should" in error messagesRichard Sandiford6-80/+90
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford11-69/+228
2016-09-21Fix misplaced ChangeLogRichard Sandiford2-11/+15
2016-09-21[AArch64][SVE 32/32] Add SVE testsRichard Sandiford15-0/+79428
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford3-1/+27
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford2-0/+11
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford2-3/+44
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford2-0/+32
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford2-15/+68
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford2-23/+237
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford2-1/+49
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford2-0/+71
2016-09-21[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predicationRichard Sandiford2-4/+61
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford2-31/+148
2016-09-21[AArch64][SVE 20/32] Add support for tied operandsRichard Sandiford2-0/+10
2016-09-21[AArch64][SVE 13/32] Add an F_STRICT flagRichard Sandiford2-4/+6
2016-09-21[AArch64][SVE 12/32] Remove boolean parameters from parse_address_mainRichard Sandiford4-24/+57
2016-09-21[AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64 interfaceRichard Sandiford5-339/+371
2016-09-21[AArch64][SVE 10/32] Move range check out of parse_aarch64_imm_floatRichard Sandiford2-8/+11
2016-09-21[AArch64][SVE 09/32] Improve error messages for invalid floatsRichard Sandiford4-6/+34
2016-09-21[AArch64][SVE 08/32] Generalise aarch64_double_precision_fmovableRichard Sandiford2-33/+37
2016-09-21[AArch64][SVE 07/32] Replace hard-coded uses of REG_TYPE_R_Z_BHSDQ_VRichard Sandiford2-22/+43
2016-09-21[AArch64][SVE 06/32] Generalise parse_neon_reg_listRichard Sandiford2-5/+15
2016-09-21[AArch64][SVE 05/32] Rename parse_neon_type_for_operandRichard Sandiford2-2/+8
2016-09-21[AArch64][SVE 04/32] Rename neon_type_el to vector_type_elRichard Sandiford2-16/+29
2016-09-21[AArch64][SVE 03/32] Rename neon_el_type to vector_el_typeRichard Sandiford2-4/+12
2016-09-21[AArch64][SVE 01/32] Remove parse_neon_operand_typeRichard Sandiford2-27/+9
2016-09-16[ARC] Disassemble correctly extension instructions.Claudiu Zissulescu3-0/+27
2016-09-15gas: run the sparc test dcti-couples-v9 only in ELF targets.Jose E. Marchesi2-1/+7
2016-09-14Modify POWER9 support to match final ISA 3.0 documentation.Peter Bergner3-65/+19
2016-09-14gas: improve architecture mismatch diagnostics in sparcJose E. Marchesi2-1/+6
2016-09-14gas: detect DCTI couples in sparcJose E. Marchesi11-18/+133
2016-09-14[ARC] Fix parsing dtpoff relocation expression.Claudiu Zissulescu4-1/+30
2016-09-12S/390: Add alternate processor names.Andreas Krebbel4-29/+70
2016-09-12S/390: Fix facility bit default.Andreas Krebbel2-1/+8
2016-09-12S/390: Fix kmctr instruction type.Patrick Steuer2-1/+5
2016-09-08Allow PROCESSOR_IAMCU for Intel MCUH.J. Lu2-1/+6
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