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2023-12-25LoongArch: Add new relocs and macro for TLSDESC.Lulu Cai1-1/+13
2023-12-22nios2: fix .text/.data interaction with .previousJan Beulich1-2/+2
2023-12-22hppa/ELF: fix .text/.data interaction with .previousJan Beulich1-4/+15
2023-12-22RISC-V: drop .bss overrideJan Beulich2-14/+0
2023-12-22x86-64: refuse "high" 8-bit regs with .insn and VEX/XOP/EVEX encodingsJan Beulich1-0/+10
2023-12-22x86: properly respect rex/{rex}Jan Beulich6-62/+98
2023-12-22LoongArch: Add support for the third expression of .align for R_LARCH_ALIGNmengqinggang4-27/+47
2023-12-20s390: Add suffix to conditional branch instruction descriptionsJens Remus2-0/+4
2023-12-20s390: Optionally print instruction description in disassemblyJens Remus3-0/+28
2023-12-19aarch64: Add FEAT_ITE supportAndrea Corallo6-0/+20
2023-12-19aarch64: Add FEAT_ECBHB supportAndrea Corallo3-2/+13
2023-12-19aarch64: Add FEAT_SPECRES2 supportAndrea Corallo6-0/+25
2023-12-19x86: Remove the restriction for size of the mask register in AVX10Haochen Jiang3-231/+30
2023-12-18LoongArch: Add call36 and tail36 pseudo instructions for medium code modelmengqinggang2-2/+10
2023-12-18LoongArch: Add new relocation R_LARCH_CALL36mengqinggang3-1/+26
2023-12-15arm: reformat -march option section in gas documentationMatthieu Longo1-110/+129
2023-12-15aarch64: Enable Cortex-X3 CPUMatthieu Longo4-0/+11
2023-12-15arm: document -march=armv9.[123]-a binutils optionsMatthieu Longo1-0/+3
2023-12-15x86: last-insn recording should be per-subsectionJan Beulich5-0/+77
2023-12-15ELF: reliably invoke md_elf_section_change_hook()Jan Beulich1-11/+18
2023-12-15ELF: drop "push" parameter from obj_elf_change_section()Jan Beulich9-24/+34
2023-12-15x86: don't needlessly override .bssJan Beulich1-8/+5
2023-12-15revert "x86: allow 32-bit reg to be used with U{RD,WR}MSR"Jan Beulich1-4/+4
2023-12-15x86: fold assembly dialect attributesJan Beulich2-5/+5
2023-12-15x86: Intel syntax implies Intel mnemonicsJan Beulich8-54/+30
2023-12-15Arm64: fix build for certain gcc versionsJan Beulich1-3/+3
2023-12-14RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.Jin Ma2-3/+3
2023-12-13Make const_1_mode print $1 in AT&T syntaxCui, Lili13-128/+128
2023-12-13Clean base_reg and assign correct values to regs for input_output_operand (%dx).Cui, Lili1-0/+2
2023-12-12Fix whitespace snafu in tc-riscv.cNick Clifton1-5/+5
2023-12-12RISC-V: Emit R_RISCV_RELAX for the la/lga pseudo instructionRui Ueyama3-0/+26
2023-12-12RISC-V: Resolve PCREL_HI20/LO12_I/S fixups with local symbols while `-mno-relax'Lifang Xia5-0/+187
2023-12-11LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1">mengqinggang2-0/+15
2023-12-11RISC-V/gas: Clarify the definition of `relaxable' in md_apply_fixNelson Chu1-1/+1
2023-12-01gas: drop unused fields from struct segment_info_structJan Beulich2-12/+1
2023-12-01x86: adjust NOP generation after potential non-insnJan Beulich2-1/+13
2023-12-01x86: i386_cons_align() badly affects diagnosticsJan Beulich3-20/+3
2023-12-01gas: no md_cons_align() for .nop{,s}Jan Beulich4-9/+17
2023-12-01x86: suppress optimization after potential non-insnJan Beulich1-0/+5
2023-12-01x86: last-insn recording should be per-sectionJan Beulich6-58/+116
2023-12-01x86: allow 32-bit reg to be used with U{RD,WR}MSRJan Beulich1-4/+4
2023-12-01RISC-V: Update gas/NEWS for RISC-V vendor extension news.Nelson Chu1-1/+3
2023-12-01RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0Nelson Chu5-0/+147
2023-12-01RISC-V: Zv*: Add support for Zvkb ISA extensionChristoph Müllner6-58/+48
2023-11-30MIPS/GAS: Add -march=loongson2f to loongson-2f-3 testYunQiang Su1-1/+1
2023-11-30MIPS: Set r6 as default arch if vendor is imgYunQiang Su4-2/+14
2023-11-30gas: support double-slash line comments in BPF assemblyJose E. Marchesi9-2/+57
2023-11-28gas: add NEWS entry for change of comment syntax in BPF assemblerJose E. Marchesi2-0/+9
2023-11-28gas: change meaning of ; in the BPF assemblerJose E. Marchesi12-35/+57
2023-11-28testsuite: Clean up .allow_index_reg in i386 testsHaochen Jiang234-574/+350
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