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AgeCommit message (Expand)AuthorFilesLines
2018-04-04i386: Clear vex instead of vex.evexH.J. Lu3-0/+14
2018-03-30Make power8 the default cpu when assembling for 64-bit little endian targets.Peter Bergner2-1/+11
2018-03-28[1/2][GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSLE_LDST8/16/32/64_TPREL_LO12 supp...Renlin Li26-6/+297
2018-03-28x86: drop VecESizeJan Beulich8-14/+42
2018-03-28x86: convert broadcast insn attribute to booleanJan Beulich4-25/+332
2018-03-28x86: fold to-scalar-int conversion insnsJan Beulich2-2/+11
2018-03-28x86: don't show suffixes for to-scalar-int conversion insnsJan Beulich3-16/+22
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton4-0/+67
2018-03-22x86: use local variable in check_VecOperands()Jan Beulich2-7/+13
2018-03-22ix86: allow HLE store of accumulator to absolute addressJan Beulich5-0/+25
2018-03-22x86: fix swapped operand handling for BNDMOVJan Beulich6-0/+31
2018-03-22x86/Intel: fix fallout from earlier template foldingJan Beulich5-2/+244
2018-03-22x86: fold a few XOP templatesJan Beulich5-4/+150
2018-03-19Updated Spanish translation for the bfd/ sub-directory, and updated Ukranian ...Nick Clifton2-2/+6
2018-03-16RISC-V: Emit better warning for unknown CSR.Jim Wilson5-6/+26
2018-03-14Missing testcase files for last commit.Jim Wilson2-0/+90
2018-03-14RISC-V: Add .insn support.Jim Wilson3-27/+673
2018-03-13Updated Russian and Brazilian Portuguese translations.Nick Clifton2-1027/+1247
2018-03-09x86: Encode EVEX instructions with VEX128 if possibleH.J. Lu4-25/+33
2018-03-09x86: Strip whitespace in check_VecOperationsH.J. Lu4-2/+15
2018-03-08x86: Optimize with EVEX128 encoding for AVX512VLH.J. Lu13-56/+459
2018-03-08x86-64: Also optimize "clr reg64"H.J. Lu4-7/+23
2018-03-08x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu10-54/+44
2018-03-08x86: fold several AVX512VL templatesJan Beulich2-6/+47
2018-03-08x86: fold certain AVX512 rotate and shift templatesJan Beulich2-3/+9
2018-03-08x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIXJan Beulich3-43/+32
2018-03-08x86: correct operand size match checks for BMI/BMI2 insnsJan Beulich5-7/+64
2018-03-08x86: fold redundant expressions in process_suffix()Jan Beulich2-20/+18
2018-03-08x86: simplify result processing of cpu_flags_match()Jan Beulich2-24/+21
2018-03-08x86: add GFNI, VAES, and VPCLMUL checking to cpu_flags_match()Jan Beulich19-2/+177
2018-03-08x86: change AVX512VL handling in cpu_flags_match()Jan Beulich2-11/+9
2018-03-08x86: drop CPU_FLAGS_32BIT_MATCHJan Beulich2-5/+10
2018-03-08x86: simplify AVX checks in cpu_flags_match()Jan Beulich2-22/+14
2018-03-08x86: avoid cpu_flags_match() bogusly setting CPU_FLAGS_ARCH_MATCHJan Beulich2-6/+5
2018-03-08x86: extend SSE check to PCLMULQDQ, AES, and GFNI insnsJan Beulich16-126/+88
2018-03-08x86: drop FloatDJan Beulich2-7/+12
2018-03-08x86/Intel: correct disassembly of fsub*/fdiv*Jan Beulich3-0/+716
2018-03-08x86: adjust 4-XMM-register-group related warningJan Beulich4-30/+39
2018-03-08x86: bogus VMOVD with 64-bit operands should only allow for registersJan Beulich4-6/+6
2018-03-08x86: fold AVX vcvtpd2ps memory formsJan Beulich2-10/+42
2018-03-08Really remove unnecessary power9 group terminating nopAlan Modra2-4/+8
2018-03-08Remove unnecessary power9 group terminating nopAlan Modra2-10/+13
2018-03-07x86: Rewrite NOP generation for fill and alignmentH.J. Lu65-3363/+2392
2018-03-07XCOFF disassemblerAlan Modra4-74/+81
2018-03-02[ARM] Fix NULL dereference of march_ext_optThomas Preud'homme2-1/+6
2018-03-01[ARM] Clean up selection of feature bitsThomas Preud'homme2-111/+171
2018-03-01x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128H.J. Lu6-2/+121
2018-03-01Add missing translations to ALL_LINGUASAlan Modra3-2/+7
2018-02-27gas: Rename .nop directive to .nopsH.J. Lu26-44/+77
2018-02-27x86: Add -O[2|s] assembler command-line optionsH.J. Lu21-2/+773
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