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AgeCommit message (Expand)AuthorFilesLines
2018-06-27gas object file locationsAlan Modra3-112/+117
2018-06-26Updated translations.Nick Clifton2-2993/+3074
2018-06-26Fix the MSP430 assembler's parsing of register names.Nick Clifton3-133/+150
2018-06-24Regenerate configure and pot files with updated binutils version number.Nick Clifton3-2957/+2616
2018-06-24Add 2.30 branch notes to ChangeLogs and NEWS files.Nick Clifton2-0/+7
2018-06-22Correct negs aliasing on AArch64.Tamar Christina3-0/+180
2018-06-21Regen doc/Makefile.inAlan Modra3-4/+9
2018-06-20Change the ARM assembler's ADR and ADRl pseudo-ops so that they will only set...Nick Clifton7-6/+44
2018-06-20RISC-V: Accept constant operands in la and llaSebastian Huber9-0/+103
2018-06-19Bump to autoconf 2.69 and automake 1.15.1Simon Marchi10-2532/+2217
2018-06-14MIPS: Add Global INValidate ASE supportFaraz Shahbazker15-0/+125
2018-06-14MIPS: Add CRC ASE support (ChangeLog)Maciej W. Rozycki1-0/+1
2018-06-13MIPS: Add CRC ASE supportScott Egerton20-0/+232
2018-06-11MIPS/GAS: Correct `-O0' and `-O' option help, add `-O1' and `-O2'Maciej W. Rozycki2-2/+8
2018-06-08[arm][gas] Add support for Arm Cortex-A76kyrtka013-0/+9
2018-06-08[AArch64][gas] Add support for Arm Cortex-A76kyrtka013-0/+9
2018-06-08Prevent undefined FMOV instructions being accepted by the AArch64 assembler.Egeyar Bagcioglu5-1/+101
2018-06-07Fix AArch64 unintialized variable which can cause diagnostic failures.Tamar Christina2-0/+8
2018-06-06Update the AArch64 assembler to note that the Qualcomm Saphira cpu supports A...Sameera Deshpande2-1/+6
2018-06-05Another s12z regenAlan Modra2-1/+5
2018-06-04xtensa: add separate property sections optionMax Filippov2-1/+32
2018-06-01Bump version number to 2.30.52H.J. Lu2-10/+14
2018-06-01Drop view when consuming line infoAlexandre Oliva2-0/+5
2018-06-01x86: don't emit REX.W for SLDT and STRJan Beulich3-4/+9
2018-06-01x86: relax redundant REX prefix checkJan Beulich5-2/+37
2018-06-01x86: simplify control register checkJan Beulich2-5/+7
2018-06-01x86: tighten condition for emitting LOCK on control register accessesJan Beulich2-4/+9
2018-06-01x86/Intel: accept "oword ptr" for INVPCIDJan Beulich7-0/+16
2018-05-30Add znver2 support.Amit Pawar12-36/+154
2018-05-25s12z regenAlan Modra2-0/+6
2018-05-24RISC-V: Fix .align handling when .option norelax.Jim Wilson7-10/+75
2018-05-21Remove fake operand handling for extended mnemonics.Peter Bergner6-455/+470
2018-05-18RISC-V: Add RV32E support.Jim Wilson3-11/+73
2018-05-18Add support for the Freescale s12z processor.John Darrington213-0/+8009
2018-05-16NDS32/GAS: Correct an `expr' global shadowing error for pre-4.8 GCCMaciej W. Rozycki2-2/+7
2018-05-15Implement Read/Write constraints on system registers on AArch64Tamar Christina7-5/+35
2018-05-15Allow non-fatal errors to be emitted and for disassembly notes be placed on A...Tamar Christina2-51/+89
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina2-10/+25
2018-05-14Stop generating GNU build notes for linkonce sections.Nick Clifton2-48/+49
2018-05-14Fix a problem in the assembler when checking for overlapping input and output...Nick Clifton2-1/+7
2018-05-12score gcc-8 warning fixesAlan Modra2-70/+72
2018-05-10Allow integer immediates for AArch64 fmov instructions.Tamar Christina8-43/+37
2018-05-10Allow integer immediate for VFP vmov instructions.Tamar Christina4-0/+34
2018-05-09gas: xtensa: fix literal movementMax Filippov9-21/+116
2018-05-09Fix binary compatibility between GCC and the TI compiler for the PRU target.Dimitar Dimitrov6-9/+37
2018-05-08RISC-V: Add missing hint instructions from RV128I.Jim Wilson5-2/+26
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu14-0/+199
2018-05-07x86: Replace AddrPrefixOp0 with AddrPrefixOpRegH.J. Lu2-3/+12
2018-05-07Cleanup ppc code dealing with opcode dumps.Peter Bergner2-38/+34
2018-05-06gas/i386/xmmhi32.d: Also allow dir32 relocationH.J. Lu2-42/+46
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