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2016-11-03arc: Implement NPS-400 dcmac instructionGraham Markall3-0/+100
2016-11-03arc: Change max instruction length to 64-bitsAndrew Burgess2-125/+44
2016-11-03arc: Replace ARC_SHORT macro with arc_opcode_len functionGraham Markall2-2/+9
2016-11-03gas/arc: Replace short_insn flag with insn length fieldGraham Markall2-45/+27
2016-11-04New option falkor for Qualcomm server partSiddhesh Poyarekar5-0/+15
2016-11-03X86: Decode opcode 0x82 as opcode 0x80 in 32-bit modeH.J. Lu4-0/+32
2016-11-03[ARM] Allow MOV/MOV.W to accept all possible immediatesJiong Wang10-17/+108
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist16-2/+762
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist24-3/+1124
2016-11-01Add support for RISC-V architecture.Nick Clifton16-7/+2667
2016-10-27gas/arc: Don't rely on bfd list of cpu type for cpu selectionAndrew Burgess3-91/+131
2016-10-26Revert "bison warning fixes"Alan Modra3-2/+8
2016-10-21X86: Remove pcommit instructionH.J. Lu10-84/+13
2016-10-20Check invalid mask registersH.J. Lu4-0/+30
2016-10-19[GAS][ARM]Generate unpredictable warning for pc used in data processing instr...Renlin Li5-0/+103
2016-10-17Fixed matching in newly added test.Cupertino Miranda2-1/+5
2016-10-17Removed pseudo invalid instructions opcodes.Cupertino Miranda3-0/+21
2016-10-14[ARC] Disassembler: fix LIMM detection for short instructions.Claudiu Zissulescu5-0/+47
2016-10-11Enhance objdump so that it will use .got, .plt and .plt.got section symbols w...Nick Clifton2-2/+6
2016-10-11[AArch64] PR target/20666, fix wrong encoding of new introduced BFC pseudoJiong Wang2-17/+22
2016-10-10MIPS64: Adjust cfi* testcases.Andreas Krebbel10-17/+29
2016-10-08Auto-generated dependencies for rx-parse.o and rl78-parse.oAlan Modra3-27/+22
2016-10-07[AArch64] PR target/20667, fix disassembler for the "special" optional SYS_Rt...Jiong Wang3-0/+162
2016-10-06[ARC] Fix parsing leave_s and enter_s mnemonics.Claudiu Zissulescu6-2/+68
2016-10-06-Wimplicit-fallthrough dodgy fixesAlan Modra3-4/+9
2016-10-06Refine .cfi_sections check to only consider compact eh_frameMatthew Fortune5-1/+42
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra37-18/+193
2016-10-06-Wimplicit-fallthrough noreturn fixesAlan Modra2-1/+5
2016-10-06-Wimplicit-fallthrough error fixesAlan Modra9-10/+28
2016-10-06bison warning fixesAlan Modra3-2/+7
2016-09-30[AArch64] PR target/20553, fix opcode mask for SIMD multiply by elementJiong Wang3-0/+22
2016-09-29Add .cfi_val_offset GAS command.Andreas Krebbel6-0/+76
2016-09-29Disallow 3-operand cmp[l][i] for ppc64Alan Modra4-4/+12
2016-09-26tc-xtensa.c: fixup xg_reverse_shift_count typoTrevor Saunders2-1/+6
2016-09-26When building target binaries, ensure that the warning flags selected for the...Vlad Zakharov4-6/+58
2016-09-26PowerPC .gnu.attributesAlan Modra2-0/+29
2016-09-22Remove legacy basepri_mask MRS/MSR special regThomas Preud'homme2-1/+5
2016-09-21[AArch64] Print spaces after commas in addressesRichard Sandiford16-9612/+9633
2016-09-21[AArch64] Use "must" rather than "should" in error messagesRichard Sandiford6-80/+90
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford11-69/+228
2016-09-21Fix misplaced ChangeLogRichard Sandiford2-11/+15
2016-09-21[AArch64][SVE 32/32] Add SVE testsRichard Sandiford15-0/+79428
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford3-1/+27
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford2-0/+11
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford2-3/+44
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford2-0/+32
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford2-15/+68
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford2-23/+237
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford2-1/+49
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford2-0/+71
generated by cgit v1.1 at 2024-12-29 11:18:27 +0000