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2021-01-30GNU Binutils 2.35.2 Releasebinutils-2_35_2Nick Clifton3-868/+881
2021-01-28POWER10: Add Return-Oriented Programming instructionsPeter Bergner7-0/+96
POWER10 adds some return-oriented programming (ROP) instructions and this patch adds support for them. You will notice that they are enabled for POWER8 and later, not just POWER10 and later. This is on purpose. This allows the instructions to be added to POWER8 binaries that can be run on POWER8, POWER9 and POWER10 cpus. On POWER8 and POWER9, these instructions just act as nop's. opcodes/ * ppc-opc.c (insert_dw, (extract_dw): New functions. (DW, (XRC_MASK): Define. (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics. gas/ * testsuite/gas/ppc/rop-checks.d, * testsuite/gas/ppc/rop-checks.l, * testsuite/gas/ppc/rop-checks.s, * testsuite/gas/ppc/rop.d, * testsuite/gas/ppc/rop.s: New tests. * testsuite/gas/ppc/ppc.exp: Run them. (cherry picked from commit aae7fcb8d755a2eb3f32a3f945a4e8f30cf5c5e2)
2021-01-28power10 on ppc32Alan Modra2-1/+9
We don't support power10 on ppc32, mainly because some instructions have 34-bit fields for which we don't have relocations on ppc32. If you try to assemble typical code, you'll see errors saying "reloc ... not supported by object file format". Also, on 32-bit hosts with binutils configured without a 64-bit bfd, you'll see errors saying "bignum invalid" when using large offsets. But let's not kill output of prefix insns entirely on 32-bit hosts. * config/tc-ppc.c (md_assemble): Emit prefix insn by parts when valueT is smaller than 64 bits. (cherry picked from commit 15a32af52fdc010801396cbcf62f33d88435ac1a)
2021-01-26PR27218, memory access violation in dwarf2dbg.cAlan Modra2-13/+20
PR 27218 * dwarf2dbg.c (dwarf2_gen_line_info): Correct setting of dwarf_level. (dwarf2_directive_filename, dwarf2_directive_loc): Likewise, and error for negative file numbers. (cherry picked from commit 498ff0328fed7689f7a675d8c9f0f04bed1f1522)
2021-01-26as: Automatically enable DWARF5 supportH.J. Lu4-9/+30
Currently $ as -o x.o x.s fails when x.s contains DWARF5 ".file 0" or ".loc 0" directives. Update assembler to automatically enable DWARF5 support so that $ gcc -S -g -c x.c $ gcc -c x.s works. PR gas/27195 * dwarf2dbg.c (dwarf2_gen_line_info): Set dwarf_level to 5 if needed. (dwarf2_directive_filename): Likewise. (dwarf2_directive_loc): Likewise. * testsuite/gas/elf/dwarf-5-file0.d: Pass --gdwarf-3. * testsuite/gas/lns/lns-diag-1.l: Remove the "Error: file number less than one" errors. (cherry picked from commit 705989f19adf20dd70c50237ec61cd708f2b0939)
2020-11-19gas, arm: PR26858 Fix availability of single precision vmul/vmla in arm modeAndre Vieira3-2/+16
This patch fixes a mistake when enabling MVE instructions that disabled support for single precision vmla and vmul for arm mode. gas/ChangeLog: 2020-11-19 Andre Vieira <andre.simoesdiasvieira@arm.com> Backport from mainline. 2020-11-12 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 26858 * config/tc-arm.c (asm_opcode insns): Fix vmul and vmla's ARM_VARIANT. * testsuite/gas/arm/pr26858.s: New test. * testsuite/gas/arm/pr26858.d: New test.
2020-11-16gas: Reuse the input file entry in the file tableH.J. Lu11-29/+309
Some instructions can be emitted (dwarf2_emit_insn is called) before the first .file <NUMBER> directive has been seen, which allocates the input file as the first file entry. Reuse the input file entry in the file table. PR gas/25878 PR gas/26740 * dwarf2dbg.c (file_entry): Remove auto_assigned. (assign_file_to_slot): Remove the auto_assign argument. (allocate_filenum): Updated. (allocate_filename_to_slot): Reuse the input file entry in the file table. (dwarf2_where): Replace as_where with as_where_physical. * testsuite/gas/i386/dwarf5-line-1.d: New file. * testsuite/gas/i386/dwarf5-line-1.s: Likewise. * testsuite/gas/i386/i386.exp: Run dwarf5-line-1. (cherry picked from commit 6915020bb134ae29fd772295c66fd67b5944962d) gas: Always use as_where for preprocessed assembly codes Always clear the slot 1 if it was assigned to the input file before the first .file <NUMBER> directive has been seen. Always use as_where to generate the correct debug infor for preprocessed assembly codes. PR gas/25878 PR gas/26740 * dwarf2dbg.c (allocate_filename_to_slot): Don't reuse the slot 1 here. (dwarf2_where): Restore as_where. (dwarf2_directive_filename): Clear the slot 1 if it was assigned to the input file. * testsuite/gas/i386/dwarf5-line-2.d: New file. * testsuite/gas/i386/dwarf5-line-2.s: Likewise. * testsuite/gas/i386/dwarf5-line-3.d: Likewise. * testsuite/gas/i386/dwarf5-line-3.s: Likewise. * testsuite/gas/i386/i386.exp: Run dwarf5-line-2 and dwarf5-line-3. (cherry picked from commit bd0c565edbf4ba8121fded38e389530d7fa6f963) gas: Clear all auto-assigned file slots Since a file slot is auto-assigned for the #APP marker appeared before the first .file <NUMBER> directive has been seen, clear all auto-assigned file slots when seeing the first .file <NUMBER> directive. PR gas/26778 * * dwarf2dbg.c (num_of_auto_assigned): New. (allocate_filenum): Increment num_of_auto_assigned. (dwarf2_directive_filename): Clear the slots auto-assigned before the first .file <NUMBER> directive was seen. * testsuite/gas/i386/dwarf4-line-1.d: New file. * testsuite/gas/i386/dwarf4-line-1.s: Likewise. * testsuite/gas/i386/i386.exp: Run dwarf4-line-1. (cherry picked from commit ae9d2233e61a98ff8dba56be10219aa5306ffc9a)
2020-11-16readelf: Show Unit Type for DWARF5Mark Wielaard2-0/+8
binutils/ChangeLog: * dwarf.c (process_debug_info): Print Unit Type for DWARF5. * testsuite/binutils-all/dw5.W: Adjust expected output. * testsuite/binutils-all/dwarf-attributes.W: Likewise. gas/ChangeLog: * testsuite/gas/elf/dwarf-5-cu.d: Adjust expected output. (cherry picked from commit debd1a62c4d250a6257e9018d9f9c7355edcdf8b)
2020-11-05aarch64: Add support for Neoverse N2 CPUAlex Coplan3-0/+16
This patch backports the AArch64 support for Arm's Neoverse N2 CPU to binutils 2.35. gas/ChangeLog: * config/tc-aarch64.c (aarch64_cpus): Add neoverse-n2. * doc/c-aarch64.texi: Document support for Neoverse N2.
2020-10-22arm: Fix the wrong error message string for mve vldr/vstr (PR26763).Srinath Parvathaneni5-1/+864
For mve vldr/vstr instructions assembler is throwing wrong error message. Instead of 'Error: syntax error' assembler fails with 'Error: lo register required'. This patch fixes the issue. eg: $ cat x.s .syntax unified .thumb vldrb.s16 q0, r0 Before this patch: $ arm-none-eabi-as x.s -march=armv8.1-m.main+mve -mfloat-abi=hard x.s: Assembler messages: x.s:4: Error: lo register required -- `vldrb.s16 q0,r0' After this patch: $ arm-none-eabi-as x.s -march=armv8.1-m.main+mve -mfloat-abi=hard x.s: Assembler messages: x.s:4: Error: syntax error -- `vldrb.s16 q0,r0' gas/ChangeLog: 2020-10-21 Srinath Parvathaneni <srinath.parvathaneni@arm.com> PR target/26763 * config/tc-arm.c (parse_address_main): Add new MVE addressing mode check. * testsuite/gas/arm/mve-vldr-vstr-bad.d: New test. * testsuite/gas/arm/mve-vldr-vstr-bad.l: Likewise. * testsuite/gas/arm/mve-vldr-vstr-bad.s: Likewise.
2020-10-09arm: Add support for Neoverse N2 CPUAlex Coplan3-0/+11
This patch backports the AArch32 support for Arm's Neoverse N2 CPU to binutils 2.35. gas/ChangeLog: * config/tc-arm.c (arm_cpus): Add Neoverse N2. * doc/c-arm.texi: Document -mcpu=neoverse-n2.
2020-10-09arm: Add support for Neoverse V1 CPUAlex Coplan3-0/+11
This patch backports the AArch32 support for Arm's Neoverse V1 CPU to binutils 2.35. gas/ChangeLog: * config/tc-arm.c (arm_cpus): Add Neoverse V1. * doc/c-arm.texi: Document Neoverse V1 support.
2020-10-07x86: Update register operand check for AddrPrefixOpRegH.J. Lu19-60/+196
When the address size prefix applies to both the memory and the register operand, we need to extract the address size prefix from the register operand if the memory operand has no real registers, like symbol, DISP or symbol(%rip). NB: GCC always generates symbol(%rip) for RIP-relative addressing for both x32 and x86-64. Move the .code16 tests in movdir.s to movdir-16bit to show the correct output from objdump. gas/ PR gas/26685 * config/tc-i386.c (process_suffix): Also check the register operand for the address size prefix if the memory operand has no real registers. * testsuite/gas/i386/enqcmd-16bit.d: New file. * testsuite/gas/i386/enqcmd-16bit.s: Likewise. * testsuite/gas/i386/movdir-16bit.d: Likewise. * testsuite/gas/i386/movdir-16bit.s: Likewise. * testsuite/gas/i386/enqcmd.s: Add tests with symbol and DISP. * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. * testsuite/gas/i386/x86-64-movdir.s: Likewise. * testsuite/gas/i386/movdir.s: Add tests with symbol and DISP. Remove the .code16 test. * testsuite/gas/i386/i386.exp: Run movdir-16bit and enqcmd-16bit. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise. * testsuite/gas/i386/enqcmd-intel.d: Likewise. * testsuite/gas/i386/enqcmd.d: Likewise. * testsuite/gas/i386/movdir-intel.d: Likewise. * testsuite/gas/i386/movdir.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise. opcodes/ PR gas/26685 * i386-dis.c (mod_table): Replace Gv with Gdq on movdiri. (cherry picked from commit b3a3496f83a14ad226790725c8e3ed9777fe2899)
2020-10-07x86: Check register operand for AddrPrefixOpRegH.J. Lu8-34/+114
If the address prefix changes the register operand, we need to check the register operand when the memory operand is RIP-relative. PR gas/26685 * config/tc-i386.c (process_suffix): Check the register operand for the address size prefix if the memory operand is symbol(%rip). * testsuite/gas/i386/x86-64-enqcmd.s: Add tests with RIP-relative addressing. * testsuite/gas/i386/x86-64-movdir.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise. (cherry picked from commit 27f134698ac529f3050f5ddbd31a0ab0bbe5be99)
2020-10-07Revert "x86: Don't display eiz with no scale"Jan Beulich4-13/+20
This reverts commit 04c662e2b66bedd050f97adec19afe0fcfce9ea7. In my underlying suggestion I neglected the fact that in those cases (,%eiz,1) is the only visible indication that 32-bit addressing is in effect. (cherry picked from commit bf4ba07ca61793a1faf81c0447ba97fdc6639b50)
2020-10-06aarch64: Fix bogus type punning in parse_barrier() [PR26699]Alex Coplan4-7/+11
This patch fixes a bogus use of type punning in parse_barrier() which was causing an assembly failure on big endian LP64 hosts when attempting to assemble "isb sy" for AArch64. The type of the entries in aarch64_barrier_opt_hsh is aarch64_name_value_pair. We were incorrectly casting this to the locally-defined asm_barrier_opt which has a wider type (on LP64) for the second member. This happened to work on little-endian hosts but fails on LP64 big endian. The fix is to use the correct type in parse_barrier(). This makes the locally-defined asm_barrier_opt redundant, so remove it. gas/ChangeLog: PR 26699 * config/tc-aarch64.c (asm_barrier_opt): Delete. (parse_barrier): Fix bogus type punning. * testsuite/gas/aarch64/system.d: Update disassembly. * testsuite/gas/aarch64/system.s: Add isb sy test. (cherry picked from commit 05cfb0d8cc9b7f8676f5ae55a93642f091d5405f)
2020-10-02aarch64: Add support for Neoverse V1 CPUAlex Coplan3-0/+15
This backports the AArch64 support for Arm's Neoverse V1 CPU to binutils 2.35. gas/ChangeLog: * config/tc-aarch64.c (aarch64_cpus): Add Neoverse V1. * doc/c-aarch64.texi: Document Neoverse V1 support.
2020-09-24Correct vcmpsq, vcmpuq and xvtlsbb BF fieldAlan Modra4-3/+8
These shouldn't be optional. The record form of vector instructions set CR6, giving an expectation that omitting BF should be the same as specifying CR6. opcodes/ * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq, vcmpuq and xvtlsbb. gas/ * testsuite/gas/ppc/int128.s: Correct vcmpuq. * testsuite/gas/ppc/int128.d: Update. * testsuite/gas/ppc/xvtlsbb.d: Update. (cherry picked from commit 18a8a00ebe3159b65798c6132cb5f93ff4ef6c17)
2020-09-24Implement missing powerpc extended mnemonicsAlan Modra5-0/+18
gas/ * testsuite/gas/ppc/power8.d, * testsuite/gas/ppc/power8.s: Add miso. * testsuite/gas/ppc/power9.d, * testsuite/gas/ppc/power8.s: Add exser, msgsndu, msgclru. opcodes/ * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru. Enable icbt for power5, miso for power8. (cherry picked from commit 8b2742a1567273f2ecc9fe6d7df1c9287865f5b6)
2020-09-24Prioritise mtfprd and mtvrd over mtvsrd in PowerPC disassemblyAlan Modra3-200/+204
gas/ * testsuite/gas/ppc/power8.d: Update. * testsuite/gas/ppc/vsx2.d: Update. opcodes/ * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over mtvsrd, and similarly for mfvsrd. (cherry picked from commit 5fbec329ec3b21fab7e06cd1e4bf7068332a876c)
2020-09-24Error on lmw, lswi and related PowerPC insns when LEAlan Modra11-1075/+1113
* config/tc-ppc.c (md_assemble): Error for lmw, stmw, lswi, lswx, stswi, or stswx in little-endian mode. * testsuite/gas/ppc/476.d, * testsuite/gas/ppc/476.s: Delete lmw, stmw, lswi, lswx, stswi, stswx. * testsuite/gas/ppc/a2.d, * testsuite/gas/ppc/a2.s: Move lmw, stmw, lswi, lswx, stswi, stswx.. * testsuite/gas/ppc/be.d, * testsuite/gas/ppc/be.s: ..to here, new big-endian only test. * testsuite/gas/ppc/le_error.d, * testsuite/gas/ppc/le_error.l: New little-endian test. * testsuite/gas/ppc/ppc.exp: Run new tests. (cherry picked from commit 86c0f617ac5f3a5f4aab76c7f90255254ca27576)
2020-09-192.35.1 point releasebinutils-2_35_1Nick Clifton3-747/+765
2020-09-19Import patch from mainline: 2020-09-15 Nick Clifton <nickc@redhat.com>Nick Clifton1-0/+9
* read.c (s_nop): Preserve the input_line_pointer around the call to md_assemble. * config/tc-s12z.c (md_assemble): Revert previous delta.
2020-09-17Use the correct no-op ocode for the BPF assembler.David Faust2-1/+10
* config/tc-bpf.h (md_single_noop_insn): Use 'ja 0' for no-op.
2020-09-15Add support to the assembler for a ".nop" directive which inserts a single ↵Nick Clifton17-36/+164
no-op instruction. Import from mainline: 2020-09-14 Nick Clifton <nickc@redhat.com> * read.c (s_nop): New function. Handles the .nop directive. (potable): Add entry for "nop". (s_nops): Code tidy. * read.h (s_nop): Add prototype. * config/tc-bpf.h (md_single_noop_insn): Define. * config/tc-mmix.h (md_single_noop_insn): Define. * config/tc-or1k.h (md_single_noop_insn): Define. * config/tc-ia64.h (md_single_noop_insn): Define. * write.c (relax_segment): Update error message regarding non-absolute values passed to .fill and .nops. * NEWS: Mention the new directive. * doc/as.texi: Document the new directive. * doc/internals.texi: Document the new internal macros used to implement the new directive. * testsuite/gas/all/nop.s: New test. * testsuite/gas/all/nop.d: New test control file. * testsuite/gas/all/gas.exp: Run the new test. * testsuite/gas/elf/dwarf-5-nop-for-line-table.s: New test. * testsuite/gas/elf/dwarf-5-nop-for-line-table.d: New test control file. * testsuite/gas/elf/elf.exp: Run the new test. * testsuite/gas/i386/space1.l: Adjust expected output.
2020-09-15gas: Don't error when .debug_line already exists, unless .loc was usedMark Wielaard13-10/+372
When -g was used to generate DWARF gas would error out when a .debug_line already exists. But when a .debug_info section already exists it would simply skip generating one without warning or error. Do the same for .debug_line. It is only an error when the user explicitly uses .loc directives and also generates the .debug_line table itself. The tests are unfortunately arch specific because the line table is only generated when actual instructions have been emitted. Use i386 because that is probably the most used architecture. Before this patch the new dwarf-line-2 testcase would fail, with this patch it succeeds (and doesn't try to add its own line table). gas/ChangeLog: * as.texi (-g): Explicitly mention when .debug_info and .debug_line are generated for the DWARF format. (Loc): Add that it is an error to both use a .loc directive and generate a .debug_line yourself. * dwarf2dbg.c (dwarf2_any_loc_directive_seen): New static variable. (dwarf2_directive_loc): Set dwarf2_any_loc_directive_seen to TRUE. (dwarf2_finish): Check dwarf2_any_loc_directive_seen before emitting an error. Only create .debug_line if it is empty (or doesn't exist). * testsuite/gas/i386/i386.exp: Add dwarf2-line-{1,2,3,4} when testing an elf target. * testsuite/gas/i386/dwarf2-line-{1,2,3,4}.{s,d,l}: New test files.
2020-09-15gas: Output directory and file names in .debug_line_str for DWARF5Mark Wielaard3-23/+85
* dwarf2dbg.c (add_line_strp): New function. (out_dir_and_file_list): Take line_seg and sizeof_offset as arguments, Use DW_FORM_line_strp for dir and file. Call add_line_strp and set symbol offset for DWARF2_LINE_VERSION 5. (out_debug_line): Call out_dir_and_file_list with line_seg and sizeof_offset. * gas/testsuite/gas/elf/dwarf-5-file0.d: Expect indirect line strings.
2020-09-15gas: Output .debug_rnglists for DWARF 5.Mark Wielaard2-13/+98
* dwarf2dbg.c (DWARF2_RNGLISTS_VERSION): New constant. (out_debug_ranges): Add ranges_sym argument and set it. (out_debug_rnglists): New function. (out_debug_info): Change ranges_seg argument to ranges_sym and use it to set DW_AT_ranges value. (dwarf2_finish): Remove ranges_seg, add ranges_sym. For DWARF2_VERSION 5 call out_debug_rnglists.
2020-09-15gas: Make sure to only add an md5 to a .file when requested.Mark Wielaard3-2/+11
* dwarf2dbg.c (dwarf2_directive_filename): Initialize with_md5 to FALSE. * gas/testsuite/gas/elf/dwarf-5-file0.s: Add a random bignum.
2020-09-15gas: Use DW_FORM_sec_offset for DWARF version 4 or higher.Mark Wielaard2-9/+19
Older DWARF versions used DW_FORM_data4 or DW_FORM_data8 for offsets into sections for e.g. DW_AT_stmt_list ot DW_AT_ranges. But version 4 introduced a dedicated form for such section offsets. Make sure to emit the proper form for newer DWARF versions. gas/ChangeLog: * dwarf2dbg.c (out_debug_abbrev): Use DW_FORM_sec_offset for DWARF version 4 or higher.
2020-09-15gas: Handle bad -gdwarf options, just like bad --gdwarf options.Mark Wielaard2-0/+14
parse_args uses getopt_long_only so it can handle long options both with double and single dash. But this means that some single dash options like -gdwarf-1 don't generate an error (unlike --gdwarf-1). This is especially confusing since there is also --gdwarf2, but no --gdwarf4 (it is --gdwarf-4). When giving -gdwarf4 the option is silently interpreted as -g (which set dwarf_version to 2). This causes some confusion for people who don't expect this and suddenly get DWARF2 instead of DWARF4 as they might expect. So make it so that the -gdwarf<unknown> creates an error, just like --gdwarf<unknown> would.
2020-08-26bpf: add xBPF ISAJose E. Marchesi7-4/+82
This patch adds support for xBPF, another ISA targetting the BPF virtual architecture. For now, the primary difference between eBPF and xBPF is that xBPF supports indirect calls through the 'call %reg' form of the call instruction. bfd/ * archures.c (bfd_mach_xbpf): Define. * bfd-in2.h: Regenerate. * cpu-bpf.c (bfd_xbpf_arch) New. (bfd_bpf_arch) Update next in list field to point to xbpf arch. cpu/ * bpf.cpu (arch bpf): Add xbpf mach and isas. (define-xbpf-isa) New pmacro. (all-isas) Add xbpfle,xbpfbe. (endian-isas): New pmacro. (mach xbpf): New. (model xbpf-def): Likewise. (h-gpr): Add xbpf mach. (f-dstle, f-srcle, dstle, srcle): Add xbpfle isa. (f-dstbe, f-srcbe, dstbe, srcbe): Add xbpfbe isa. (define-alu-insn-un): Use new endian-isas pmacro. (define-alu-insn-bin, define-alu-insn-mov): Likewise. (define-endian-insn, define-lddw): Likewise. (dlind, dxli, dxsi, dsti): Likewise. (define-cond-jump-insn, define-call-insn): Likewise. (define-atomic-insns): Likewise. gas/ * config/tc-bpf.c: Add option -mxbpf to select xbpf isa. * testsuite/gas/bpf/indcall-1.d: New file. * testsuite/gas/bpf/indcall-1.s: Likewise. * testsuite/gas/bpf/indcall-bad-1.l: Likewise. * testsuite/gas/bpf/indcall-bad-1.s: Likewise. * testsuite/gas/bpf/bpf.exp: Run new tests. opcodes/ * bpf-desc.c: Regenerate. * bpf-desc.h: Likewise. * bpf-opc.c: Likewise. * bpf-opc.h: Likewise. * disassemble.c (disassemble_init_for_target): Set bits for xBPF ISA when appropriate. (cherry picked from commit 4449c81a85eef44b10532032207e8db5858c00ee)
2020-08-25Backport patches from the mainline to fix bugs in the assembler's support ↵Nick Clifton9-15/+131
for DWARF-5. 2020-08-04 Mark Wielaard <mark@klomp.org> * dwarf2dbg.c (out_debug_abbrev): When DWARF2_VERSION >= 4, use DW_FORM_udata for DW_AT_high_pc. (out_debug_info): Use emit_leb128_expr for DW_AT_high_pc, when DWARF2_VERSION >= 4. * read.c (emit_leb128_exp): No longer static. * read.h (emit_leb128_exp): Define. 2020-08-02 Mark Wielaard <mark@klomp.org> * gas/dwarf2dbg.c (out_dir_and_file_list): For DWARF5 emit at least one directory if there is at least one file. Use dirs[1] if dirs[0] is not set, or if there is no dirs[1] the current working directory. Use files[1] filename, when files[0] filename isn't set. 2020-08-02 Mark Wielaard <mark@klomp.org> * dwarf2dbg.c (out_debug_info): Emit unit type and abbrev offset for DWARF5. * gas/testsuite/gas/elf/dwarf-4-cu.d: New file. * gas/testsuite/gas/elf/dwarf-4-cu.s: Likewise. * gas/testsuite/gas/elf/dwarf-5-cu.d: Likewise. * gas/testsuite/gas/elf/dwarf-5-cu.s: Likewise. * testsuite/gas/elf/elf.exp: Run dwarf-4-cu and dwarf-5-cu.
2020-08-18PowerPC: Rename xvcvbf16sp to xvcvbf16spnPeter Bergner3-2/+10
The xvcvbf16sp mnemonic has been renamed to xvcvbf16spn, to be consistent with the other non-signaling conversion instructions which all end with "n". opcodes/ Backported from master: 2020-08-18 Peter Bergner <bergner@linux.ibm.com> * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this... <xvcvbf16spn>: ...to this. gas/ Backported from master: 2020-08-18 Peter Bergner <bergner@linux.ibm.com> * testsuite/gas/ppc/vsx4.s: Update test to use new mnemonic. * testsuite/gas/ppc/vsx4.d: Likewise. (cherry picked from commit f5fc30d05c7e2aaba4fe892ab52fbf0930342dac)
2020-08-14Arm: Fix IT-predicated MVE vcvtJoe Ramsay7-8/+46
This patch fixes an incorrect parsing of vcvtne for MVE. Even when it appeared in an IT block, vcvtne would be parsed as a VPT-predicated vcvtn, instead of an IT-predicated vcvt. This change extends the existing handling of MVE vcvt to properly account for IT predication. gas/ChangeLog: 2020-08-13 Joe Ramsay <joe.ramsay@arm.com> Backported from master 2020-08-04 Joe Ramsay <joe.ramsay@.arm.com> * config/tc-arm.c (do_neon_cvt_1): Parse vcvtne as vcvt-ne for NS_FD shape when MVE is present * testsuite/gas/arm/mve-vcvtne-it-bad.d: New test. * testsuite/gas/arm/mve-vcvtne-it-bad.l: New test. * testsuite/gas/arm/mve-vcvtne-it-bad.s: New test. * testsuite/gas/arm/mve-vcvtne-it.d: New test. * testsuite/gas/arm/mve-vcvtne-it.s: New test.
2020-08-12Remove spurious text in changelog entryNick Clifton2-2248/+2646
2020-08-04gas/NEWS: Mention {disp16} pseudo prefixH.J. Lu2-0/+6
* NEWS: Mention {disp16} pseudo prefix. (cherry picked from commit 789198ca955f924c7928c016d922c68e3e2e6dae)
2020-08-04x86: Add {disp16} pseudo prefixH.J. Lu12-23/+190
Use Prefix_XXX for pseudo prefixes. Add {disp16} pseudo prefix and replace {disp32} pseudo prefix with {disp16} in 16-bit mode test. Check invalid {disp16}/{disp32} pseudo prefixes. gas/ PR gas/26305 * config/tc-i386.c (_i386_insn::disp_encoding): Add disp_encoding_16bit. (parse_insn): Check Prefix_XXX for pseudo prefixes. Handle {disp16}. (build_modrm_byte): Handle {disp16}. (i386_index_check): Check invalid {disp16} and {disp32} pseudo prefixes. * doc/c-i386.texi: Update {disp32} documentation and document {disp16}. * testsuite/gas/i386/i386.exp: Run x86-64-inval-pseudo. * testsuite/gas/i386/inval-pseudo.s: Add {disp32}/{disp16} tests. * testsuite/gas/i386/pseudos.s: Add {disp8}/{disp32} vmovaps tests with 128-byte displacement. Add {disp16} tests. * testsuite/gas/i386/x86-64-pseudos.s: Add {disp8}/{disp32} vmovaps test. Add (%r13)/(%r13d) tests. * testsuite/gas/i386/x86-64-inval-pseudo.l: New file. * testsuite/gas/i386/x86-64-inval-pseudo.s: Likewise. * testsuite/gas/i386/inval-pseudo.l: Updated. * testsuite/gas/i386/pseudos.d: Likewise. * testsuite/gas/i386/x86-64-pseudos.d: Likewise. opcodes/ PR gas/26305 * i386-opc.h (Prefix_Disp8): New. (Prefix_Disp16): Likewise. (Prefix_Disp32): Likewise. (Prefix_Load): Likewise. (Prefix_Store): Likewise. (Prefix_VEX): Likewise. (Prefix_VEX3): Likewise. (Prefix_EVEX): Likewise. (Prefix_REX): Likewise. (Prefix_NoOptimize): Likewise. * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}. * i386-tbl.h: Regenerated. (cherry picked from commit 41eb8e88859b297f59f4d093aab9306d4b7057d9)
2020-07-30Default to DWARF level 3 in the assembler.Nick Clifton2-3/+4
* as.c (dwatf_level): Default to level 3 in case version is not set on the command line.
2020-07-30Default to DWARF level 4 in the assembler.Nick Clifton2-1/+6
* as.c (dwatf_level): Default to level 4 in case version is not set on the command line.
2020-07-28x86: Handle {disp32} for (%bp)/(%ebp)/(%rbp)H.J. Lu7-3/+92
Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}. Note: Since there is no disp32 on 0(%bp), use disp16 instead. PR gas/26305 * config/tc-i386.c (build_modrm_byte): Use disp32/disp16 on (%bp)/(%ebp)/(%rbp) for {disp32}. * doc/c-i386.texi: Update {disp32} documentation. * testsuite/gas/i386/pseudos.s: Add (%bp)/(%ebp) tests. * testsuite/gas/i386/x86-64-pseudos.s: Add (%ebp)/(%rbp) tests. * testsuite/gas/i386/pseudos.d: Updated. * testsuite/gas/i386/x86-64-pseudos.d: Likewise. (cherry picked from commit 1a02d6b0ff80048df106cbb776a550278f8c9d9c)
2020-07-24Set version to 2.35.0 and enable developmentNick Clifton2-10/+14
2020-07-242.35 Releasebinutils-2_35Nick Clifton3-264/+270
2020-07-19x86: Change PLT32 reloc against section to PC32H.J. Lu4-6/+25
Commit 292676c1 resolved PLT32 reloc aganst local symbol to section. Since PLT32 relocation must be against symbols, turn such PLT32 relocation into PC32 relocation. gas/ PR gas/26263 * config/tc-i386.c (i386_validate_fix): Change PLT32 reloc against section to PC32 reloc. * testsuite/gas/i386/relax-5.d: Updated. * testsuite/gas/i386/x86-64-relax-4.d: Likewise. ld/ PR gas/26263 * testsuite/ld-i386/i386.exp: Run PR gas/26263 test. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-i386/pr26263.d: New file. * testsuite/ld-x86-64/pr26263.d: Likewise. * testsuite/ld-x86-64/pr26263.s: Likewise. (cherry picked from commit 2585b7a5ce5830e60a089aa2316a329558902f0c)
2020-07-15x86: Don't display eiz with no scaleH.J. Lu4-13/+21
Change 67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef(,%eiz,1),%rbx to 67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef,%rbx in AT&T syntax and 67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR [eiz*1+0x89abcdef] to 67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR ds:0x89abcdef in Intel syntax. gas/ PR gas/26237 * testsuite/gas/i386/evex-no-scale-64.d: Updated. * testsuite/gas/i386/addr32.d: Likewise. * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/x86-64-addr32.d: Likewise. opcodes/ PR gas/26237 * i386-dis.c (OP_E_memory): Don't display eiz with no scale without base nor index registers. (cherry picked from commit 04c662e2b66bedd050f97adec19afe0fcfce9ea7)
2020-07-15x86-64: Zero-extend lower 32 bits displacement to 64 bitsH.J. Lu8-54/+48
Since the addr32 (0x67) prefix zero-extends the lower 32 bits address to 64 bits, change disassembler to zero-extend the lower 32 bits displacement to 64 bits when there is no base nor index registers. gas/ PR gas/26237 * testsuite/gas/i386/addr32.s: Add tests for 32-bit wrapped around address. * testsuite/gas/i386/x86-64-addr32.s: Likewise. * testsuite/gas/i386/addr32.d: Updated. * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/x86-64-addr32.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise. opcodes/ PR gas/26237 * i386-dis.c (OP_E_memory): Without base nor index registers, 32-bit displacement to 64 bits. (cherry picked from commit 8e58ef803cf752cbde547a5064540f05470ea714)
2020-07-15x86: Remove 32-bit sign extension in offset_in_rangeH.J. Lu2-8/+6
When encoding a 32-bit offset, there is no need to sign-extend it to 64 bits since only the lower 32 bits are used. PR gas/26237 * config/tc-i386.c (offset_in_range): Remove 32-bit sign extension. (cherry picked from commit 7a705315596cf5effe01de8c3ac2535687c5663d)
2020-07-15Fix the generation of REL relocs for missing build notes.Nick Clifton2-9/+24
* write.c (create_note_reloc): Add desc2_size parameter. Zero out the addend field of REL relocations. Store the full addend into the note for REL relocations.
2020-07-13Updated French translation for the gas/ and binutils/ sub-directoriesNick Clifton2-2261/+2649
2020-07-07x86: Remove an incorrect AVX2 entryH.J. Lu2-10/+5
The upper 16 vector registers were added by AVX512. PR gas/26212 * doc/c-i386.texi: Remove an incorrect AVX2 entry. (cherry picked from commit dbdba9b04d4b91121357ac9a0402d67cb53ce7ce)
generated by cgit v1.1 at 2024-10-20 07:26:36 +0000