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2013-11-05gas/Yufeng Zhang6-0/+30
* config/tc-aarch64.c (parse_sys_reg): Update to use aarch64_sys_reg; call aarch64_sys_reg_deprecated_p and warn about the deprecated system registers. gas/testsuite/ * gas/aarch64/deprecated.d: New file. * gas/aarch64/deprecated.l: New file. * gas/aarch64/deprecated.s: New file. * gas/aarch64/sysreg-1.s: Add tests. * gas/aarch64/sysreg-1.d: Add tests. include/opcode/ * aarch64.h (aarch64_sys_reg): New typedef. (aarch64_sys_regs): Change to define with the new type. (aarch64_sys_reg_deprecated_p): Declare. opcodes/ * aarch64-opc.c (F_DEPRECATED): New macro. (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with F_DEPRECATED. (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on AARCH64_OPND_SYSREG.
2013-11-05gas/Yufeng Zhang8-2/+71
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_COND1. gas/testsuite/ * gas/aarch64/alias.s: Add tests. * gas/aarch64/alias.d: Update. * gas/aarch64/no-aliases.d: Update. * gas/aarch64/diagnostic.s: Add tests. * gas/aarch64/diagnostic.l: Update. * gas/aarch64/illegal.s: Add tests. * gas/aarch64/illegal.l: Update. include/opcode/ * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND. (enum aarch64_opnd): Add AARCH64_OPND_COND1. opcodes/ * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'. (convert_from_csel): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Handle AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1. (aarch64_print_operand): Handle AARCH64_OPND_COND1. * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of COND for cinc, cset, cinv, csetm and cneg. (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1. * aarch64-asm-2.c: Re-generated. * aarch64-dis-2.c: Ditto. * aarch64-opc-2.c: Ditto.
2013-11-05opcodes/Yufeng Zhang3-0/+17
* aarch64-opc.c (set_syntax_error): New function. (operand_general_constraint_met_p): Replace set_other_error with set_syntax_error. gas/testsuite/ * gas/aarch64/diagnostic.s: Add tests of ldp/stp. * gas/aarch64/diagnostic.l: Update.
2013-11-05config/tc-aarch64.c: Avoid trying to parse a vector mov as immediate.Will Newton3-0/+19
Parsing a vector mov instruction currently leads to a phantom undefined symbol being added to the symbol table. e.g.: .text mov x0, v0.D[0] Produces an undefined symbol called "v0.D". gas/ChangeLog: 2013-11-05 Will Newton <will.newton@linaro.org> PR gas/16103 * config/tc-aarch64.c (parse_operands): Avoid trying to parse a vector register as an immediate. gas/testsuite/ChangeLog: 2013-11-05 Will Newton <will.newton@linaro.org> * gas/aarch64/advsimd-mov-bad.d: New file. * gas/aarch64/advsimd-mov-bad.s: Likewise.
2013-11-04x86-64/gas: fix an asymmetry in suffix/register checkingJan Beulich4-0/+36
Without this, constructs like "orw %rax, (%rax)" aren't being rejected (other than any other wrong suffix/register combination). gas/ 2013-11-04 Jan Beulich <jbeulich@suse.com> * config/tc-i386.c (check_long_reg): Correct comment indentation. (check_qword_reg): Correct comment and its indentation. (check_word_reg): Extend comment and correct its indentation. Also check for 64-bit register. gas/testsuite/ 2013-11-04 Jan Beulich <jbeulich@suse.com> * gas/i386/x86-64-suffix-bad.[sl]: New. * gas/i386/i386.exp: Run new test.
2013-11-02Assorted x86 testsuite fixes.Alan Modra2-5/+4
I think HJ has already fixed the binutils and ld tests with his 2013-09-27 readelf change, but this allows them to pass with wider address output as per Nick's 2013-09-12 readelf change. binutils/testsuite/ * binutils-all/x86-64/compressed-1a.d: Allow wide display of addresses. gas/testsuite/ * gas/cfi/cfi-x86_64.d: Match when lacking end of section padding. ld/testsuite/ * ld-pe/cfi.d: Allow wide display of addresses.
2013-10-29ld/ELF: refine fake STT_FILE symbol emissionJan Beulich3-48/+52
There's no real need to emit these always: They're needed only if we indeed want to emit a localized symbol. Hence defer emission until we at least did the basic early checks that would lead to no such symbol getting emitted. This in particular avoids emitting such a symbol in the majority of (if not all) "ld -r" cases. I hope my set of cross build tests caught all the test cases needing adjustment - please forgive if I missed a few. bfd/ 2013-10-29 Jan Beulich <jbeulich@suse.com> * elflink.c (struct elf_outext_info): Add field file_sym_done. (bfd_elf_final_link): Initialize new field. Move fake STT_FILE symbol emission from here ... (elf_link_output_extsym): ... to here. gas/testsuite/ 2013-10-29 Jan Beulich <jbeulich@suse.com> * gas/microblaze/relax_size.elf: Drop expectation of no longer present STT_FILE symbol. * gas/microblaze/relax_size2.elf: Likewise. ld/testsuite/ 2013-10-29 Jan Beulich <jbeulich@suse.com> * ld-cris/tls-e-tpoffcomm1.d: Drop expectation of no longer present STT_FILE symbol. * ld-mmix/bpo-18.d: Likewise. * ld-mmix/bpo-22.d: Likewise. * ld-mmix/greg-6.d: Likewise. * ld-mmix/greg-7.d: Likewise. * ld-mmix/loc4.d: Likewise. * ld-mmix/local1.d: Likewise. * ld-mmix/local3.d: Likewise. * ld-mmix/local5.d: Likewise. * ld-mmix/local7.d: Likewise. * ld-mmix/loct-1.d: Likewise. * ld-sh/sh64/abi32.xd: Likewise. * ld-sh/sh64/abi64.xd: Likewise. * ld-sh/sh64/cmpct1.xd: Likewise. * ld-sh/sh64/crange1.rd: Likewise. * ld-sh/sh64/crange2.rd: Likewise. * ld-sh/sh64/crange3-cmpct.rd: Likewise. * ld-sh/sh64/crange3-media.rd: Likewise. * ld-sh/sh64/crange3.rd: Likewise. * ld-sh/sh64/crangerel1.rd: Likewise. * ld-sh/sh64/crangerel2.rd: Likewise. * ld-sh/sh64/mix1.xd: Likewise. * ld-sh/sh64/mix2.xd: Likewise. * ld-sh/sh64/shdl32.xd: Likewise. * ld-sh/sh64/shdl64.xd: Likewise.
2013-10-182013-10-18 Chao-ying Fu <Chao-ying.Fu@imgtec.com>Chao-ying Fu5-0/+750
* gas/mips/micromips@msa-branch.d, gas/mips/msa-branch.d, gas/mips/msa-branch.s: New. * gas/mips/mips.exp: Run new tests.
2013-10-15Fix neon vshll disassembly.Ramana Radhakrishnan2-6/+10
opcodes/ 2013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * arm-dis.c (neon_opcodes): Adjust print string for vshll. gas/testsuite/ 2013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * gas/arm/neon-cov.d: Adjust output.
2013-10-142013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>Chao-ying Fu12-0/+2657
* gas/mips/micromips@msa-relax.d, gas/mips/micromips@msa.d, gas/mips/micromips@msa64.d, gas/mips/msa-relax.d, gas/mips/msa-relax.l, gas/mips/msa-relax.s, gas/mips/msa.d, gas/mips/msa.s, gas/mips/msa64.d, gas/mips/msa64.s: New. * gas/mips/mips.exp: Run new tests.
2013-10-14 * gen-aout.c (main): Fix formatting. Close file.Nick Clifton2-1/+6
* emultempl/aix.em (_read_file): Close file at end of function. * gas/all/itbl-test.c (main): Close fas. * read.c (add_include_dir): Use xrealloc. * config/tc-score.c (do_macro_bcmp): Initialise inst_main. * config/tc-tic6x.c (tic6x_parse_operand): Initialise second_reg. * readelf.c (decode_arm_unwind): Initialise addr structure. (process_symbol_table): Free lengths. * srcconv.c (wr_sc): Free info. * chew.c (perform): Free next.
2013-10-142013-10-13 Sandra Loosemore <sandra@codesourcery.com>Sandra Loosemore4-13/+20
opcodes/ * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba" as the primary name of r30. gas/ * config/tc-nios2.c (nios2_consume_arg): Make the "ba" warning also test/refer to "sstatus". Reformat the warning message. gas/testsuite/ * gas/nios2/warn_nobreak.l: Update text of warning messages. * gas/nios2/registers.s: Use "sstatus" rather than "ba" as the primary name of r30. * gas/nios2/registers.d: Likewise.
2013-10-12Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcnH.J. Lu5-54/+38
gas/testsuite/ * gas/i386/mpx.s: Remove bndcl/bndcu/bndcn tests with AX. * gas/i386/x86-64-mpx.s: Likwise. * gas/i386/mpx.d: Updated. * gas/i386/x86-64-mpx.d: Likewise. opcodes/ * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the default case. (OP_E_register): Move v_bnd_mode alongside m_mode. * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants. Drop Reg16 and Disp16. Add NoRex64. (bndmk, bndmov, bndldx, bndstx): Drop Disp16. * i386-tbl.h: Re-generate.
2013-10-11 * gas/xgate/all_insns.d: Add com macro insn test.Sean Keys3-35/+42
* gas/xgate/all_insns.s: Add com macro insn test.
2013-10-08gas/Jan Beulich3-0/+14
2013-10-08 Jan Beulich <jbeulich@suse.com> * gas/config/tc-arm.c (do_t_push_pop): Honor inst.size_req. Simplify LR/PC check. gas/testsuite/ 2013-10-08 Jan Beulich <jbeulich@suse.com> * gas/arm/thumb-w-good.s: Add PUSH.W and POP.W tests. * gas/arm/thumb-w-good.d: Update accordingly.
2013-10-08 * config/tc-msp430.c (msp430_operands): Accept "<foo>.a" as an aliasNick Clifton7-0/+61
for "<foo>a". Issue error messages for unrecognised or corrrupt size extensions. * gas/msp430/bad.s: New test: Checks erroneous size extensions. * gas/msp430/bad.d: New test command file. * gas/msp430/bad.l: New file: Expected error messages. * gas/msp430/msp430.exp: Run the new test. * gas/msp430/msp430x.s: Add "<foo>.a" aliases of "<foo>a" instructions. * gas/msp430/msp430x.d: Update expected disassembly.
2013-10-072013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>Chao-ying Fu2-4/+8
* gas/mips/micromips@virt64.d: Fix dmfgc0 and dmtgc0.
2013-10-04[gas/]Kyrylo Tkachov4-0/+12
2013-10-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-arm.c (do_t_mvn_tst): Use narrow form for tst when possible. [gas/testsuite/] 2013-10-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gas/arm/thumb2_it.s: Add test for narrow tst. * gas/arm/thumb2_it.d: Update expected output. * gas/arm/thumb2_it_auto.d: Likewise.
2013-09-30Add AMD bdver4 support.Saravanan Ekanathan6-0/+420
gas/ * config/tc-i386.c (cpu_arch): Add CPU_BDVER4_FLAGS. * doc/c-i386.texi: Add -march=bdver4 option. gas/testsuite/ * gas/i386/i386.exp: Run bdver4 test cases. * gas/i386/nops-1-bdver4.d: New. * gas/i386/arch-10-bdver4.d: New. * gas/i386/x86-64-nops-1-bdver4.d: New. * gas/i386/x86-64-arch-2-bdver4.d: New. opcodes/ * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS. * i386-init.h: Regenerated.
2013-09-17opcodes/Richard Sandiford3-0/+8
* s390-opc.txt (clih): Make the immediate unsigned. gas/testsuite/ * gas/s390/zarch-z196.s, gas/s390/zarch-z196.d: Test CLIH with 4000000000.
2013-09-16gas/config/tc-arm.c: Fix parsing of NEON load/store element sizes.Will Newton6-0/+40
The existing code would accept VLD2.64 and similar undefined instructions. gas/ChangeLog: 2013-09-16 Will Newton <will.newton@linaro.org> * config/tc-arm.c (do_neon_ld_st_interleave): Add constraint disallowing element size 64 with interleave other than 1. gas/testsuite/ChangeLog: 2013-09-16 Will Newton <will.newton@linaro.org> * gas/arm/neon-ldst-es.d: Add VLD1.64 instructions. * gas/arm/neon-ldst-es.s: Likewise. * testsuite/gas/arm/neon-ldst-es-bad.d: New file. * testsuite/gas/arm/neon-ldst-es-bad.l: Likewise. * testsuite/gas/arm/neon-ldst-es-bad.s: Likewise.
2013-09-122013-09-12 Chao-ying Fu <Chao-ying.Fu@imgtec.com>Chao-ying Fu4-0/+24
* gas/mips/bltzal.s: New file. * gas/mips/bltzal.l: New file. * gas/mips/mips.exp: Run the bltzal test.
2013-09-12 * dwarf.c (dwarf_vmatoa): Rename to dwarf_vmatoa_1 and add aNick Clifton23-266/+292
precision parameter. (dwarf_vmatoa): New wrapper for dwarf_vmatoa_1. (print_dwarf_vma): Use dwarf_vmatoa_1. (SAFE_BYTE_GET): Add check that VAL is big enough to contain AMOUNT bytes. (process_debug_info): Use an unsigned int for the offset size. (process_debug_pubnames): Likewise. (display_debug_aranges): Likewise. (struct Frame_Chunk): Use dwarf_vma type for pc_begin and pc_range fields. (frame_display_row): Use print_dwarf_vma to display dwarf_vma values. (display_debug_frames): Likewise. * binutils-all/x86-64/compressed-1a.d: Update expected output to allow for 64-bit addresses. * ld-elf/eh1.d: Update expected output to allow for 64-bit addresses. * ld-elf/eh2.d: Likewise. * ld-elf/eh3.d: Likewise. * ld-elf/eh4.d: Likewise. * ld-elf/eh5.d: Likewise. * ld-elf/eh6.d: Likewise. * ld-mips-elf/eh-frame1-n64.d: Likewise. * ld-mips-elf/eh-frame2-n64.d: Likewise. * ld-mips-elf/eh-frame3.d: Likewise. * gas/cfi/cfi-alpha-1.d: Update expected output to allow for 64-bit addresses. * gas/cfi/cfi-alpha-3.d: Likewise. * gas/cfi/cfi-arm-1.d: Likewise. * gas/cfi/cfi-common-1.d: Likewise. * gas/cfi/cfi-common-2.d: Likewise. * gas/cfi/cfi-common-3.d: Likewise. * gas/cfi/cfi-common-4.d: Likewise. * gas/cfi/cfi-common-5.d: Likewise. * gas/cfi/cfi-common-6.d: Likewise. * gas/cfi/cfi-common-7.d: Likewise. * gas/cfi/cfi-hppa-1.d: Likewise. * gas/cfi/cfi-i386-2.d: Likewise. * gas/cfi/cfi-i386.d: Likewise. * gas/cfi/cfi-m68k.d: Likewise. * gas/cfi/cfi-mips-1.d: Likewise. * gas/cfi/cfi-ppc-1.d: Likewise. * gas/cfi/cfi-s390-1.d: Likewise. * gas/cfi/cfi-s390x-1.d: Likewise. * gas/cfi/cfi-sh-1.d: Likewise. * gas/cfi/cfi-sparc-1.d: Likewise. * gas/cfi/cfi-sparc64-1.d: Likewise. * gas/cfi/cfi-x86_64.d: Likewise.
2013-09-04gas/Tristan Gingold4-0/+39
* config/tc-ppc.c (md_apply_fix): Handle defined after use toc symbols. gas/testsuite/ * gas/ppc/aix.exp: Run xcoff-toc-1 test. * gas/ppc/xcoff-toc-1.s, gas/ppc/xcoff-toc-1.d: New test.
2013-09-04 PR gas/15914Nick Clifton7-0/+83
* config/tc-arm.c (T16_32_TAB): Add _udf. (do_t_udf): New function. (insns): Add "udf". * gas/arm/udf-bad.s: New file. * gas/arm/udf-bad.d: New file. * gas/arm/udf-bad.l: New file. * gas/arm/udf.s: New file. * gas/arm/udf.d: New file. * gas/arm/udf.l: New file. * arm-dis.c (arm_opcodes): Add udf. (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION. (thumb32_opcodes): Add udf.w. (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
2013-08-28 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if theNick Clifton3-1/+11
immediate is not suitable for the 32-bit ABI. * gas/aarch64/illegal.s: Add illegal constant for logical operation. * gas/aarch64/illegal.l: Add expected error message.
2013-08-23 opcodes/Maciej W. Rozycki6-23/+17
* micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps", replacing NODS. gas/testsuite/ * gas/testsuite/gas/mips/micromips-insn32.d: Adjust for delay slot scheduling of ALNV.PS. * gas/testsuite/gas/mips/micromips-noinsn32.d: Likewise. * gas/testsuite/gas/mips/micromips-trap.d: Likewise. * gas/testsuite/gas/mips/micromips.d: Likewise. * gas/testsuite/gas/mips/micromips@alnv_ps-swap.d: Likewise.
2013-08-23 PR binutils/15834Nick Clifton3-2/+8
Fix typos: --- bfd/bfdio.c | 2 +- bfd/elf32-spu.c | 2 +- bfd/elfnn-aarch64.c | 2 +- binutils/od-xcoff.c | 2 +- config/tcl.m4 | 2 +- gas/config/tc-ia64.c | 2 +- gas/config/tc-sparc.c | 2 +- gas/config/tc-z80.c | 12 ++++++------ gas/doc/c-i386.texi | 6 +++--- gas/doc/c-m32r.texi | 2 +- gas/testsuite/gas/d10v/instruction_packing.d | 2 +- gas/testsuite/gas/z80/atend.d | 2 +- gold/object.h | 2 +- include/gdb/remote-sim.h | 2 +- include/opcode/ChangeLog | 2 +- include/opcode/i960.h | 2 +- ld/testsuite/ld-mips-elf/mips16-pic-1.inc | 2 +- opcodes/aarch64-asm.c | 2 +- opcodes/aarch64-dis.c | 2 +- opcodes/msp430-dis.c | 2 +-
2013-08-23gas/config/tc-arm.c: Improve validation of NEON addressing modes.Will Newton3-9/+23
NEON vector load and store instructions do not accept immediates or pre-indexed base plus offset addressing modes, so make sure that the assembler enforces this. gas/ChangeLog: 2013-08-23 Will Newton <will.newton@linaro.org> * config/tc-arm.c (do_neon_ldx_stx): Add extra constraints for pre-indexed addressing modes. * testsuite/gas/arm/neon-addressing-bad.l: Add test for VLDn and VSTn instructions. * testsuite/gas/arm/neon-addressing-bad.s: Likewise. gas/testsuite/ChangeLog: 2013-08-23 Will Newton <will.newton@linaro.org> * testsuite/gas/arm/neon-addressing-bad.l: Add test for VLDn and VSTn instructions. * testsuite/gas/arm/neon-addressing-bad.s: Likewise.
2013-08-19gas/Richard Sandiford62-1539/+1568
* config/tc-mips.c (mips_check_isa_supports_ase, reg_lookup) (mips_parse_argument_token, validate_micromips_insn, md_begin) (check_regno, match_float_constant, check_completed_insn, append_insn) (match_insn, match_mips16_insn, match_insns, macro_start) (macro_build_ldst_constoffset, load_register, macro, mips_ip) (mips16_ip, mips_set_option_string, md_parse_option) (mips_after_parse_args, mips_after_parse_args, md_pcrel_from) (md_apply_fix, s_align, s_option, s_mipsset, s_tls_rel_directive) (s_gpword, s_gpdword, s_ehword, s_nan, tc_gen_reloc, md_convert_frag) (s_mips_end, s_mips_ent, s_mips_frame, s_mips_mask, mips_parse_cpu): Start error messages with a lower-case letter. Do not end error messages with a period. Wrap long messages to 80 character-lines. Use "cannot" instead of "can't" and "can not". gas/testsuite/ * gas/mips/ase-errors-1.l, gas/mips/ase-errors-2.l, gas/mips/ase-errors-3.l, gas/mips/ase-errors-4.l, gas/mips/at-2.l, gas/mips/baddata1.l, gas/mips/elf-rel30.l, gas/mips/illegal.l, gas/mips/jalr.l, gas/mips/ldstla-32-1.l, gas/mips/ldstla-32-mips3-1.l, gas/mips/lui-1.l, gas/mips/macro-warn-1.l, gas/mips/macro-warn-1-n32.l, gas/mips/macro-warn-2.l, gas/mips/macro-warn-3.l, gas/mips/macro-warn-4.l, gas/mips/micromips-branch-delay.l, gas/mips/micromips-branch-relax.l, gas/mips/micromips-branch-relax-pic.l, gas/mips/micromips-ill.l, gas/mips/micromips.l, gas/mips/micromips-size-0.l, gas/mips/micromips-size-1.l, gas/mips/micromips-warn-branch-delay.l, gas/mips/micromips-warn.l, gas/mips/mips16e-64.l, gas/mips/mips16e-save-err.l, gas/mips/mips1-fp.l, gas/mips/mips32r2-fp32.l, gas/mips/mips32r2-ill.l, gas/mips/mips32-sf32.l, gas/mips/mips4-branch-likely.l, gas/mips/mips4-fp.l, gas/mips/mips5-fp.l, gas/mips/mips64-mips3d.l, gas/mips/mips-double-float-flag.l, gas/mips/mips-gp64-fp32.l, gas/mips/mips-gp64-fp64.l, gas/mips/mips-hard-float-flag.l, gas/mips/mips-macro-ill-nofp.l, gas/mips/mips-macro-ill-sfp.l, gas/mips/nan-error-1.l, gas/mips/nan-error-2.l, gas/mips/noat-2.l, gas/mips/noat-3.l, gas/mips/noat-4.l, gas/mips/noat-5.l, gas/mips/noat-6.l, gas/mips/noat-7.l, gas/mips/octeon-ill.l, gas/mips/r5900-error-vu0.l, gas/mips/r5900-nollsc.l, gas/mips/relax-bc1any.l, gas/mips/relax-bposge.l, gas/mips/relax.l, gas/mips/relax-swap1.l, gas/mips/relax-swap2.l, gas/mips/set-arch.l, gas/mips/tls-ill.l, gas/mips/vr5400-ill.l: Adjust expected output.
2013-08-19include/opcode/Richard Sandiford9-83/+92
* mips.h (M_DEXT, M_DINS): Delete. opcodes/ * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins" macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases. Use +H rather than +C for the real "dext". * mips-opc.c (mips_builtin_opcodes): Likewise. gas/ * config/tc-mips.c (report_bad_range, report_bad_field): Delete. (macro): Remove M_DEXT and M_DINS handling. gas/testsuite/ * gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS error messages to have the same form as the EXT and INS ones. * gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d, gas/mips/micromips.d, gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect "dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu".
2013-08-19gas/Richard Sandiford4-5/+16
* config/tc-mips.c (match_expression): Report uses of registers here. Add a "must be an immediate expression" error. Handle elided offsets here rather than... (match_int_operand): ...here. gas/testsuite/ * gas/mips/octeon-ill.l: Adjust expected output. * gas/mips/lui-1.l, gas/mips/lui-1.s: Add more cases.
2013-08-19gas/Richard Sandiford16-126/+199
* config/tc-mips.c (mips_arg_info): Remove soft_match. (match_out_of_range, match_not_constant): New functions. (match_const_int): Remove fallback parameter and check for soft_match. Use match_not_constant. (match_mapped_int_operand, match_addiusp_operand) (match_perf_reg_operand, match_save_restore_list_operand) (match_mdmx_imm_reg_operand): Update accordingly. Use match_out_of_range and set_insn_error* instead of as_bad. (match_int_operand): Likewise. Use match_not_constant in the !allows_nonconst case. (match_float_constant): Report invalid float constants. (match_insn, match_mips16_insn): Remove soft_match code. Rely on match_float_constant to check for invalid constants. Fail the match if match_const_int or match_float_constant return false. (mips_ip): Update accordingly. (mips16_ip): Likewise. Undo null termination of instruction name once lookup is complete. gas/testsuite/ * gas/mips/ext-ill.l, gas/mips/lui-1.l, gas/mips/mips16e-64.l, gas/mips/mips32r2-ill-fp64.l, gas/mips/mips32r2-ill-nofp.l, gas/mips/mips32r2-ill.l, gas/mips/mips64r2-ill.l, gas/mips/octeon-ill.l, gas/mips/r5900-error-vu0.l, gas/mips/vr5400-ill.l: Adjust expected errors. * gas/mips/micromips-size-0.l, gas/mips/micromips-size-0.s: Likewise. Add new tests. * gas/mips/mips16e-save-err.s, gas/mips/mips16e-save-err.l: New test. * gas/mips/mips.exp: Run it.
2013-08-19gas/Richard Sandiford2-2/+6
* config/tc-mips.c (mips_insn_error_format): New enum. (mips_insn_error): New struct. (insn_error): Change to a mips_insn_error. (clear_insn_error, set_insn_error_format, set_insn_error) (set_insn_error_i, set_insn_error_ss, report_insn_error): New functions. (mips_parse_argument_token, md_assemble, match_insn) (match_mips16_insn): Use them instead of manipulating insn_error directly. (mips_ip, mips16_ip): Likewise. Simplify control flow. gas/testsuite/ * gas/mips/micromips-ill.l: Expect "floating-point expression required"
2013-08-06opcodes/Richard Sandiford5-5/+17
2013-08-06 Jürgen Urban <JuergenUrban@gmx.de> * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of VCLIPW. gas/ 2013-08-06 Jürgen Urban <JuergenUrban@gmx.de> * config/tc-mips.c (match_vu0_suffix_operand): Allow single-channel suffixes to be elided too. (mips_lookup_insn): Don't reject INSN2_VU0_CHANNEL_SUFFIX here. (mips_ip): Assume .xyzw if no VU0 suffix is specified. Allow +N to be omitted too. gas/testsuite/ 2013-08-06 Jürgen Urban <JuergenUrban@gmx.de> * gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l, gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d: Allow single-channel suffixes to be elided.
2013-08-04include/opcode/Richard Sandiford9-38/+20253
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * mips.h: Document new VU0 operand characters. (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types. (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R) (OP_REG_R5900_ACC): New mips_reg_operand_types. (INSN2_VU0_CHANNEL_SUFFIX): New macro. (mips_vu0_channel_mask): Declare. opcodes/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. (print_vu0_channel): New function. (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (print_insn_args): Handle '#'. (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX. * mips-opc.c (mips_vu0_channel_mask): New constant. (decode_mips_operand): Handle new VU0 operand types. (VU0, VU0CH): New macros. (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E" for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2. Use "+6" rather than "G" for QMFC2 and QMTC2. gas/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * config/tc-mips.c (MAX_OPERANDS): Bump to 6. (RWARN): Bump to 0x8000000. (RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R) (RTYPE_R5900_ACC): New register types. (RTYPE_MASK): Include them. (R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New macros. (reg_names): Include them. (mips_parse_register_1): New function, split out from... (mips_parse_register): ...here. Add a channels_ptr parameter. Look for VU0 channel suffixes when nonnull. (reg_lookup): Update the call to mips_parse_register. (mips_parse_vu0_channels): New function. (OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types. (mips_operand_token): Add a "channels" field to the union. Extend the comment above "ch" to OT_DOUBLE_CHAR. (mips_parse_base_start): Match -- and ++. Handle channel suffixes. (mips_parse_argument_token): Handle channel suffixes here too. (validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX. Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits. Handle '#' formats. (md_begin): Register $vfN and $vfI registers. (operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. (match_vu0_suffix_operand): New function. (match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (macro): Use "+7" rather than "E" for LDQ2 and STQ2. (mips_lookup_insn): New function. (mips_ip): Use it. Allow "+K" operands to be elided at the end of an instruction. Handle '#' sequences. gas/testsuite/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> * gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric coprocessor registers. * gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d, gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d, gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests. * gas/mips/mips.exp: Run them.
2013-08-03gas/Richard Sandiford4-0/+194
* config/tc-mips.c (mips16_macro): Don't use move_register. (mips16_ip): Allow macros to use 'p'. gas/testsuite/ * gas/mips/mips16-macro.s, gas/mips/mips16-macro.d: New test. * gas/mips/mips.exp: Run it.
2013-07-26Add Intel AVX-512 supportH.J. Lu67-7/+123596
binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-25opcodes/Richard Sandiford2-4/+9
2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi> PR gas/15220 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps. gas/testsuite/ * gas/mips/loongson-2f.d: Fix expected output for madd.ps, msub.ps, nmadd.ps and nmsub.ps.
2013-07-25Support Intel SHAH.J. Lu6-0/+299
gas/ 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386.c (cpu_arch): Add .sha. * doc/c-i386.texi: Document sha/.sha. gas/testsuite/ 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/i386/sha.d: New. * gas/i386/sha.s: New. * gas/i386/x86-64-sha.d: New. * gas/i386/x86-64-sha.s: New. * gas/i386/i386.exp: Run new SHA tests. opcodes/ 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD, PREFIX_0F3ACC. (prefix_table): Updated. (three_byte_table): Likewise. * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS. (cpu_flags): Add CpuSHA. (i386_cpu_flags): Add cpusha. * i386-init.h: Regenerate. * i386-opc.h (CpuSHA): New. (CpuUnused): Restored. (i386_cpu_flags): Add cpusha. * i386-opc.tbl: Add SHA instructions. * i386-tbl.h: Regenerate.
2013-07-24Support Intel MPXH.J. Lu23-40/+1263
gas/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386.c (BND_PREFIX): New. (struct _i386_insn): Add new field bnd_prefix. (add_bnd_prefix): New. (cpu_arch): Add MPX. (i386_operand_type): Add regbnd. (md_assemble): Handle BND prefixes. (parse_insn): Likewise. (output_branch): Likewise. (output_jump): Likewise. (build_modrm_byte): Handle regbnd. (OPTION_MADD_BND_PREFIX): New. (md_longopts): Add entry for 'madd-bnd-prefix'. (md_parse_option): Handle madd-bnd-prefix option. (md_show_usage): Add description for madd-bnd-prefix option. * doc/c-i386.texi: Document mpx/.mpx and -madd-bnd-prefix. gas/testsuite/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/i386/mpx-add-bnd-prefix.s: New. * gas/i386/mpx-add-bnd-prefix.d: New. * gas/i386/mpx-inval-1.l: New. * gas/i386/mpx-inval-1.s: New. * gas/i386/mpx.d: New. * gas/i386/mpx.s: New. * gas/i386/x86-64-mpx-add-bnd-prefix.d: New. * gas/i386/x86-64-mpx-add-bnd-prefix.s: New. * gas/i386/x86-64-mpx-addr32.d: New. * gas/i386/x86-64-mpx-addr32.s: New. * gas/i386/x86-64-mpx-inval-1.l: New. * gas/i386/x86-64-mpx-inval-1.s: New. * gas/i386/x86-64-mpx-inval-2.l: New. * gas/i386/x86-64-mpx-inval-2.s: New. * gas/i386/x86-64-mpx.d: New. * gas/i386/x86-64-mpx.s: New. * gas/i386/nops.d: Adjust to MPX changes. * gas/i386/nops.s: Likewise. * gas/i386/x86-64-nops.d: Likewise. * gas/i386/x86-64-nops.s: Likewise. * gas/i386/ilp32/x86-64-nops.d: Likewise. * gas/i386/i386.exp: Run new MPX tests. include/opcode/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386.h (BND_PREFIX_OPCODE): New. opcodes/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis.c (BND_Fixup): New. (Ebnd): New. (Ev_bnd): New. (Gbnd): New. (BND): New. (v_bnd_mode): New. (bnd_mode): New. (MOD enum): Add new entries. (PREFIX enum): Likewise. (dis tables): Replace XX with BND for near branch and call instructions. (prefix_table): Add new entries. (mod_table): Likewise. (names_bnd): New. (intel_names_bnd): New. (att_names_bnd): New. (BND_PREFIX): New. (prefix_name): Handle BND_PREFIX. (print_insn): Initialize names_bnd. (intel_operand_size): Handle new modes. (OP_E_register): Likewise. (OP_E_memory): Likewise. (OP_G): Likewise. * i386-gen.c (cpu_flag_init): Add CpuMPX. (cpu_flags): Add CpuMPX. (operand_type_init): Add RegBND. (opcode_modifiers): Add BNDPrefixOk. (operand_types): Add RegBND. * i386-init.h: Regenerate. * i386-opc.h (CpuMPX): New. (CpuUnused): Comment out. (i386_cpu_flags): Add cpumpx. (BNDPrefixOk): New. (i386_opcode_modifier): Add bndprefixok. (RegBND): New. (i386_operand_type): Add regbnd. * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets. Add MPX instructions and bnd prefix. * i386-reg.tbl: Add bnd0-bnd3 registers. * i386-tbl.h: Regenerate.
2013-07-24bfd/Tristan Gingold9-0/+140
2013-07-24 Tristan Gingold <gingold@adacore.com> * coff-rs6000.c (xcoff_howto_table): Fix masks and pc_relative for R_RBR. Add numbers in comments. (_bfd_xcoff_reloc_type_lookup): Handle BFD_RELOC_PPC_B16. * coff64-rs6000.c: Likewise. gas/ 2013-07-24 Tristan Gingold <gingold@adacore.com> * config/tc-ppc.c (md_apply_fix): Adjust BFD_RELOC_PPC_B16 on xcoff targets. gas/testsuite/ 2013-07-24 Tristan Gingold <gingold@adacore.com> * gas/ppc/test2xcoff32.s, gas/ppc/test2xcoff32.d: New files * gas/ppc/ppc.exp: Add new test. * gas/ppc/xcoff-br16-1.s, gas/ppc/xcoff-br16-1.d, gas/ppc/xcoff-br16-2.s, gas/ppc/xcoff-br16-2.d: New files * gas/ppc/aix.exp: Add new tests.
2013-07-19[AArch64, ILP32] Retire -milp32 and -mlp64; use -mabi=ilp32 and -mabi=lp64.Yufeng Zhang2-1/+5
gas/ * config/tc-aarch64.c (enum aarch64_abi_type): New enumeration tag. (AARCH64_ABI_LP64, AARCH64_ABI_ILP32): New enumerators. (aarch64_abi): New variable. (ilp32_p): Change to be a macro. (aarch64_opts): Remove the support for option -milp32 and -mlp64. (struct aarch64_option_abi_value_table): New struct. (aarch64_abis): New table. (aarch64_parse_abi): New function. (aarch64_long_opts): Add entry for -mabi=. * doc/as.texinfo (Target AArch64 options): Document -mabi. * doc/c-aarch64.texi: Likewise. gas/testsuite/ * gas/aarch64/ilp32-basic.d (#as): Update to use -mabi=ilp32
2013-07-14gas/Richard Sandiford6-0/+30
* config/tc-mips.c (mips_prefer_vec_regno, mips_parse_register): New functions, split out from... (reg_lookup): ...here. Remove itbl support. (reglist_lookup): Delete. (mips_operand_token_type): New enum. (mips_operand_token): New structure. (mips_operand_tokens): New variable. (mips_add_token, mips_parse_base_start, mips_parse_argument_token) (mips_parse_arguments): New functions. (md_begin): Initialize mips_operand_tokens. (mips_arg_info): Add a token field. Remove optional_reg field. (match_char, match_expression): New functions. (match_const_int): Use match_expression. Remove "s" argument and return a boolean result. Remove O_register handling. (match_regno, match_reg, match_reg_range): New functions. (match_int_operand, match_mapped_int_operand, match_msb_operand) (match_reg_operand, match_reg_pair_operand, match_perf_reg_operand) (match_addiusp_operand, match_clo_clz_dest_operand) (match_lwm_swm_list_operand, match_entry_exit_operand) (match_save_restore_list_operand, match_mdmx_imm_reg_operand) (match_tied_reg_operand): Remove "s" argument and return a boolean result. Match tokens rather than text. Update calls to match_const_int. Rely on match_regno to call check_regno. (match_pcrel_operand, match_pc_operand): Replace "s" argument with "arg" argument. Return a boolean result. (parse_float_constant): Replace with... (match_float_constant): ...this new function. (match_operand): Remove "s" argument and return a boolean result. Update calls to subfunctions. (mips_ip, mips16_ip): Call mips_parse_arguments. Use match routines rather than string-parsing routines. Update handling of optional registers for token scheme. gas/testsuite/ * gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: Add some more cases. * gas/mips/micromips-ill.s, gas/mips/micromips-ill.l: New test. * gas/mips/mips.exp: Run it.
2013-07-14gas/Richard Sandiford9-123/+126
* config/tc-mips.c: Enable functions commented out in previous patch. (SKIP_SPACE_TABS): Move further up file. (mips32_to_micromips_reg_b_map, mips32_to_micromips_reg_c_map) (mips32_to_micromips_reg_d_map, mips32_to_micromips_reg_e_map) (ips32_to_micromips_reg_f_map, mips32_to_micromips_reg_g_map) (mips32_to_micromips_reg_l_map, mips32_to_micromips_reg_m_map) (mips32_to_micromips_reg_q_map, mips32_to_micromips_reg_n_map) (micromips_imm_b_map, micromips_imm_c_map): Delete. (mips_lookup_reg_pair): Delete. (macro): Use report_bad_range and report_bad_field. (mips_immed, expr_const_in_range): Delete. (mips_ip): Rewrite main parsing loop to use new functions. gas/testsuite/ * gas/mips/at-2.l: Remove duplicated $at warnings. * gas/mips/ext-ill.l, gas/mips/lui-1.l, gas/mips/mips32r2-ill.l, gas/mips/mips32r2-ill-nofp.l, gas/mips/mips32r2-ill-fp64.l, gas/mips/mips64r2-ill.l, gas/mips/octeon-ill.l: Update error messages. Expect negative numbers to be printed as such, rather than as large unsigned positive numbers.
2013-07-12 include/elf/Maciej W. Rozycki19-0/+110
* mips.h (EF_MIPS_NAN2008): New macro. bfd/ * elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Handle EF_MIPS_NAN2008. (_bfd_mips_elf_print_private_bfd_data): Likewise. binutils/ * readelf.c (get_machine_flags): Handle EF_MIPS_NAN2008. gas/ * config/tc-mips.c (mips_flag_nan2008): New variable. (options): Add OPTION_NAN enum value. (md_longopts): Handle it. (md_parse_option): Likewise. (s_nan): New function. (mips_elf_final_processing): Handle EF_MIPS_NAN2008. (md_show_usage): Add -mnan. * doc/as.texinfo (Overview): Add -mnan. * doc/c-mips.texi (MIPS Opts): Document -mnan. (MIPS NaN Encodings): New node. Document .nan directive. (MIPS-Dependent): List the new node. gas/testsuite/ * gas/mips/nan-2008-1.d: New test. * gas/mips/nan-2008-2.d: New test. * gas/mips/nan-2008-3.d: New test. * gas/mips/nan-2008-4.d: New test. * gas/mips/nan-legacy-1.d: New test. * gas/mips/nan-legacy-2.d: New test. * gas/mips/nan-legacy-3.d: New test. * gas/mips/nan-legacy-4.d: New test. * gas/mips/nan-legacy-5.d: New test. * gas/mips/nan-error-1.l: New list test. * gas/mips/nan-error-2.l: New list test. * gas/mips/nan-2008-override.s: New test source. * gas/mips/nan-2008.s: New test source. * gas/mips/nan-legacy-override.s: New test source. * gas/mips/nan-legacy.s: New test source. * gas/mips/nan-error-1.s: New test source. * gas/mips/nan-error-2.s: New test source. * gas/mips/mips.exp: Run the new tests. ld/testsuite/ * ld-mips-elf/nan-2008.d: New test. * ld-mips-elf/nan-legacy.d: New test. * ld-mips-elf/nan-mixed-1.d: New test. * ld-mips-elf/nan-mixed-2.d: New test. * ld-mips-elf/nan-2008.s: New test source. * ld-mips-elf/nan-legacy.s: New test source.
2013-07-09gas/testsuite/Richard Sandiford5-0/+101
* gas/mips/la-reloc.s, gas/mips/la-reloc.d, gas/mips/dla-reloc.s, gas/mips/dla-reloc.d: Add files missing from earlier commit.
2013-07-08Replace Xmmword with Qword on cvttps2piH.J. Lu4-0/+10
gas/testsuite/ PR gas/13572 * gas/i386/simd.s: Add a test for cvttps2pi. * gas/i386/simd-intel.d: Updated. * gas/i386/simd.d: Likewise. opcodes/ PR gas/13572 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi. * i386-tbl.h: Regenerated.
2013-07-08gas/Richard Sandiford5-0/+55
* config/tc-mips.c (mips_ip): Unconditionally parse an expression for 'A' and assume that the constant has been elided if the result is an O_register. gas/testsuite/ * gas/mips/la.s, gas/mips/la.d, gas/mips/la-svr4pic.d, gas/mips/la-xgot.d: Add tests for bracketed addresses.
2013-07-07include/opcode/Richard Sandiford24-3407/+3193
* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB) (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB) (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A) (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB) (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB) (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB) (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB) (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB) (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A) (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A) (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB) (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete. (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A): Rename to... (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB) (M_USD_AB): ...these. opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD and SD A(B) macros up. * micromips-opc.c (micromips_opcodes): Likewise. gas/ * config/tc-mips.c (gprel16_reloc_p): New function. (macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are BFD_RELOC_UNUSED. (offset_high_part, small_offset_p): New functions. (nacro): Use them. Remove *_OB and *_DOB cases. For single- register load and store macros, handle the 16-bit offset case first. If a 16-bit offset is not suitable for the instruction we're generating, load it into the temporary register using ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the M_L_DAB code once the address has been constructed. For double load and store macros, again handle the 16-bit offset case first. If the second register cannot be accessed from the same high part as the first, load it into AT using ADDRESS_ADDI_INSN. Fix the handling of LD in cases where the first register is the same as the base. Also handle the case where the offset is not 16 bits and the second register cannot be accessed from the same high part as the first. For unaligned loads and stores, fuse the offbits == 12 and old "ab" handling. Apply this handling whenever the second offset needs a different high part from the first. Construct the offset using ADDRESS_ADDI_INSN where possible, for offbits == 16 as well as offbits == 12. Use offset_reloc when constructing the individual loads and stores. (mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc and offset_reloc before matching against a particular opcode. Handle elided 'A' constants. Allow 'A' constants to use relocation operators. gas/testsuite/ * gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for truncated constants. * gas/mips/ldstla-32-shared.d: Likewise. * gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding 16-bit constants to the base. * gas/mips/micromips@mcu.d: Likewise. * gas/mips/micromips@cache.d: Likewise. * gas/mips/micromips@pref.d: Likewise. * gas/mips/micromips.d, gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise. Allow the full 16-bit offset range to be used for SB, LB and LBU in USH and ULH sequences. Fix the expected output for LD and SD when the two LW and SW offsets need different high parts. * gas/mips/eva.s: Test PREFE with relocation operators. * gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit constants. Update after eva.s change. * gas/mips/micromips@eva.d: Likewise. * gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s, gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d, gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s, gas/mips/ulh-reloc.d: New tests. * gas/mips/mips.exp: Run them.
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