aboutsummaryrefslogtreecommitdiff
path: root/gas/testsuite
AgeCommit message (Expand)AuthorFilesLines
2018-02-12MIPS/GAS/test: Fix an n32 `.reginfo' size test failureMaciej W. Rozycki1-1/+1
2018-02-12MIPS: Fix encoding for MIPSr6 sigrie instruction.Henry Wong3-6/+6
2018-02-08PR22819, powerpc gas "instruction address is not a multiple of 4"Alan Modra6-0/+29
2018-02-05MIPS/BFD: Correctly report unsupported `.reginfo' section sizeMaciej W. Rozycki5-0/+16
2018-01-24[GAS][AARCH64]Add group relocations to create PC-relative offset.Renlin Li14-0/+155
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist7-0/+58
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist7-0/+58
2018-01-22Fix the RX assembler so that it can handle escaped double quote characters, i...Oleg Endo3-0/+17
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist9-0/+44
2018-01-15RISC-V: Add support for addi that compresses to c.nop.Jim Wilson2-2/+4
2018-01-15[ARM] Enable conditional Armv8-M instructionsThomas Preud'homme1-2/+11
2018-01-15[ARM] No IT usage deprecation for ARMv8-MThomas Preud'homme5-48/+49
2018-01-11Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist19-1030/+16
2018-01-10x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich12-381/+384
2018-01-10x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich6-0/+36
2018-01-09RISC-V: Disassemble x0 based addresses as 0.Jim Wilson2-0/+16
2018-01-09[Arm] Add CSDB instructionJames Greenhalgh4-0/+19
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh1-1/+1
2018-01-08x86: Properly encode vmovd with 64-bit memeoryH.J. Lu4-0/+136
2018-01-04RISC-V: Add 2 missing privileged registers.Jim Wilson2-24/+28
2018-01-03Update year range in copyright notice of binutils filesAlan Modra192-192/+192
2017-12-28RISC-V: Add missing privileged spec registers.Jim Wilson2-0/+518
2017-12-20RISC-V: Add compressed instruction hints, and a few misc cleanups.Jim Wilson12-0/+92
2017-12-19Correct disassembly of dot product instructions.Tamar Christina1-432/+432
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina3-0/+24
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich1-45/+45
2017-12-17x86: Check pseudo prefix without instructionH.J. Lu3-0/+17
2017-12-14Update the address of the FSF in the copyright notice of files which were usi...Nick Clifton1-3/+3
2017-12-13Add missing RISC-V fsrmi and fsflagsi instructions.Jim Wilson2-0/+17
2017-12-13This patch enables disassembler_needs_relocs for PRU. It is needed to print c...Dimitar Dimitrov2-0/+15
2017-12-04Run powerpc vle gas tests for all powerpc ELF targetsAlan Modra18-39/+37
2017-11-30x86/Intel: issue diagnostics for redundant segment override prefixesJan Beulich4-4/+26
2017-11-30Revert "x86: Update segment register check in Intel syntax"Jan Beulich5-43/+11
2017-11-29Fix riscv malloc error on small alignment after norvc.Jim Wilson3-9/+6
2017-11-29[GAS][AARCH64]Fix a typo for IP1 register alias.Renlin Li2-1/+5
2017-11-27Compress loads/stores with implicit 0 offset.Jim Wilson5-0/+54
2017-11-27gas: xtensa: implement trampoline coalescingMax Filippov5-16/+38
2017-11-27gas: xtensa: reuse trampoline placement codeMax Filippov1-3/+3
2017-11-27gas: xtensa: rewrite xg_relax_trampolineMax Filippov2-16/+15
2017-11-26gas: Update x86 sse-noavx testsH.J. Lu5-0/+7
2017-11-24x86: reject further invalid AVX-512 masking constructsJan Beulich4-0/+42
2017-11-24x86: don't omit disambiguating suffixes from "fi*"Jan Beulich9-13/+16
2017-11-23Fix vax/ns32k/mmix gas testsuite regression.Jim Wilson1-1/+1
2017-11-23Add Disp8MemShift for AVX512 VAES instructions.Igor Tsimbalist17-96/+192
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich3-0/+20
2017-11-23x86-64: always use unsigned 32-bit reloc for 32-bit addressing w/o base regJan Beulich2-0/+10
2017-11-23x86: correct UDnJan Beulich8-11/+12
2017-11-23x86/Intel: don't report multiple errors for a single insn operandJan Beulich2-6/+0
2017-11-22Riscv ld-elf/stab failure and fake label cleanup.Jim Wilson1-0/+3
2017-11-22[ARC] Fix handling of ARCv2 H-register class.claziss1-0/+11
generated by cgit v1.1 at 2024-12-25 11:02:41 +0000